Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T9,T10

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T3,T8
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T11,T12,T13
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T14,T15,T16
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T14,T17,T11

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	152276	114127	0	158
AlertKnownO_A	152968	115809	0	0
InBandInitRequest_A	152968	3984	0	0
InBandInitSequence_A	152968	407	0	0
InitReq_A	152968	743	0	0
IntegFailKnownO_A	152968	115809	0	0
NoSpuriousAlertsDuringInit_A	152968	15879	0	0
NoSpuriousPingOksDuringInit_A	152968	15457	0	0
PingDiffOk_A	152084	114925	0	0
PingOkBypassDuringInit_A	152968	47	0	40
PingOkKnownO_A	152968	115809	0	0
PingPKnownO_A	152968	115809	0	0
PingPending_A	152968	829	0	119
PingRequest0_A	152968	0	0	0
PingResponse0_A	152968	760	0	0
gen_async_assert.Alert_A	78975	1309	0	0
gen_async_assert.PingResponse1_A	78975	328	0	0
gen_async_assert.SigInt_A	78975	236	0	92
gen_sync_assert.Alert_A	73993	3142	0	0
gen_sync_assert.PingResponse1_A	73993	334	0	0
gen_sync_assert.SigInt_A	73993	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152276	114127	0	158
T1	1104	965	0	2
T2	1139	1002	0	2
T3	1175	1014	0	2
T7	1194	1018	0	2
T8	1013	928	0	2
T14	1157	1078	0	2
T17	1127	1028	0	2
T18	1116	1020	0	2
T19	1037	936	0	2
T20	1106	1036	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	115809	0	0
T1	1119	984	0	0
T2	1154	1021	0	0
T3	1190	1033	0	0
T7	1210	1038	0	0
T8	1028	945	0	0
T14	1171	1094	0	0
T17	1142	1045	0	0
T18	1132	1038	0	0
T19	1050	951	0	0
T20	1121	1053	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	3984	0	0
T1	1119	30	0	0
T2	1154	49	0	0
T3	1190	48	0	0
T7	1210	56	0	0
T8	1028	26	0	0
T14	1171	69	0	0
T17	1142	52	0	0
T18	1132	50	0	0
T19	1050	11	0	0
T20	1121	69	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	407	0	0
T2	1154	1	0	0
T3	1190	1	0	0
T7	1210	2	0	0
T8	1028	0	0	0
T11	1200	2	0	0
T14	1171	2	0	0
T17	1142	2	0	0
T18	1132	3	0	0
T19	1050	0	0	0
T20	1121	1	0	0
T21	0	1	0	0
T22	0	1	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	743	0	0
T1	1119	8	0	0
T2	1154	9	0	0
T3	1190	11	0	0
T7	1210	12	0	0
T8	1028	6	0	0
T14	1171	11	0	0
T17	1142	9	0	0
T18	1132	9	0	0
T19	1050	5	0	0
T20	1121	11	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	115809	0	0
T1	1119	984	0	0
T2	1154	1021	0	0
T3	1190	1033	0	0
T7	1210	1038	0	0
T8	1028	945	0	0
T14	1171	1094	0	0
T17	1142	1045	0	0
T18	1132	1038	0	0
T19	1050	951	0	0
T20	1121	1053	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	15879	0	0
T1	1119	158	0	0
T2	1154	192	0	0
T3	1190	238	0	0
T7	1210	255	0	0
T8	1028	120	0	0
T14	1171	222	0	0
T17	1142	182	0	0
T18	1132	184	0	0
T19	1050	108	0	0
T20	1121	212	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	15457	0	0
T1	1119	143	0	0
T2	1154	160	0	0
T3	1190	232	0	0
T7	1210	238	0	0
T8	1028	108	0	0
T14	1171	209	0	0
T17	1142	179	0	0
T18	1132	183	0	0
T19	1050	96	0	0
T20	1121	208	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152084	114925	0	0
T1	1103	968	0	0
T2	1136	1003	0	0
T3	1172	1015	0	0
T7	1197	1025	0	0
T8	1015	932	0	0
T14	1158	1081	0	0
T17	1129	1032	0	0
T18	1115	1021	0	0
T19	1034	935	0	0
T20	1103	1035	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	47	0	40
T1	0	0	0	1
T3	1190	1	0	0
T7	1210	2	0	0
T8	1028	0	0	0
T11	1200	1	0	0
T14	1171	0	0	0
T17	1142	0	0	0
T18	1132	1	0	0
T19	1050	0	0	0
T20	1121	0	0	0
T21	1071	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	115809	0	0
T1	1119	984	0	0
T2	1154	1021	0	0
T3	1190	1033	0	0
T7	1210	1038	0	0
T8	1028	945	0	0
T14	1171	1094	0	0
T17	1142	1045	0	0
T18	1132	1038	0	0
T19	1050	951	0	0
T20	1121	1053	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	115809	0	0
T1	1119	984	0	0
T2	1154	1021	0	0
T3	1190	1033	0	0
T7	1210	1038	0	0
T8	1028	945	0	0
T14	1171	1094	0	0
T17	1142	1045	0	0
T18	1132	1038	0	0
T19	1050	951	0	0
T20	1121	1053	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	829	0	119
T1	1119	11	0	1
T2	1154	11	0	1
T3	1190	11	0	1
T7	1210	11	0	1
T8	1028	11	0	1
T14	1171	11	0	1
T17	1142	11	0	1
T18	1132	11	0	1
T19	1050	11	0	1
T20	1121	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152968	760	0	0
T1	1119	9	0	0
T2	1154	10	0	0
T3	1190	9	0	0
T7	1210	9	0	0
T8	1028	10	0	0
T14	1171	10	0	0
T17	1142	8	0	0
T18	1132	10	0	0
T19	1050	10	0	0
T20	1121	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78975	1309	0	0
T1	1119	9	0	0
T2	1154	6	0	0
T3	1190	8	0	0
T7	1210	6	0	0
T8	1028	8	0	0
T14	1171	6	0	0
T17	1142	9	0	0
T18	1132	7	0	0
T19	1050	8	0	0
T20	1121	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78975	328	0	0
T1	1119	8	0	0
T2	1154	10	0	0
T3	1190	6	0	0
T7	1210	6	0	0
T8	1028	10	0	0
T14	1171	10	0	0
T17	1142	8	0	0
T18	1132	9	0	0
T19	1050	10	0	0
T20	1121	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78975	236	0	92
T1	1119	6	0	3
T2	1154	6	0	3
T3	1190	5	0	3
T7	1210	7	0	2
T8	1028	7	0	3
T14	1171	6	0	2
T17	1142	6	0	2
T18	1132	6	0	2
T19	1050	7	0	2
T20	1121	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73993	3142	0	0
T9	958	10	0	0
T27	950	9	0	0
T28	863	10	0	0
T29	979	9	0	0
T36	970	8	0	0
T37	1023	11	0	0
T38	800	12	0	0
T39	952	10	0	0
T40	928	7	0	0
T41	870	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73993	334	0	0
T9	958	8	0	0
T27	950	6	0	0
T28	863	6	0	0
T29	979	8	0	0
T36	970	8	0	0
T37	1023	8	0	0
T38	800	9	0	0
T39	952	10	0	0
T40	928	8	0	0
T41	870	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73993	40	0	0
T9	958	1	0	0
T27	950	1	0	0
T28	863	1	0	0
T29	979	1	0	0
T36	970	1	0	0
T37	1023	1	0	0
T38	800	1	0	0
T39	952	1	0	0
T40	928	1	0	0
T41	870	1	0	0