Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T6,T9	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T3,T6,T9
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T1,T2,T7
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T10,T11,T12

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	151198	113630	0	156
AlertKnownO_A	151883	115287	0	0
InBandInitRequest_A	151883	4326	0	0
InBandInitSequence_A	151883	447	0	0
InitReq_A	151883	781	0	0
IntegFailKnownO_A	151883	115287	0	0
NoSpuriousAlertsDuringInit_A	151883	16381	0	0
NoSpuriousPingOksDuringInit_A	151883	16068	0	0
PingDiffOk_A	150999	114403	0	0
PingOkBypassDuringInit_A	151883	50	0	40
PingOkKnownO_A	151883	115287	0	0
PingPKnownO_A	151883	115287	0	0
PingPending_A	151883	818	0	118
PingRequest0_A	151883	0	0	0
PingResponse0_A	151883	749	0	0
gen_async_assert.Alert_A	79046	1301	0	0
gen_async_assert.PingResponse1_A	79046	301	0	0
gen_async_assert.SigInt_A	79046	250	0	92
gen_sync_assert.Alert_A	72837	3051	0	0
gen_sync_assert.PingResponse1_A	72837	345	0	0
gen_sync_assert.SigInt_A	72837	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151198	113630	0	156
T1	1103	1003	0	2
T2	1161	1066	0	2
T3	1203	1054	0	2
T6	1153	1023	0	2
T7	1106	1020	0	2
T9	1157	980	0	2
T10	1136	1047	0	2
T11	1212	1058	0	2
T13	1057	971	0	2
T14	1073	1018	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	115287	0	0
T1	1118	1020	0	0
T2	1175	1082	0	0
T3	1219	1074	0	0
T6	1168	1042	0	0
T7	1121	1037	0	0
T9	1172	999	0	0
T10	1151	1064	0	0
T11	1228	1078	0	0
T13	1072	988	0	0
T14	1087	1034	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	4326	0	0
T1	1118	63	0	0
T2	1175	64	0	0
T3	1219	56	0	0
T6	1168	64	0	0
T7	1121	53	0	0
T9	1172	43	0	0
T10	1151	55	0	0
T11	1228	57	0	0
T13	1072	34	0	0
T14	1087	83	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	447	0	0
T1	1118	4	0	0
T2	1175	2	0	0
T3	1219	2	0	0
T6	1168	1	0	0
T7	1121	1	0	0
T8	0	2	0	0
T9	1172	2	0	0
T10	1151	1	0	0
T11	1228	3	0	0
T13	1072	0	0	0
T14	1087	4	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	781	0	0
T1	1118	8	0	0
T2	1175	13	0	0
T3	1219	9	0	0
T6	1168	10	0	0
T7	1121	11	0	0
T9	1172	7	0	0
T10	1151	11	0	0
T11	1228	10	0	0
T13	1072	7	0	0
T14	1087	13	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	115287	0	0
T1	1118	1020	0	0
T2	1175	1082	0	0
T3	1219	1074	0	0
T6	1168	1042	0	0
T7	1121	1037	0	0
T9	1172	999	0	0
T10	1151	1064	0	0
T11	1228	1078	0	0
T13	1072	988	0	0
T14	1087	1034	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	16381	0	0
T1	1118	162	0	0
T2	1175	253	0	0
T3	1219	192	0	0
T6	1168	209	0	0
T7	1121	214	0	0
T9	1172	153	0	0
T10	1151	214	0	0
T11	1228	208	0	0
T13	1072	143	0	0
T14	1087	252	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	16068	0	0
T1	1118	149	0	0
T2	1175	233	0	0
T3	1219	190	0	0
T6	1168	205	0	0
T7	1121	210	0	0
T9	1172	147	0	0
T10	1151	213	0	0
T11	1228	207	0	0
T13	1072	139	0	0
T14	1087	242	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150999	114403	0	0
T1	1101	1003	0	0
T2	1159	1066	0	0
T3	1202	1057	0	0
T6	1153	1027	0	0
T7	1103	1019	0	0
T9	1156	983	0	0
T10	1135	1048	0	0
T11	1211	1061	0	0
T13	1058	974	0	0
T14	1070	1017	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	50	0	40
T1	0	0	0	1
T6	1168	1	0	0
T7	1121	1	0	0
T8	1192	1	0	0
T9	1172	0	0	0
T10	1151	1	0	0
T11	1228	1	0	0
T13	1072	2	0	0
T14	1087	2	0	0
T15	1223	2	0	0
T16	1109	2	0	0
T17	0	2	0	0
T18	0	0	0	1
T19	0	0	0	1
T20	0	0	0	1
T21	0	0	0	1
T22	0	0	0	1
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	115287	0	0
T1	1118	1020	0	0
T2	1175	1082	0	0
T3	1219	1074	0	0
T6	1168	1042	0	0
T7	1121	1037	0	0
T9	1172	999	0	0
T10	1151	1064	0	0
T11	1228	1078	0	0
T13	1072	988	0	0
T14	1087	1034	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	115287	0	0
T1	1118	1020	0	0
T2	1175	1082	0	0
T3	1219	1074	0	0
T6	1168	1042	0	0
T7	1121	1037	0	0
T9	1172	999	0	0
T10	1151	1064	0	0
T11	1228	1078	0	0
T13	1072	988	0	0
T14	1087	1034	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	818	0	118
T1	1118	11	0	1
T2	1175	11	0	1
T3	1219	11	0	1
T6	1168	11	0	1
T7	1121	11	0	1
T9	1172	11	0	1
T10	1151	11	0	1
T11	1228	11	0	1
T13	1072	11	0	1
T14	1087	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151883	749	0	0
T1	1118	10	0	0
T2	1175	10	0	0
T3	1219	10	0	0
T6	1168	9	0	0
T7	1121	9	0	0
T9	1172	10	0	0
T10	1151	10	0	0
T11	1228	10	0	0
T13	1072	10	0	0
T14	1087	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79046	1301	0	0
T1	1118	8	0	0
T2	1175	4	0	0
T3	1219	8	0	0
T6	1168	7	0	0
T7	1121	8	0	0
T9	1172	9	0	0
T10	1151	7	0	0
T11	1228	6	0	0
T13	1072	9	0	0
T14	1087	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79046	301	0	0
T1	1118	9	0	0
T2	1175	8	0	0
T3	1219	9	0	0
T6	1168	7	0	0
T7	1121	7	0	0
T9	1172	7	0	0
T10	1151	9	0	0
T11	1228	9	0	0
T13	1072	7	0	0
T14	1087	4	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79046	250	0	92
T1	1118	7	0	3
T2	1175	5	0	2
T3	1219	6	0	2
T6	1168	6	0	2
T7	1121	7	0	3
T9	1172	7	0	2
T10	1151	7	0	3
T11	1228	6	0	2
T13	1072	6	0	3
T14	1087	8	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72837	3051	0	0
T18	1017	8	0	0
T19	936	8	0	0
T20	877	11	0	0
T21	879	10	0	0
T22	893	10	0	0
T27	774	9	0	0
T28	972	8	0	0
T29	922	8	0	0
T30	978	10	0	0
T31	1011	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72837	345	0	0
T18	1017	8	0	0
T19	936	7	0	0
T20	877	9	0	0
T21	879	8	0	0
T22	893	8	0	0
T27	774	10	0	0
T28	972	10	0	0
T29	922	8	0	0
T30	978	10	0	0
T31	1011	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72837	40	0	0
T18	1017	1	0	0
T19	936	1	0	0
T20	877	1	0	0
T21	879	1	0	0
T22	893	1	0	0
T27	774	1	0	0
T28	972	1	0	0
T29	922	1	0	0
T30	978	1	0	0
T31	1011	1	0	0