Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 79
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.32 88.32 100.00 100.00 91.67 91.67 100.00 100.00 75.00 75.00 95.83 95.83 67.44 67.44 /workspace/coverage/default/9.prim_async_alert.2727103539
92.39 4.07 100.00 0.00 93.75 2.08 100.00 0.00 85.71 10.71 95.83 0.00 79.07 11.63 /workspace/coverage/sync_alert/10.prim_sync_alert.4121459796
94.25 1.86 100.00 0.00 97.92 4.17 100.00 0.00 85.71 0.00 95.83 0.00 86.05 6.98 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.830616508
95.19 0.94 100.00 0.00 100.00 2.08 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/15.prim_async_alert.2270757532

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.2087218636
/workspace/coverage/default/1.prim_async_alert.1763951947
/workspace/coverage/default/10.prim_async_alert.3483809273
/workspace/coverage/default/11.prim_async_alert.354031174
/workspace/coverage/default/12.prim_async_alert.3299863325
/workspace/coverage/default/13.prim_async_alert.3514864104
/workspace/coverage/default/14.prim_async_alert.798702823
/workspace/coverage/default/16.prim_async_alert.1523122185
/workspace/coverage/default/17.prim_async_alert.883371375
/workspace/coverage/default/18.prim_async_alert.1173939493
/workspace/coverage/default/19.prim_async_alert.1136922357
/workspace/coverage/default/2.prim_async_alert.3596268934
/workspace/coverage/default/4.prim_async_alert.1842278911
/workspace/coverage/default/5.prim_async_alert.4020787137
/workspace/coverage/default/6.prim_async_alert.1379660475
/workspace/coverage/default/7.prim_async_alert.2323136915
/workspace/coverage/default/8.prim_async_alert.3271026138
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4124157881
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2724299655
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4148984926
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.118932949
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.501226578
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.664426686
/workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2610499000
/workspace/coverage/fatal_alert/16.prim_async_fatal_alert.920990097
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1619812045
/workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1006648910
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3633520123
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1704067015
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1042853398
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1627468367
/workspace/coverage/fatal_alert/5.prim_async_fatal_alert.627367181
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1116386718
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1722696718
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1974148521
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2904275214
/workspace/coverage/sync_alert/0.prim_sync_alert.129091872
/workspace/coverage/sync_alert/1.prim_sync_alert.75879172
/workspace/coverage/sync_alert/11.prim_sync_alert.3192277796
/workspace/coverage/sync_alert/12.prim_sync_alert.1202516476
/workspace/coverage/sync_alert/13.prim_sync_alert.2245339399
/workspace/coverage/sync_alert/14.prim_sync_alert.3181795701
/workspace/coverage/sync_alert/15.prim_sync_alert.1890004403
/workspace/coverage/sync_alert/16.prim_sync_alert.1077598143
/workspace/coverage/sync_alert/17.prim_sync_alert.1808650106
/workspace/coverage/sync_alert/18.prim_sync_alert.1337673586
/workspace/coverage/sync_alert/19.prim_sync_alert.1509928362
/workspace/coverage/sync_alert/2.prim_sync_alert.2158317211
/workspace/coverage/sync_alert/3.prim_sync_alert.1839805949
/workspace/coverage/sync_alert/4.prim_sync_alert.1613122311
/workspace/coverage/sync_alert/5.prim_sync_alert.1599743787
/workspace/coverage/sync_alert/6.prim_sync_alert.1329117911
/workspace/coverage/sync_alert/7.prim_sync_alert.1191370606
/workspace/coverage/sync_alert/8.prim_sync_alert.3129086245
/workspace/coverage/sync_alert/9.prim_sync_alert.2542521945
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.33865174
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.369883824
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2123848828
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4194763241
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.572974168
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3885579137
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3419698567
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2287903046
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.897052254
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.24100096
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.537614369
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.894567213
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3486397975
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2790847734
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4233133405
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.789052508
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3491305527
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3097463234
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.860877842
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2919729598



Total test records in report: 79
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.prim_async_alert.2270757532 Jul 20 04:23:39 PM PDT 24 Jul 20 04:23:40 PM PDT 24 12053690 ps
T2 /workspace/coverage/default/8.prim_async_alert.3271026138 Jul 20 04:22:12 PM PDT 24 Jul 20 04:22:12 PM PDT 24 11144442 ps
T3 /workspace/coverage/default/1.prim_async_alert.1763951947 Jul 20 04:24:27 PM PDT 24 Jul 20 04:24:28 PM PDT 24 10508507 ps
T9 /workspace/coverage/default/19.prim_async_alert.1136922357 Jul 20 04:24:11 PM PDT 24 Jul 20 04:24:13 PM PDT 24 11651291 ps
T19 /workspace/coverage/default/4.prim_async_alert.1842278911 Jul 20 04:23:50 PM PDT 24 Jul 20 04:23:51 PM PDT 24 10827994 ps
T11 /workspace/coverage/default/9.prim_async_alert.2727103539 Jul 20 04:24:39 PM PDT 24 Jul 20 04:24:40 PM PDT 24 11891935 ps
T20 /workspace/coverage/default/5.prim_async_alert.4020787137 Jul 20 04:24:21 PM PDT 24 Jul 20 04:24:22 PM PDT 24 10817591 ps
T17 /workspace/coverage/default/18.prim_async_alert.1173939493 Jul 20 04:24:11 PM PDT 24 Jul 20 04:24:12 PM PDT 24 10438035 ps
T7 /workspace/coverage/default/0.prim_async_alert.2087218636 Jul 20 04:23:53 PM PDT 24 Jul 20 04:23:54 PM PDT 24 10879890 ps
T21 /workspace/coverage/default/12.prim_async_alert.3299863325 Jul 20 04:24:22 PM PDT 24 Jul 20 04:24:24 PM PDT 24 11164886 ps
T23 /workspace/coverage/default/7.prim_async_alert.2323136915 Jul 20 04:24:21 PM PDT 24 Jul 20 04:24:22 PM PDT 24 11183934 ps
T22 /workspace/coverage/default/11.prim_async_alert.354031174 Jul 20 04:20:34 PM PDT 24 Jul 20 04:20:35 PM PDT 24 10742970 ps
T14 /workspace/coverage/default/17.prim_async_alert.883371375 Jul 20 04:19:49 PM PDT 24 Jul 20 04:19:50 PM PDT 24 11094073 ps
T15 /workspace/coverage/default/14.prim_async_alert.798702823 Jul 20 04:24:46 PM PDT 24 Jul 20 04:24:48 PM PDT 24 11133668 ps
T8 /workspace/coverage/default/16.prim_async_alert.1523122185 Jul 20 04:21:28 PM PDT 24 Jul 20 04:21:28 PM PDT 24 12070809 ps
T43 /workspace/coverage/default/13.prim_async_alert.3514864104 Jul 20 04:19:50 PM PDT 24 Jul 20 04:19:51 PM PDT 24 11225313 ps
T44 /workspace/coverage/default/10.prim_async_alert.3483809273 Jul 20 04:24:39 PM PDT 24 Jul 20 04:24:40 PM PDT 24 11307843 ps
T45 /workspace/coverage/default/6.prim_async_alert.1379660475 Jul 20 04:23:33 PM PDT 24 Jul 20 04:23:34 PM PDT 24 10943738 ps
T46 /workspace/coverage/default/2.prim_async_alert.3596268934 Jul 20 04:23:53 PM PDT 24 Jul 20 04:23:54 PM PDT 24 12485748 ps
T37 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3633520123 Jul 20 05:45:17 PM PDT 24 Jul 20 05:45:23 PM PDT 24 32517515 ps
T4 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.830616508 Jul 20 05:45:12 PM PDT 24 Jul 20 05:45:13 PM PDT 24 30253283 ps
T38 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2724299655 Jul 20 05:45:10 PM PDT 24 Jul 20 05:45:11 PM PDT 24 30779661 ps
T39 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4124157881 Jul 20 05:45:09 PM PDT 24 Jul 20 05:45:10 PM PDT 24 30177249 ps
T5 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1627468367 Jul 20 05:45:11 PM PDT 24 Jul 20 05:45:12 PM PDT 24 29446699 ps
T40 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.920990097 Jul 20 05:45:11 PM PDT 24 Jul 20 05:45:12 PM PDT 24 32340497 ps
T16 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1116386718 Jul 20 05:45:10 PM PDT 24 Jul 20 05:45:11 PM PDT 24 30442170 ps
T18 /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1006648910 Jul 20 05:45:13 PM PDT 24 Jul 20 05:45:14 PM PDT 24 29717403 ps
T41 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2904275214 Jul 20 05:45:13 PM PDT 24 Jul 20 05:45:14 PM PDT 24 29281219 ps
T42 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1704067015 Jul 20 05:45:22 PM PDT 24 Jul 20 05:45:23 PM PDT 24 29856414 ps
T47 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1722696718 Jul 20 05:45:14 PM PDT 24 Jul 20 05:45:14 PM PDT 24 31058084 ps
T12 /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.627367181 Jul 20 05:45:17 PM PDT 24 Jul 20 05:45:18 PM PDT 24 31595097 ps
T48 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4148984926 Jul 20 05:45:11 PM PDT 24 Jul 20 05:45:12 PM PDT 24 31730377 ps
T49 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1974148521 Jul 20 05:45:16 PM PDT 24 Jul 20 05:45:17 PM PDT 24 31312597 ps
T50 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.118932949 Jul 20 05:45:15 PM PDT 24 Jul 20 05:45:16 PM PDT 24 29125627 ps
T51 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.664426686 Jul 20 05:45:17 PM PDT 24 Jul 20 05:45:18 PM PDT 24 28913640 ps
T35 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2610499000 Jul 20 05:45:17 PM PDT 24 Jul 20 05:45:18 PM PDT 24 30841151 ps
T52 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.501226578 Jul 20 05:45:12 PM PDT 24 Jul 20 05:45:13 PM PDT 24 27522430 ps
T36 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1619812045 Jul 20 05:45:10 PM PDT 24 Jul 20 05:45:10 PM PDT 24 29522218 ps
T6 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1042853398 Jul 20 05:45:15 PM PDT 24 Jul 20 05:45:16 PM PDT 24 31037402 ps
T32 /workspace/coverage/sync_alert/13.prim_sync_alert.2245339399 Jul 20 05:24:46 PM PDT 24 Jul 20 05:24:48 PM PDT 24 10870424 ps
T10 /workspace/coverage/sync_alert/10.prim_sync_alert.4121459796 Jul 20 05:24:47 PM PDT 24 Jul 20 05:24:48 PM PDT 24 9078812 ps
T24 /workspace/coverage/sync_alert/0.prim_sync_alert.129091872 Jul 20 05:24:43 PM PDT 24 Jul 20 05:24:44 PM PDT 24 9157333 ps
T25 /workspace/coverage/sync_alert/16.prim_sync_alert.1077598143 Jul 20 05:24:47 PM PDT 24 Jul 20 05:24:48 PM PDT 24 10013858 ps
T26 /workspace/coverage/sync_alert/8.prim_sync_alert.3129086245 Jul 20 05:24:50 PM PDT 24 Jul 20 05:24:51 PM PDT 24 8807685 ps
T27 /workspace/coverage/sync_alert/4.prim_sync_alert.1613122311 Jul 20 05:24:45 PM PDT 24 Jul 20 05:24:46 PM PDT 24 9050631 ps
T33 /workspace/coverage/sync_alert/7.prim_sync_alert.1191370606 Jul 20 05:24:47 PM PDT 24 Jul 20 05:24:48 PM PDT 24 9393939 ps
T34 /workspace/coverage/sync_alert/15.prim_sync_alert.1890004403 Jul 20 05:24:47 PM PDT 24 Jul 20 05:24:49 PM PDT 24 9065379 ps
T13 /workspace/coverage/sync_alert/14.prim_sync_alert.3181795701 Jul 20 05:24:46 PM PDT 24 Jul 20 05:24:48 PM PDT 24 10314970 ps
T28 /workspace/coverage/sync_alert/6.prim_sync_alert.1329117911 Jul 20 05:24:48 PM PDT 24 Jul 20 05:24:50 PM PDT 24 9052554 ps
T29 /workspace/coverage/sync_alert/11.prim_sync_alert.3192277796 Jul 20 05:24:47 PM PDT 24 Jul 20 05:24:49 PM PDT 24 8164641 ps
T53 /workspace/coverage/sync_alert/12.prim_sync_alert.1202516476 Jul 20 05:24:49 PM PDT 24 Jul 20 05:24:50 PM PDT 24 7855361 ps
T54 /workspace/coverage/sync_alert/18.prim_sync_alert.1337673586 Jul 20 05:24:49 PM PDT 24 Jul 20 05:24:51 PM PDT 24 10222603 ps
T30 /workspace/coverage/sync_alert/3.prim_sync_alert.1839805949 Jul 20 05:24:38 PM PDT 24 Jul 20 05:24:40 PM PDT 24 9918412 ps
T55 /workspace/coverage/sync_alert/2.prim_sync_alert.2158317211 Jul 20 05:24:45 PM PDT 24 Jul 20 05:24:46 PM PDT 24 8570803 ps
T31 /workspace/coverage/sync_alert/17.prim_sync_alert.1808650106 Jul 20 05:24:48 PM PDT 24 Jul 20 05:24:50 PM PDT 24 9058756 ps
T56 /workspace/coverage/sync_alert/5.prim_sync_alert.1599743787 Jul 20 05:24:48 PM PDT 24 Jul 20 05:24:49 PM PDT 24 9468449 ps
T57 /workspace/coverage/sync_alert/19.prim_sync_alert.1509928362 Jul 20 05:24:48 PM PDT 24 Jul 20 05:24:50 PM PDT 24 8937671 ps
T58 /workspace/coverage/sync_alert/1.prim_sync_alert.75879172 Jul 20 05:24:41 PM PDT 24 Jul 20 05:24:44 PM PDT 24 9560132 ps
T59 /workspace/coverage/sync_alert/9.prim_sync_alert.2542521945 Jul 20 05:24:49 PM PDT 24 Jul 20 05:24:51 PM PDT 24 9146249 ps
T60 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.860877842 Jul 20 05:45:44 PM PDT 24 Jul 20 05:45:46 PM PDT 24 28858637 ps
T61 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.897052254 Jul 20 05:45:46 PM PDT 24 Jul 20 05:45:47 PM PDT 24 27971040 ps
T62 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2123848828 Jul 20 05:45:29 PM PDT 24 Jul 20 05:45:30 PM PDT 24 28171018 ps
T63 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3419698567 Jul 20 05:45:45 PM PDT 24 Jul 20 05:45:46 PM PDT 24 27767749 ps
T64 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3885579137 Jul 20 05:45:40 PM PDT 24 Jul 20 05:45:41 PM PDT 24 28538798 ps
T65 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2919729598 Jul 20 05:45:40 PM PDT 24 Jul 20 05:45:41 PM PDT 24 26850531 ps
T66 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2790847734 Jul 20 05:45:33 PM PDT 24 Jul 20 05:45:34 PM PDT 24 27909633 ps
T67 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.789052508 Jul 20 05:45:35 PM PDT 24 Jul 20 05:45:37 PM PDT 24 29249257 ps
T68 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.894567213 Jul 20 05:45:29 PM PDT 24 Jul 20 05:45:30 PM PDT 24 27738993 ps
T69 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2287903046 Jul 20 05:45:33 PM PDT 24 Jul 20 05:45:34 PM PDT 24 28467364 ps
T70 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.24100096 Jul 20 05:45:31 PM PDT 24 Jul 20 05:45:32 PM PDT 24 27942980 ps
T71 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4194763241 Jul 20 05:45:50 PM PDT 24 Jul 20 05:45:55 PM PDT 24 27658664 ps
T72 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.33865174 Jul 20 05:45:40 PM PDT 24 Jul 20 05:45:41 PM PDT 24 27714590 ps
T73 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3491305527 Jul 20 05:45:46 PM PDT 24 Jul 20 05:45:49 PM PDT 24 27867696 ps
T74 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3097463234 Jul 20 05:45:31 PM PDT 24 Jul 20 05:45:32 PM PDT 24 29566545 ps
T75 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4233133405 Jul 20 05:45:31 PM PDT 24 Jul 20 05:45:33 PM PDT 24 27433612 ps
T76 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.369883824 Jul 20 05:45:45 PM PDT 24 Jul 20 05:45:47 PM PDT 24 26987720 ps
T77 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.537614369 Jul 20 05:45:34 PM PDT 24 Jul 20 05:45:36 PM PDT 24 27300360 ps
T78 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3486397975 Jul 20 05:45:31 PM PDT 24 Jul 20 05:45:32 PM PDT 24 28483324 ps
T79 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.572974168 Jul 20 05:45:27 PM PDT 24 Jul 20 05:45:28 PM PDT 24 28074537 ps

Test location /workspace/coverage/default/9.prim_async_alert.2727103539
Short name T11
Test name
Test status
Simulation time 11891935 ps
CPU time 0.38 seconds
Started Jul 20 04:24:39 PM PDT 24
Finished Jul 20 04:24:40 PM PDT 24
Peak memory 145764 kb
Host smart-0708efed-345f-4205-a4fa-b824b4b52a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727103539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.2727103539
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.4121459796
Short name T10
Test name
Test status
Simulation time 9078812 ps
CPU time 0.37 seconds
Started Jul 20 05:24:47 PM PDT 24
Finished Jul 20 05:24:48 PM PDT 24
Peak memory 145568 kb
Host smart-59887420-7bd8-4b6b-b9f9-76a7a5c6dfe0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4121459796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.4121459796
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.830616508
Short name T4
Test name
Test status
Simulation time 30253283 ps
CPU time 0.4 seconds
Started Jul 20 05:45:12 PM PDT 24
Finished Jul 20 05:45:13 PM PDT 24
Peak memory 145336 kb
Host smart-2ebdd738-37a2-4918-938b-651018ed63dc
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=830616508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.830616508
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.2270757532
Short name T1
Test name
Test status
Simulation time 12053690 ps
CPU time 0.45 seconds
Started Jul 20 04:23:39 PM PDT 24
Finished Jul 20 04:23:40 PM PDT 24
Peak memory 145660 kb
Host smart-967fc81a-fe8d-4329-8c21-0312bad6632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270757532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.2270757532
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.2087218636
Short name T7
Test name
Test status
Simulation time 10879890 ps
CPU time 0.46 seconds
Started Jul 20 04:23:53 PM PDT 24
Finished Jul 20 04:23:54 PM PDT 24
Peak memory 142812 kb
Host smart-cd3c8c1a-0321-474f-be7b-0d0978d5b879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087218636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2087218636
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.1763951947
Short name T3
Test name
Test status
Simulation time 10508507 ps
CPU time 0.46 seconds
Started Jul 20 04:24:27 PM PDT 24
Finished Jul 20 04:24:28 PM PDT 24
Peak memory 145168 kb
Host smart-a144e339-ee79-45ac-8e7d-3e3e43703c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763951947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1763951947
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.3483809273
Short name T44
Test name
Test status
Simulation time 11307843 ps
CPU time 0.37 seconds
Started Jul 20 04:24:39 PM PDT 24
Finished Jul 20 04:24:40 PM PDT 24
Peak memory 145224 kb
Host smart-349fb947-3647-4553-83fe-cdcdadc315dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483809273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.3483809273
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.354031174
Short name T22
Test name
Test status
Simulation time 10742970 ps
CPU time 0.43 seconds
Started Jul 20 04:20:34 PM PDT 24
Finished Jul 20 04:20:35 PM PDT 24
Peak memory 145608 kb
Host smart-65d7ea6f-0a78-4c53-b0af-cf6aff51a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354031174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.354031174
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.3299863325
Short name T21
Test name
Test status
Simulation time 11164886 ps
CPU time 0.39 seconds
Started Jul 20 04:24:22 PM PDT 24
Finished Jul 20 04:24:24 PM PDT 24
Peak memory 145284 kb
Host smart-4f38adb1-4075-436a-9dae-fe5566590df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299863325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.3299863325
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.3514864104
Short name T43
Test name
Test status
Simulation time 11225313 ps
CPU time 0.39 seconds
Started Jul 20 04:19:50 PM PDT 24
Finished Jul 20 04:19:51 PM PDT 24
Peak memory 145816 kb
Host smart-5769f80e-96ec-4255-ae48-bd826d92724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514864104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.3514864104
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.798702823
Short name T15
Test name
Test status
Simulation time 11133668 ps
CPU time 0.41 seconds
Started Jul 20 04:24:46 PM PDT 24
Finished Jul 20 04:24:48 PM PDT 24
Peak memory 145880 kb
Host smart-ff9035f0-486f-43bd-8f84-f1dc2f3569d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798702823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.798702823
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.1523122185
Short name T8
Test name
Test status
Simulation time 12070809 ps
CPU time 0.4 seconds
Started Jul 20 04:21:28 PM PDT 24
Finished Jul 20 04:21:28 PM PDT 24
Peak memory 145624 kb
Host smart-d85b4ef3-9c8e-4523-a56d-6c65527a31bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523122185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.1523122185
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.883371375
Short name T14
Test name
Test status
Simulation time 11094073 ps
CPU time 0.4 seconds
Started Jul 20 04:19:49 PM PDT 24
Finished Jul 20 04:19:50 PM PDT 24
Peak memory 145620 kb
Host smart-cb03b47b-facf-4866-baef-92bd5f83a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883371375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.883371375
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.1173939493
Short name T17
Test name
Test status
Simulation time 10438035 ps
CPU time 0.38 seconds
Started Jul 20 04:24:11 PM PDT 24
Finished Jul 20 04:24:12 PM PDT 24
Peak memory 145920 kb
Host smart-e979a2bc-97b0-49f0-ad44-a54ca8c2ee97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173939493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.1173939493
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.1136922357
Short name T9
Test name
Test status
Simulation time 11651291 ps
CPU time 0.39 seconds
Started Jul 20 04:24:11 PM PDT 24
Finished Jul 20 04:24:13 PM PDT 24
Peak memory 145376 kb
Host smart-ecffee67-add1-4147-939b-292360bc400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136922357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.1136922357
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3596268934
Short name T46
Test name
Test status
Simulation time 12485748 ps
CPU time 0.47 seconds
Started Jul 20 04:23:53 PM PDT 24
Finished Jul 20 04:23:54 PM PDT 24
Peak memory 142808 kb
Host smart-2ca13385-8169-4773-8395-6631949f3b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596268934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3596268934
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.1842278911
Short name T19
Test name
Test status
Simulation time 10827994 ps
CPU time 0.38 seconds
Started Jul 20 04:23:50 PM PDT 24
Finished Jul 20 04:23:51 PM PDT 24
Peak memory 145440 kb
Host smart-c5bc88ff-d98f-4ff0-a6d6-312904ec4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842278911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.1842278911
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/5.prim_async_alert.4020787137
Short name T20
Test name
Test status
Simulation time 10817591 ps
CPU time 0.37 seconds
Started Jul 20 04:24:21 PM PDT 24
Finished Jul 20 04:24:22 PM PDT 24
Peak memory 145328 kb
Host smart-648b4999-1543-465c-9ca1-b9b63b072159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020787137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.4020787137
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.1379660475
Short name T45
Test name
Test status
Simulation time 10943738 ps
CPU time 0.41 seconds
Started Jul 20 04:23:33 PM PDT 24
Finished Jul 20 04:23:34 PM PDT 24
Peak memory 145264 kb
Host smart-d66a0aef-98a5-40fe-95f2-5873b6d17bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379660475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.1379660475
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.2323136915
Short name T23
Test name
Test status
Simulation time 11183934 ps
CPU time 0.38 seconds
Started Jul 20 04:24:21 PM PDT 24
Finished Jul 20 04:24:22 PM PDT 24
Peak memory 145400 kb
Host smart-8fcf2d2b-a057-4139-9175-207579499f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323136915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.2323136915
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.3271026138
Short name T2
Test name
Test status
Simulation time 11144442 ps
CPU time 0.38 seconds
Started Jul 20 04:22:12 PM PDT 24
Finished Jul 20 04:22:12 PM PDT 24
Peak memory 145672 kb
Host smart-6de28c1a-f0e7-4a88-b8bb-1f6f61b49e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271026138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.3271026138
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.4124157881
Short name T39
Test name
Test status
Simulation time 30177249 ps
CPU time 0.4 seconds
Started Jul 20 05:45:09 PM PDT 24
Finished Jul 20 05:45:10 PM PDT 24
Peak memory 145236 kb
Host smart-8ec34d91-63b4-4156-b400-35198a0f9b47
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4124157881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.4124157881
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.2724299655
Short name T38
Test name
Test status
Simulation time 30779661 ps
CPU time 0.4 seconds
Started Jul 20 05:45:10 PM PDT 24
Finished Jul 20 05:45:11 PM PDT 24
Peak memory 145236 kb
Host smart-51904fd3-b152-4c6e-93e6-37fa69397dec
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2724299655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2724299655
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.4148984926
Short name T48
Test name
Test status
Simulation time 31730377 ps
CPU time 0.41 seconds
Started Jul 20 05:45:11 PM PDT 24
Finished Jul 20 05:45:12 PM PDT 24
Peak memory 145332 kb
Host smart-c7898725-e1a9-4f41-af68-a3855d7f58d2
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4148984926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.4148984926
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.118932949
Short name T50
Test name
Test status
Simulation time 29125627 ps
CPU time 0.39 seconds
Started Jul 20 05:45:15 PM PDT 24
Finished Jul 20 05:45:16 PM PDT 24
Peak memory 145276 kb
Host smart-40a4b47b-d0e7-4bac-9748-ea185483788d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=118932949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.118932949
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.501226578
Short name T52
Test name
Test status
Simulation time 27522430 ps
CPU time 0.4 seconds
Started Jul 20 05:45:12 PM PDT 24
Finished Jul 20 05:45:13 PM PDT 24
Peak memory 145192 kb
Host smart-d0f412da-622e-46ed-953c-8ad7fdc5cf30
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=501226578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.501226578
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.664426686
Short name T51
Test name
Test status
Simulation time 28913640 ps
CPU time 0.41 seconds
Started Jul 20 05:45:17 PM PDT 24
Finished Jul 20 05:45:18 PM PDT 24
Peak memory 145308 kb
Host smart-a0a976c0-e148-45d4-8c34-b35fb37bbffb
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=664426686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.664426686
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.2610499000
Short name T35
Test name
Test status
Simulation time 30841151 ps
CPU time 0.41 seconds
Started Jul 20 05:45:17 PM PDT 24
Finished Jul 20 05:45:18 PM PDT 24
Peak memory 145300 kb
Host smart-bfb5e532-c813-4d23-9e0b-811bb643b8ac
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2610499000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.2610499000
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.920990097
Short name T40
Test name
Test status
Simulation time 32340497 ps
CPU time 0.4 seconds
Started Jul 20 05:45:11 PM PDT 24
Finished Jul 20 05:45:12 PM PDT 24
Peak memory 145244 kb
Host smart-c33b5928-f849-4114-82fd-b030bf5c45b3
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=920990097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.920990097
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.1619812045
Short name T36
Test name
Test status
Simulation time 29522218 ps
CPU time 0.44 seconds
Started Jul 20 05:45:10 PM PDT 24
Finished Jul 20 05:45:10 PM PDT 24
Peak memory 145280 kb
Host smart-29dab2dc-98fa-43f8-a63c-96f3c549a44a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1619812045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.1619812045
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/18.prim_async_fatal_alert.1006648910
Short name T18
Test name
Test status
Simulation time 29717403 ps
CPU time 0.39 seconds
Started Jul 20 05:45:13 PM PDT 24
Finished Jul 20 05:45:14 PM PDT 24
Peak memory 145236 kb
Host smart-b8c4aec6-31d0-4611-80ae-cd4c693ae189
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1006648910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_async_fatal_alert.1006648910
Directory /workspace/18.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3633520123
Short name T37
Test name
Test status
Simulation time 32517515 ps
CPU time 0.42 seconds
Started Jul 20 05:45:17 PM PDT 24
Finished Jul 20 05:45:23 PM PDT 24
Peak memory 145300 kb
Host smart-38459d5d-2143-40cc-8622-d31f14699ba5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3633520123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3633520123
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.1704067015
Short name T42
Test name
Test status
Simulation time 29856414 ps
CPU time 0.39 seconds
Started Jul 20 05:45:22 PM PDT 24
Finished Jul 20 05:45:23 PM PDT 24
Peak memory 145332 kb
Host smart-fecb2eee-8694-4b1b-8aaa-008345e49aff
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1704067015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.1704067015
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.1042853398
Short name T6
Test name
Test status
Simulation time 31037402 ps
CPU time 0.41 seconds
Started Jul 20 05:45:15 PM PDT 24
Finished Jul 20 05:45:16 PM PDT 24
Peak memory 145300 kb
Host smart-a9c565ee-97c9-4573-adbd-aea2508b1a8c
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1042853398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1042853398
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.1627468367
Short name T5
Test name
Test status
Simulation time 29446699 ps
CPU time 0.4 seconds
Started Jul 20 05:45:11 PM PDT 24
Finished Jul 20 05:45:12 PM PDT 24
Peak memory 145300 kb
Host smart-1a342057-5765-421b-be93-cce0bc58b12e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1627468367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.1627468367
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/5.prim_async_fatal_alert.627367181
Short name T12
Test name
Test status
Simulation time 31595097 ps
CPU time 0.41 seconds
Started Jul 20 05:45:17 PM PDT 24
Finished Jul 20 05:45:18 PM PDT 24
Peak memory 145332 kb
Host smart-2d163a70-049b-463b-944b-652878a15b8d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=627367181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.627367181
Directory /workspace/5.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.1116386718
Short name T16
Test name
Test status
Simulation time 30442170 ps
CPU time 0.42 seconds
Started Jul 20 05:45:10 PM PDT 24
Finished Jul 20 05:45:11 PM PDT 24
Peak memory 145240 kb
Host smart-552f6332-f6ee-4aee-b9d4-3f7ce93c0260
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1116386718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1116386718
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1722696718
Short name T47
Test name
Test status
Simulation time 31058084 ps
CPU time 0.39 seconds
Started Jul 20 05:45:14 PM PDT 24
Finished Jul 20 05:45:14 PM PDT 24
Peak memory 145336 kb
Host smart-34cedad1-d41e-4e73-be26-afa79eccd64a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1722696718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1722696718
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.1974148521
Short name T49
Test name
Test status
Simulation time 31312597 ps
CPU time 0.4 seconds
Started Jul 20 05:45:16 PM PDT 24
Finished Jul 20 05:45:17 PM PDT 24
Peak memory 145300 kb
Host smart-2358bbb8-043d-4e43-aaaf-46813fd26499
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1974148521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.1974148521
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.2904275214
Short name T41
Test name
Test status
Simulation time 29281219 ps
CPU time 0.46 seconds
Started Jul 20 05:45:13 PM PDT 24
Finished Jul 20 05:45:14 PM PDT 24
Peak memory 145244 kb
Host smart-190c6615-f242-4486-88a7-7504b1eab202
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2904275214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2904275214
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.129091872
Short name T24
Test name
Test status
Simulation time 9157333 ps
CPU time 0.4 seconds
Started Jul 20 05:24:43 PM PDT 24
Finished Jul 20 05:24:44 PM PDT 24
Peak memory 145592 kb
Host smart-b80efb3d-fcf9-41b6-a50a-75c24d48939e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=129091872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.129091872
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.75879172
Short name T58
Test name
Test status
Simulation time 9560132 ps
CPU time 0.38 seconds
Started Jul 20 05:24:41 PM PDT 24
Finished Jul 20 05:24:44 PM PDT 24
Peak memory 145552 kb
Host smart-bb256587-e8af-427b-8316-7bc3f6a1dcad
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=75879172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.75879172
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.3192277796
Short name T29
Test name
Test status
Simulation time 8164641 ps
CPU time 0.39 seconds
Started Jul 20 05:24:47 PM PDT 24
Finished Jul 20 05:24:49 PM PDT 24
Peak memory 145508 kb
Host smart-a374d406-3c8c-46ed-9e0c-515abf08e68d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3192277796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.3192277796
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.1202516476
Short name T53
Test name
Test status
Simulation time 7855361 ps
CPU time 0.38 seconds
Started Jul 20 05:24:49 PM PDT 24
Finished Jul 20 05:24:50 PM PDT 24
Peak memory 145512 kb
Host smart-f7b223ac-7b60-4e3c-90f2-3366aa77b494
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1202516476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.1202516476
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2245339399
Short name T32
Test name
Test status
Simulation time 10870424 ps
CPU time 0.38 seconds
Started Jul 20 05:24:46 PM PDT 24
Finished Jul 20 05:24:48 PM PDT 24
Peak memory 145568 kb
Host smart-f016a319-4667-40cd-a589-6b6d7dbf031d
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2245339399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2245339399
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.3181795701
Short name T13
Test name
Test status
Simulation time 10314970 ps
CPU time 0.39 seconds
Started Jul 20 05:24:46 PM PDT 24
Finished Jul 20 05:24:48 PM PDT 24
Peak memory 145596 kb
Host smart-fda3434e-56f9-4f89-a99d-4190a3bde897
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3181795701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.3181795701
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.1890004403
Short name T34
Test name
Test status
Simulation time 9065379 ps
CPU time 0.4 seconds
Started Jul 20 05:24:47 PM PDT 24
Finished Jul 20 05:24:49 PM PDT 24
Peak memory 145500 kb
Host smart-4eb5429d-24f6-4e74-85e5-26fa58d42e8f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1890004403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.1890004403
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.1077598143
Short name T25
Test name
Test status
Simulation time 10013858 ps
CPU time 0.39 seconds
Started Jul 20 05:24:47 PM PDT 24
Finished Jul 20 05:24:48 PM PDT 24
Peak memory 145496 kb
Host smart-39b9989a-8a9a-49f2-a2db-025be1bf3e06
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1077598143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.1077598143
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.1808650106
Short name T31
Test name
Test status
Simulation time 9058756 ps
CPU time 0.39 seconds
Started Jul 20 05:24:48 PM PDT 24
Finished Jul 20 05:24:50 PM PDT 24
Peak memory 145560 kb
Host smart-47d0a62c-d4ac-4b46-ad51-6925562c4fef
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1808650106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.1808650106
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1337673586
Short name T54
Test name
Test status
Simulation time 10222603 ps
CPU time 0.39 seconds
Started Jul 20 05:24:49 PM PDT 24
Finished Jul 20 05:24:51 PM PDT 24
Peak memory 145508 kb
Host smart-42adfda3-e8d5-487a-9516-2d38c7961ade
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1337673586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1337673586
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.1509928362
Short name T57
Test name
Test status
Simulation time 8937671 ps
CPU time 0.4 seconds
Started Jul 20 05:24:48 PM PDT 24
Finished Jul 20 05:24:50 PM PDT 24
Peak memory 145580 kb
Host smart-a9f7762b-f227-4b9b-99ea-ffd3f3281db9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1509928362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.1509928362
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.2158317211
Short name T55
Test name
Test status
Simulation time 8570803 ps
CPU time 0.37 seconds
Started Jul 20 05:24:45 PM PDT 24
Finished Jul 20 05:24:46 PM PDT 24
Peak memory 145492 kb
Host smart-d7faff01-98b0-4b70-818d-90948a46b09a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2158317211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.2158317211
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1839805949
Short name T30
Test name
Test status
Simulation time 9918412 ps
CPU time 0.39 seconds
Started Jul 20 05:24:38 PM PDT 24
Finished Jul 20 05:24:40 PM PDT 24
Peak memory 145508 kb
Host smart-0a5f9d8d-1514-46cd-90d2-55c5c4d28b8a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1839805949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1839805949
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.1613122311
Short name T27
Test name
Test status
Simulation time 9050631 ps
CPU time 0.38 seconds
Started Jul 20 05:24:45 PM PDT 24
Finished Jul 20 05:24:46 PM PDT 24
Peak memory 145552 kb
Host smart-8b1818f6-5b33-4662-95bb-3a5f7576de54
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1613122311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.1613122311
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1599743787
Short name T56
Test name
Test status
Simulation time 9468449 ps
CPU time 0.39 seconds
Started Jul 20 05:24:48 PM PDT 24
Finished Jul 20 05:24:49 PM PDT 24
Peak memory 145508 kb
Host smart-2962b8b1-b54f-4c18-9448-8aa5f6db40c5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1599743787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1599743787
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.1329117911
Short name T28
Test name
Test status
Simulation time 9052554 ps
CPU time 0.38 seconds
Started Jul 20 05:24:48 PM PDT 24
Finished Jul 20 05:24:50 PM PDT 24
Peak memory 145492 kb
Host smart-8ca4e954-70ad-43bf-ab1a-02ed1ca05ac7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1329117911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.1329117911
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.1191370606
Short name T33
Test name
Test status
Simulation time 9393939 ps
CPU time 0.4 seconds
Started Jul 20 05:24:47 PM PDT 24
Finished Jul 20 05:24:48 PM PDT 24
Peak memory 145572 kb
Host smart-b87aa038-854b-4e29-9b24-abe5e185ad7e
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1191370606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.1191370606
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3129086245
Short name T26
Test name
Test status
Simulation time 8807685 ps
CPU time 0.39 seconds
Started Jul 20 05:24:50 PM PDT 24
Finished Jul 20 05:24:51 PM PDT 24
Peak memory 145552 kb
Host smart-5b076445-c4f4-4f33-91f1-834384155161
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3129086245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3129086245
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.2542521945
Short name T59
Test name
Test status
Simulation time 9146249 ps
CPU time 0.4 seconds
Started Jul 20 05:24:49 PM PDT 24
Finished Jul 20 05:24:51 PM PDT 24
Peak memory 145584 kb
Host smart-daf23c01-1c2f-40c2-970e-3af607d7b9a5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2542521945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.2542521945
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.33865174
Short name T72
Test name
Test status
Simulation time 27714590 ps
CPU time 0.41 seconds
Started Jul 20 05:45:40 PM PDT 24
Finished Jul 20 05:45:41 PM PDT 24
Peak memory 145564 kb
Host smart-58dda865-3758-4936-9828-8efd3949deb4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=33865174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.33865174
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.369883824
Short name T76
Test name
Test status
Simulation time 26987720 ps
CPU time 0.4 seconds
Started Jul 20 05:45:45 PM PDT 24
Finished Jul 20 05:45:47 PM PDT 24
Peak memory 145640 kb
Host smart-6181227b-6b8e-45c4-96d0-2ebc807f4fb5
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=369883824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.369883824
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.2123848828
Short name T62
Test name
Test status
Simulation time 28171018 ps
CPU time 0.39 seconds
Started Jul 20 05:45:29 PM PDT 24
Finished Jul 20 05:45:30 PM PDT 24
Peak memory 145600 kb
Host smart-c5a73a4b-1c0e-4cea-8328-4fe0e4bb41e4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2123848828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.2123848828
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.4194763241
Short name T71
Test name
Test status
Simulation time 27658664 ps
CPU time 0.38 seconds
Started Jul 20 05:45:50 PM PDT 24
Finished Jul 20 05:45:55 PM PDT 24
Peak memory 145528 kb
Host smart-f695563b-07f5-49f4-844c-758fe992ec24
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4194763241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.4194763241
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.572974168
Short name T79
Test name
Test status
Simulation time 28074537 ps
CPU time 0.4 seconds
Started Jul 20 05:45:27 PM PDT 24
Finished Jul 20 05:45:28 PM PDT 24
Peak memory 145608 kb
Host smart-4c5a279d-6cf4-4429-baa8-1bea90b28f12
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=572974168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.572974168
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.3885579137
Short name T64
Test name
Test status
Simulation time 28538798 ps
CPU time 0.4 seconds
Started Jul 20 05:45:40 PM PDT 24
Finished Jul 20 05:45:41 PM PDT 24
Peak memory 145588 kb
Host smart-802b7162-c0af-4457-9ea7-344cdb125a04
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3885579137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.3885579137
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.3419698567
Short name T63
Test name
Test status
Simulation time 27767749 ps
CPU time 0.4 seconds
Started Jul 20 05:45:45 PM PDT 24
Finished Jul 20 05:45:46 PM PDT 24
Peak memory 145584 kb
Host smart-b0e60607-b47e-4dec-8753-eb9f86891c15
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3419698567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.3419698567
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.2287903046
Short name T69
Test name
Test status
Simulation time 28467364 ps
CPU time 0.4 seconds
Started Jul 20 05:45:33 PM PDT 24
Finished Jul 20 05:45:34 PM PDT 24
Peak memory 145600 kb
Host smart-41b76f8a-a027-44e4-b998-1589a2925ce1
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2287903046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.2287903046
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.897052254
Short name T61
Test name
Test status
Simulation time 27971040 ps
CPU time 0.39 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:47 PM PDT 24
Peak memory 145580 kb
Host smart-b1f701bd-3282-4a09-bee5-18126c2819d8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=897052254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.897052254
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.24100096
Short name T70
Test name
Test status
Simulation time 27942980 ps
CPU time 0.39 seconds
Started Jul 20 05:45:31 PM PDT 24
Finished Jul 20 05:45:32 PM PDT 24
Peak memory 145556 kb
Host smart-5b38f291-18de-4e0e-a09a-1e2de9048e0a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=24100096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.24100096
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.537614369
Short name T77
Test name
Test status
Simulation time 27300360 ps
CPU time 0.41 seconds
Started Jul 20 05:45:34 PM PDT 24
Finished Jul 20 05:45:36 PM PDT 24
Peak memory 145596 kb
Host smart-8c2f45ad-b3f4-4591-8255-c57d0c279552
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=537614369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.537614369
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.894567213
Short name T68
Test name
Test status
Simulation time 27738993 ps
CPU time 0.44 seconds
Started Jul 20 05:45:29 PM PDT 24
Finished Jul 20 05:45:30 PM PDT 24
Peak memory 145600 kb
Host smart-18962031-c17f-40a0-8fa8-f04cd1789b17
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=894567213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.894567213
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.3486397975
Short name T78
Test name
Test status
Simulation time 28483324 ps
CPU time 0.41 seconds
Started Jul 20 05:45:31 PM PDT 24
Finished Jul 20 05:45:32 PM PDT 24
Peak memory 145580 kb
Host smart-4c11773f-0802-4edd-8dd9-6549c9ca813d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3486397975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3486397975
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.2790847734
Short name T66
Test name
Test status
Simulation time 27909633 ps
CPU time 0.4 seconds
Started Jul 20 05:45:33 PM PDT 24
Finished Jul 20 05:45:34 PM PDT 24
Peak memory 145588 kb
Host smart-e5e4426e-4d7e-4f23-9d5f-a2e52aa8c99a
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2790847734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.2790847734
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.4233133405
Short name T75
Test name
Test status
Simulation time 27433612 ps
CPU time 0.39 seconds
Started Jul 20 05:45:31 PM PDT 24
Finished Jul 20 05:45:33 PM PDT 24
Peak memory 145544 kb
Host smart-260fce8f-ca13-4b58-a81e-3480f8bdb180
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4233133405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.4233133405
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.789052508
Short name T67
Test name
Test status
Simulation time 29249257 ps
CPU time 0.42 seconds
Started Jul 20 05:45:35 PM PDT 24
Finished Jul 20 05:45:37 PM PDT 24
Peak memory 145604 kb
Host smart-e967dc0b-a535-401d-9038-a443513f6dc7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=789052508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.789052508
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.3491305527
Short name T73
Test name
Test status
Simulation time 27867696 ps
CPU time 0.41 seconds
Started Jul 20 05:45:46 PM PDT 24
Finished Jul 20 05:45:49 PM PDT 24
Peak memory 145576 kb
Host smart-b00fa67a-9423-49b7-995b-f5cd4f5099d3
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3491305527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.3491305527
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.3097463234
Short name T74
Test name
Test status
Simulation time 29566545 ps
CPU time 0.4 seconds
Started Jul 20 05:45:31 PM PDT 24
Finished Jul 20 05:45:32 PM PDT 24
Peak memory 145604 kb
Host smart-8bd6c166-a63e-4989-b5f1-5ec674e3e520
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3097463234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.3097463234
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.860877842
Short name T60
Test name
Test status
Simulation time 28858637 ps
CPU time 0.41 seconds
Started Jul 20 05:45:44 PM PDT 24
Finished Jul 20 05:45:46 PM PDT 24
Peak memory 145580 kb
Host smart-78ad83c6-ab12-4d22-a14f-9019526f4a84
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=860877842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.860877842
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.2919729598
Short name T65
Test name
Test status
Simulation time 26850531 ps
CPU time 0.4 seconds
Started Jul 20 05:45:40 PM PDT 24
Finished Jul 20 05:45:41 PM PDT 24
Peak memory 145580 kb
Host smart-da37ddf9-4485-40e3-b896-8e35b84b9ac9
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2919729598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.2919729598
Directory /workspace/9.prim_sync_fatal_alert/latest
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