Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05


Total tests in report: 78
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
88.53 88.53 100.00 100.00 91.67 91.67 100.00 100.00 78.57 78.57 95.83 95.83 65.12 65.12 /workspace/coverage/default/5.prim_async_alert.1072798487
91.66 3.13 100.00 0.00 91.67 0.00 100.00 0.00 85.71 7.14 95.83 0.00 76.74 11.63 /workspace/coverage/sync_alert/12.prim_sync_alert.3920697334
93.90 2.24 100.00 0.00 95.83 4.17 100.00 0.00 85.71 0.00 95.83 0.00 86.05 9.30 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3597145857
94.50 0.60 100.00 0.00 95.83 0.00 100.00 0.00 89.29 3.57 95.83 0.00 86.05 0.00 /workspace/coverage/default/10.prim_async_alert.1513380432
94.85 0.35 100.00 0.00 97.92 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1049235103
95.19 0.35 100.00 0.00 100.00 2.08 100.00 0.00 89.29 0.00 95.83 0.00 86.05 0.00 /workspace/coverage/sync_alert/13.prim_sync_alert.2198761529

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_async_alert.3478280590
/workspace/coverage/default/1.prim_async_alert.392475922
/workspace/coverage/default/11.prim_async_alert.3499467492
/workspace/coverage/default/12.prim_async_alert.2078503788
/workspace/coverage/default/13.prim_async_alert.1174153920
/workspace/coverage/default/14.prim_async_alert.718207100
/workspace/coverage/default/15.prim_async_alert.749282182
/workspace/coverage/default/16.prim_async_alert.3722717918
/workspace/coverage/default/17.prim_async_alert.792586599
/workspace/coverage/default/18.prim_async_alert.754464352
/workspace/coverage/default/19.prim_async_alert.3132022241
/workspace/coverage/default/2.prim_async_alert.3483477329
/workspace/coverage/default/3.prim_async_alert.4000463396
/workspace/coverage/default/4.prim_async_alert.3350992302
/workspace/coverage/default/6.prim_async_alert.3563784673
/workspace/coverage/default/7.prim_async_alert.579762183
/workspace/coverage/default/8.prim_async_alert.2645271960
/workspace/coverage/default/9.prim_async_alert.900600138
/workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2192756903
/workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1260956168
/workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2486676808
/workspace/coverage/fatal_alert/11.prim_async_fatal_alert.962046891
/workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1289270859
/workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3058686813
/workspace/coverage/fatal_alert/14.prim_async_fatal_alert.427138373
/workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2839594453
/workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3639051062
/workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4163992688
/workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3415311090
/workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3675624701
/workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2724795596
/workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1110762356
/workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4067511773
/workspace/coverage/fatal_alert/9.prim_async_fatal_alert.17928178
/workspace/coverage/sync_alert/0.prim_sync_alert.270467554
/workspace/coverage/sync_alert/1.prim_sync_alert.1116432250
/workspace/coverage/sync_alert/10.prim_sync_alert.2427909846
/workspace/coverage/sync_alert/11.prim_sync_alert.4253750111
/workspace/coverage/sync_alert/14.prim_sync_alert.1810351279
/workspace/coverage/sync_alert/15.prim_sync_alert.2006043358
/workspace/coverage/sync_alert/16.prim_sync_alert.3538398840
/workspace/coverage/sync_alert/17.prim_sync_alert.2041320946
/workspace/coverage/sync_alert/18.prim_sync_alert.1183840608
/workspace/coverage/sync_alert/19.prim_sync_alert.2183893511
/workspace/coverage/sync_alert/2.prim_sync_alert.3861726286
/workspace/coverage/sync_alert/3.prim_sync_alert.1721906495
/workspace/coverage/sync_alert/4.prim_sync_alert.3872213089
/workspace/coverage/sync_alert/5.prim_sync_alert.1076879536
/workspace/coverage/sync_alert/6.prim_sync_alert.3350307451
/workspace/coverage/sync_alert/7.prim_sync_alert.3109100137
/workspace/coverage/sync_alert/8.prim_sync_alert.3665855043
/workspace/coverage/sync_alert/9.prim_sync_alert.703629850
/workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.69822289
/workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1577267949
/workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.61824791
/workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1899894510
/workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2174912210
/workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1609901901
/workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1672770147
/workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.689966190
/workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.711579654
/workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1598414147
/workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3657710789
/workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3169158053
/workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2351094954
/workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3924038045
/workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2649944143
/workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1125251790
/workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.365469386
/workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2243232274
/workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.854553757
/workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3644530694



Total test records in report: 78
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/16.prim_async_alert.3722717918 Jul 21 04:21:01 PM PDT 24 Jul 21 04:21:02 PM PDT 24 10947701 ps
T2 /workspace/coverage/default/18.prim_async_alert.754464352 Jul 21 04:20:43 PM PDT 24 Jul 21 04:20:44 PM PDT 24 12095154 ps
T3 /workspace/coverage/default/14.prim_async_alert.718207100 Jul 21 04:22:34 PM PDT 24 Jul 21 04:22:35 PM PDT 24 11739686 ps
T7 /workspace/coverage/default/12.prim_async_alert.2078503788 Jul 21 04:22:00 PM PDT 24 Jul 21 04:22:01 PM PDT 24 11353083 ps
T8 /workspace/coverage/default/10.prim_async_alert.1513380432 Jul 21 04:23:34 PM PDT 24 Jul 21 04:23:35 PM PDT 24 11941746 ps
T14 /workspace/coverage/default/5.prim_async_alert.1072798487 Jul 21 04:23:26 PM PDT 24 Jul 21 04:23:27 PM PDT 24 11865921 ps
T21 /workspace/coverage/default/2.prim_async_alert.3483477329 Jul 21 04:19:09 PM PDT 24 Jul 21 04:19:10 PM PDT 24 11106523 ps
T17 /workspace/coverage/default/3.prim_async_alert.4000463396 Jul 21 04:19:09 PM PDT 24 Jul 21 04:19:10 PM PDT 24 11596570 ps
T9 /workspace/coverage/default/11.prim_async_alert.3499467492 Jul 21 04:23:33 PM PDT 24 Jul 21 04:23:34 PM PDT 24 11549644 ps
T15 /workspace/coverage/default/7.prim_async_alert.579762183 Jul 21 04:21:33 PM PDT 24 Jul 21 04:21:34 PM PDT 24 11224913 ps
T48 /workspace/coverage/default/6.prim_async_alert.3563784673 Jul 21 04:23:26 PM PDT 24 Jul 21 04:23:27 PM PDT 24 11582828 ps
T22 /workspace/coverage/default/19.prim_async_alert.3132022241 Jul 21 04:23:18 PM PDT 24 Jul 21 04:23:19 PM PDT 24 10974692 ps
T10 /workspace/coverage/default/17.prim_async_alert.792586599 Jul 21 04:22:49 PM PDT 24 Jul 21 04:22:51 PM PDT 24 10865920 ps
T11 /workspace/coverage/default/4.prim_async_alert.3350992302 Jul 21 04:19:55 PM PDT 24 Jul 21 04:19:55 PM PDT 24 10956708 ps
T49 /workspace/coverage/default/15.prim_async_alert.749282182 Jul 21 04:20:06 PM PDT 24 Jul 21 04:20:07 PM PDT 24 10883834 ps
T23 /workspace/coverage/default/0.prim_async_alert.3478280590 Jul 21 04:19:16 PM PDT 24 Jul 21 04:19:17 PM PDT 24 11021357 ps
T16 /workspace/coverage/default/1.prim_async_alert.392475922 Jul 21 04:21:59 PM PDT 24 Jul 21 04:22:00 PM PDT 24 12046303 ps
T24 /workspace/coverage/default/13.prim_async_alert.1174153920 Jul 21 04:18:53 PM PDT 24 Jul 21 04:18:54 PM PDT 24 10782049 ps
T18 /workspace/coverage/default/9.prim_async_alert.900600138 Jul 21 04:22:11 PM PDT 24 Jul 21 04:22:11 PM PDT 24 11405082 ps
T12 /workspace/coverage/default/8.prim_async_alert.2645271960 Jul 21 04:21:44 PM PDT 24 Jul 21 04:21:44 PM PDT 24 11357908 ps
T19 /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1260956168 Jul 21 04:20:49 PM PDT 24 Jul 21 04:20:50 PM PDT 24 30916757 ps
T25 /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3597145857 Jul 21 04:19:42 PM PDT 24 Jul 21 04:19:42 PM PDT 24 31237547 ps
T4 /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1049235103 Jul 21 04:23:20 PM PDT 24 Jul 21 04:23:20 PM PDT 24 30978687 ps
T20 /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4067511773 Jul 21 04:22:13 PM PDT 24 Jul 21 04:22:14 PM PDT 24 29747665 ps
T42 /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1110762356 Jul 21 04:23:31 PM PDT 24 Jul 21 04:23:32 PM PDT 24 29215603 ps
T43 /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2724795596 Jul 21 04:19:15 PM PDT 24 Jul 21 04:19:16 PM PDT 24 30599386 ps
T44 /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.17928178 Jul 21 04:23:31 PM PDT 24 Jul 21 04:23:32 PM PDT 24 30974309 ps
T45 /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4163992688 Jul 21 04:22:39 PM PDT 24 Jul 21 04:22:40 PM PDT 24 29161749 ps
T46 /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3058686813 Jul 21 04:23:59 PM PDT 24 Jul 21 04:24:00 PM PDT 24 29196329 ps
T47 /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.427138373 Jul 21 04:23:06 PM PDT 24 Jul 21 04:23:07 PM PDT 24 28421244 ps
T50 /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1289270859 Jul 21 04:23:58 PM PDT 24 Jul 21 04:23:59 PM PDT 24 30607899 ps
T51 /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2486676808 Jul 21 04:20:15 PM PDT 24 Jul 21 04:20:16 PM PDT 24 31236477 ps
T52 /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2192756903 Jul 21 04:20:50 PM PDT 24 Jul 21 04:20:51 PM PDT 24 30145996 ps
T41 /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2839594453 Jul 21 04:21:37 PM PDT 24 Jul 21 04:21:37 PM PDT 24 29232648 ps
T53 /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3415311090 Jul 21 04:23:08 PM PDT 24 Jul 21 04:23:09 PM PDT 24 30228160 ps
T54 /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3639051062 Jul 21 04:21:39 PM PDT 24 Jul 21 04:21:39 PM PDT 24 29584688 ps
T55 /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3675624701 Jul 21 04:23:08 PM PDT 24 Jul 21 04:23:09 PM PDT 24 29614894 ps
T56 /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.962046891 Jul 21 04:23:20 PM PDT 24 Jul 21 04:23:21 PM PDT 24 30115623 ps
T26 /workspace/coverage/sync_alert/6.prim_sync_alert.3350307451 Jul 21 04:20:10 PM PDT 24 Jul 21 04:20:11 PM PDT 24 9097120 ps
T27 /workspace/coverage/sync_alert/17.prim_sync_alert.2041320946 Jul 21 04:21:05 PM PDT 24 Jul 21 04:21:06 PM PDT 24 9065770 ps
T28 /workspace/coverage/sync_alert/2.prim_sync_alert.3861726286 Jul 21 04:18:54 PM PDT 24 Jul 21 04:18:55 PM PDT 24 8805566 ps
T29 /workspace/coverage/sync_alert/12.prim_sync_alert.3920697334 Jul 21 04:18:59 PM PDT 24 Jul 21 04:19:00 PM PDT 24 10361851 ps
T30 /workspace/coverage/sync_alert/7.prim_sync_alert.3109100137 Jul 21 04:22:34 PM PDT 24 Jul 21 04:22:35 PM PDT 24 8479298 ps
T36 /workspace/coverage/sync_alert/14.prim_sync_alert.1810351279 Jul 21 04:23:02 PM PDT 24 Jul 21 04:23:03 PM PDT 24 9210471 ps
T37 /workspace/coverage/sync_alert/8.prim_sync_alert.3665855043 Jul 21 04:20:32 PM PDT 24 Jul 21 04:20:33 PM PDT 24 8639294 ps
T38 /workspace/coverage/sync_alert/0.prim_sync_alert.270467554 Jul 21 04:23:34 PM PDT 24 Jul 21 04:23:34 PM PDT 24 9028341 ps
T39 /workspace/coverage/sync_alert/5.prim_sync_alert.1076879536 Jul 21 04:23:33 PM PDT 24 Jul 21 04:23:34 PM PDT 24 8295068 ps
T40 /workspace/coverage/sync_alert/9.prim_sync_alert.703629850 Jul 21 04:23:19 PM PDT 24 Jul 21 04:23:20 PM PDT 24 8773005 ps
T31 /workspace/coverage/sync_alert/11.prim_sync_alert.4253750111 Jul 21 04:20:15 PM PDT 24 Jul 21 04:20:16 PM PDT 24 9409890 ps
T57 /workspace/coverage/sync_alert/10.prim_sync_alert.2427909846 Jul 21 04:20:19 PM PDT 24 Jul 21 04:20:19 PM PDT 24 8735866 ps
T32 /workspace/coverage/sync_alert/16.prim_sync_alert.3538398840 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:38 PM PDT 24 8666590 ps
T33 /workspace/coverage/sync_alert/1.prim_sync_alert.1116432250 Jul 21 04:22:20 PM PDT 24 Jul 21 04:22:21 PM PDT 24 10378103 ps
T58 /workspace/coverage/sync_alert/15.prim_sync_alert.2006043358 Jul 21 04:22:35 PM PDT 24 Jul 21 04:22:37 PM PDT 24 8396762 ps
T59 /workspace/coverage/sync_alert/3.prim_sync_alert.1721906495 Jul 21 04:22:50 PM PDT 24 Jul 21 04:22:51 PM PDT 24 10228791 ps
T34 /workspace/coverage/sync_alert/18.prim_sync_alert.1183840608 Jul 21 04:22:40 PM PDT 24 Jul 21 04:22:42 PM PDT 24 8840483 ps
T60 /workspace/coverage/sync_alert/4.prim_sync_alert.3872213089 Jul 21 04:22:49 PM PDT 24 Jul 21 04:22:51 PM PDT 24 8776207 ps
T13 /workspace/coverage/sync_alert/13.prim_sync_alert.2198761529 Jul 21 04:22:36 PM PDT 24 Jul 21 04:22:37 PM PDT 24 8665505 ps
T35 /workspace/coverage/sync_alert/19.prim_sync_alert.2183893511 Jul 21 04:23:37 PM PDT 24 Jul 21 04:23:38 PM PDT 24 8648415 ps
T5 /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.689966190 Jul 21 04:19:31 PM PDT 24 Jul 21 04:19:32 PM PDT 24 28388508 ps
T61 /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.61824791 Jul 21 04:23:14 PM PDT 24 Jul 21 04:23:15 PM PDT 24 26664563 ps
T6 /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1899894510 Jul 21 04:23:14 PM PDT 24 Jul 21 04:23:15 PM PDT 24 27633713 ps
T62 /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.854553757 Jul 21 04:18:06 PM PDT 24 Jul 21 04:18:07 PM PDT 24 25921889 ps
T63 /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2243232274 Jul 21 04:23:08 PM PDT 24 Jul 21 04:23:09 PM PDT 24 27815529 ps
T64 /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3169158053 Jul 21 04:19:32 PM PDT 24 Jul 21 04:19:33 PM PDT 24 27852432 ps
T65 /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1577267949 Jul 21 04:21:09 PM PDT 24 Jul 21 04:21:10 PM PDT 24 28844338 ps
T66 /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.69822289 Jul 21 04:23:50 PM PDT 24 Jul 21 04:23:51 PM PDT 24 27306182 ps
T67 /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3657710789 Jul 21 04:23:06 PM PDT 24 Jul 21 04:23:07 PM PDT 24 26759849 ps
T68 /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2649944143 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:38 PM PDT 24 25237314 ps
T69 /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2174912210 Jul 21 04:23:10 PM PDT 24 Jul 21 04:23:11 PM PDT 24 26493941 ps
T70 /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.365469386 Jul 21 04:24:17 PM PDT 24 Jul 21 04:24:18 PM PDT 24 30053618 ps
T71 /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1672770147 Jul 21 04:23:05 PM PDT 24 Jul 21 04:23:06 PM PDT 24 28441719 ps
T72 /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3924038045 Jul 21 04:20:16 PM PDT 24 Jul 21 04:20:17 PM PDT 24 27170346 ps
T73 /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2351094954 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:38 PM PDT 24 28097257 ps
T74 /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3644530694 Jul 21 04:19:15 PM PDT 24 Jul 21 04:19:16 PM PDT 24 27287725 ps
T75 /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1598414147 Jul 21 04:23:06 PM PDT 24 Jul 21 04:23:07 PM PDT 24 28397272 ps
T76 /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1609901901 Jul 21 04:19:01 PM PDT 24 Jul 21 04:19:02 PM PDT 24 28605181 ps
T77 /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1125251790 Jul 21 04:18:53 PM PDT 24 Jul 21 04:18:54 PM PDT 24 26900166 ps
T78 /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.711579654 Jul 21 04:18:59 PM PDT 24 Jul 21 04:19:00 PM PDT 24 26128599 ps

Test location /workspace/coverage/default/5.prim_async_alert.1072798487
Short name T14
Test name
Test status
Simulation time 11865921 ps
CPU time 0.39 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:23:27 PM PDT 24
Peak memory 145404 kb
Host smart-7fb70476-df0e-4432-8304-2e8379c90b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072798487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.1072798487
Directory /workspace/5.prim_async_alert/latest

Test location /workspace/coverage/sync_alert/12.prim_sync_alert.3920697334
Short name T29
Test name
Test status
Simulation time 10361851 ps
CPU time 0.38 seconds
Started Jul 21 04:18:59 PM PDT 24
Finished Jul 21 04:19:00 PM PDT 24
Peak memory 144744 kb
Host smart-16ba34ac-c5bd-471d-8140-bac512c912be
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3920697334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_alert.3920697334
Directory /workspace/12.prim_sync_alert/latest

Test location /workspace/coverage/fatal_alert/16.prim_async_fatal_alert.3597145857
Short name T25
Test name
Test status
Simulation time 31237547 ps
CPU time 0.42 seconds
Started Jul 21 04:19:42 PM PDT 24
Finished Jul 21 04:19:42 PM PDT 24
Peak memory 145348 kb
Host smart-abf65418-1bbb-46be-aada-3346b43f4e8d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3597145857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_async_fatal_alert.3597145857
Directory /workspace/16.prim_async_fatal_alert/latest

Test location /workspace/coverage/default/10.prim_async_alert.1513380432
Short name T8
Test name
Test status
Simulation time 11941746 ps
CPU time 0.38 seconds
Started Jul 21 04:23:34 PM PDT 24
Finished Jul 21 04:23:35 PM PDT 24
Peak memory 145492 kb
Host smart-e8de6db6-bfb8-4827-b63c-676ec6c79be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513380432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.1513380432
Directory /workspace/10.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/15.prim_async_fatal_alert.1049235103
Short name T4
Test name
Test status
Simulation time 30978687 ps
CPU time 0.38 seconds
Started Jul 21 04:23:20 PM PDT 24
Finished Jul 21 04:23:20 PM PDT 24
Peak memory 145188 kb
Host smart-8c967d4f-292e-4858-91b9-2b0070a2326a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1049235103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_async_fatal_alert.1049235103
Directory /workspace/15.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/13.prim_sync_alert.2198761529
Short name T13
Test name
Test status
Simulation time 8665505 ps
CPU time 0.39 seconds
Started Jul 21 04:22:36 PM PDT 24
Finished Jul 21 04:22:37 PM PDT 24
Peak memory 143988 kb
Host smart-e2bb6a76-ee6a-4ff8-b183-30f16d8d4745
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2198761529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_alert.2198761529
Directory /workspace/13.prim_sync_alert/latest

Test location /workspace/coverage/default/0.prim_async_alert.3478280590
Short name T23
Test name
Test status
Simulation time 11021357 ps
CPU time 0.4 seconds
Started Jul 21 04:19:16 PM PDT 24
Finished Jul 21 04:19:17 PM PDT 24
Peak memory 145192 kb
Host smart-71fb3e83-e581-41ed-8f0d-f7bfffdd26c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478280590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.3478280590
Directory /workspace/0.prim_async_alert/latest

Test location /workspace/coverage/default/1.prim_async_alert.392475922
Short name T16
Test name
Test status
Simulation time 12046303 ps
CPU time 0.38 seconds
Started Jul 21 04:21:59 PM PDT 24
Finished Jul 21 04:22:00 PM PDT 24
Peak memory 145584 kb
Host smart-3529d1c8-1620-4bdf-8df0-6cacc989fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392475922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.392475922
Directory /workspace/1.prim_async_alert/latest

Test location /workspace/coverage/default/11.prim_async_alert.3499467492
Short name T9
Test name
Test status
Simulation time 11549644 ps
CPU time 0.38 seconds
Started Jul 21 04:23:33 PM PDT 24
Finished Jul 21 04:23:34 PM PDT 24
Peak memory 145484 kb
Host smart-5f80f738-ed9b-4ff3-a962-c088b4de459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499467492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.3499467492
Directory /workspace/11.prim_async_alert/latest

Test location /workspace/coverage/default/12.prim_async_alert.2078503788
Short name T7
Test name
Test status
Simulation time 11353083 ps
CPU time 0.38 seconds
Started Jul 21 04:22:00 PM PDT 24
Finished Jul 21 04:22:01 PM PDT 24
Peak memory 145604 kb
Host smart-f033e08e-02f5-4734-bbf4-5ad0bd246e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078503788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.2078503788
Directory /workspace/12.prim_async_alert/latest

Test location /workspace/coverage/default/13.prim_async_alert.1174153920
Short name T24
Test name
Test status
Simulation time 10782049 ps
CPU time 0.39 seconds
Started Jul 21 04:18:53 PM PDT 24
Finished Jul 21 04:18:54 PM PDT 24
Peak memory 145532 kb
Host smart-019aa044-a88b-4c4c-8f5a-818f9be4d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174153920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1174153920
Directory /workspace/13.prim_async_alert/latest

Test location /workspace/coverage/default/14.prim_async_alert.718207100
Short name T3
Test name
Test status
Simulation time 11739686 ps
CPU time 0.43 seconds
Started Jul 21 04:22:34 PM PDT 24
Finished Jul 21 04:22:35 PM PDT 24
Peak memory 144004 kb
Host smart-76833c2d-c31c-4b8e-9205-c03ed256ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718207100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.718207100
Directory /workspace/14.prim_async_alert/latest

Test location /workspace/coverage/default/15.prim_async_alert.749282182
Short name T49
Test name
Test status
Simulation time 10883834 ps
CPU time 0.4 seconds
Started Jul 21 04:20:06 PM PDT 24
Finished Jul 21 04:20:07 PM PDT 24
Peak memory 145652 kb
Host smart-58d3a25b-a4ed-4279-986e-b69aa58c46d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749282182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.749282182
Directory /workspace/15.prim_async_alert/latest

Test location /workspace/coverage/default/16.prim_async_alert.3722717918
Short name T1
Test name
Test status
Simulation time 10947701 ps
CPU time 0.38 seconds
Started Jul 21 04:21:01 PM PDT 24
Finished Jul 21 04:21:02 PM PDT 24
Peak memory 145604 kb
Host smart-f57f786d-2bf2-4b81-b439-ca29a47d165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722717918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3722717918
Directory /workspace/16.prim_async_alert/latest

Test location /workspace/coverage/default/17.prim_async_alert.792586599
Short name T10
Test name
Test status
Simulation time 10865920 ps
CPU time 0.38 seconds
Started Jul 21 04:22:49 PM PDT 24
Finished Jul 21 04:22:51 PM PDT 24
Peak memory 145624 kb
Host smart-48955a51-d9ae-4973-b1b7-3aa4afeecb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792586599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.792586599
Directory /workspace/17.prim_async_alert/latest

Test location /workspace/coverage/default/18.prim_async_alert.754464352
Short name T2
Test name
Test status
Simulation time 12095154 ps
CPU time 0.39 seconds
Started Jul 21 04:20:43 PM PDT 24
Finished Jul 21 04:20:44 PM PDT 24
Peak memory 145780 kb
Host smart-0450d8f4-9940-403c-824a-f3166fdeeff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754464352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.754464352
Directory /workspace/18.prim_async_alert/latest

Test location /workspace/coverage/default/19.prim_async_alert.3132022241
Short name T22
Test name
Test status
Simulation time 10974692 ps
CPU time 0.39 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:23:19 PM PDT 24
Peak memory 145628 kb
Host smart-cfcd2c98-fcd2-4201-8f7f-121cb5642f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132022241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.3132022241
Directory /workspace/19.prim_async_alert/latest

Test location /workspace/coverage/default/2.prim_async_alert.3483477329
Short name T21
Test name
Test status
Simulation time 11106523 ps
CPU time 0.38 seconds
Started Jul 21 04:19:09 PM PDT 24
Finished Jul 21 04:19:10 PM PDT 24
Peak memory 145584 kb
Host smart-d843ee04-ddd2-4b4d-be56-2bae88cd9f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483477329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3483477329
Directory /workspace/2.prim_async_alert/latest

Test location /workspace/coverage/default/3.prim_async_alert.4000463396
Short name T17
Test name
Test status
Simulation time 11596570 ps
CPU time 0.44 seconds
Started Jul 21 04:19:09 PM PDT 24
Finished Jul 21 04:19:10 PM PDT 24
Peak memory 144212 kb
Host smart-fe7abc43-b90b-4090-a01f-8f0331091eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000463396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.4000463396
Directory /workspace/3.prim_async_alert/latest

Test location /workspace/coverage/default/4.prim_async_alert.3350992302
Short name T11
Test name
Test status
Simulation time 10956708 ps
CPU time 0.38 seconds
Started Jul 21 04:19:55 PM PDT 24
Finished Jul 21 04:19:55 PM PDT 24
Peak memory 145668 kb
Host smart-8f98b757-36ad-4aad-85b9-f42bf19423c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350992302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.3350992302
Directory /workspace/4.prim_async_alert/latest

Test location /workspace/coverage/default/6.prim_async_alert.3563784673
Short name T48
Test name
Test status
Simulation time 11582828 ps
CPU time 0.39 seconds
Started Jul 21 04:23:26 PM PDT 24
Finished Jul 21 04:23:27 PM PDT 24
Peak memory 145472 kb
Host smart-ac4ab493-2134-4389-99cf-54e8ca3d2936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563784673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.3563784673
Directory /workspace/6.prim_async_alert/latest

Test location /workspace/coverage/default/7.prim_async_alert.579762183
Short name T15
Test name
Test status
Simulation time 11224913 ps
CPU time 0.39 seconds
Started Jul 21 04:21:33 PM PDT 24
Finished Jul 21 04:21:34 PM PDT 24
Peak memory 145804 kb
Host smart-ddc7eb46-0011-494a-b70d-aa4f71d51b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579762183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.579762183
Directory /workspace/7.prim_async_alert/latest

Test location /workspace/coverage/default/8.prim_async_alert.2645271960
Short name T12
Test name
Test status
Simulation time 11357908 ps
CPU time 0.38 seconds
Started Jul 21 04:21:44 PM PDT 24
Finished Jul 21 04:21:44 PM PDT 24
Peak memory 145784 kb
Host smart-e66e4221-24ae-4916-b08f-b897ef1d8551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645271960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2645271960
Directory /workspace/8.prim_async_alert/latest

Test location /workspace/coverage/default/9.prim_async_alert.900600138
Short name T18
Test name
Test status
Simulation time 11405082 ps
CPU time 0.39 seconds
Started Jul 21 04:22:11 PM PDT 24
Finished Jul 21 04:22:11 PM PDT 24
Peak memory 145584 kb
Host smart-c686b03d-7c19-4634-9c0b-1da81eb787ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900600138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.900600138
Directory /workspace/9.prim_async_alert/latest

Test location /workspace/coverage/fatal_alert/0.prim_async_fatal_alert.2192756903
Short name T52
Test name
Test status
Simulation time 30145996 ps
CPU time 0.45 seconds
Started Jul 21 04:20:50 PM PDT 24
Finished Jul 21 04:20:51 PM PDT 24
Peak memory 145380 kb
Host smart-5758c87a-8aa0-4ce3-afb6-7297db979c0e
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2192756903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.2192756903
Directory /workspace/0.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/1.prim_async_fatal_alert.1260956168
Short name T19
Test name
Test status
Simulation time 30916757 ps
CPU time 0.4 seconds
Started Jul 21 04:20:49 PM PDT 24
Finished Jul 21 04:20:50 PM PDT 24
Peak memory 145168 kb
Host smart-8f652800-99e2-4853-9057-2736c7647c43
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1260956168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.1260956168
Directory /workspace/1.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/10.prim_async_fatal_alert.2486676808
Short name T51
Test name
Test status
Simulation time 31236477 ps
CPU time 0.4 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:20:16 PM PDT 24
Peak memory 145064 kb
Host smart-627f839a-39e2-44ec-abb9-8201ec881d7a
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2486676808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_async_fatal_alert.2486676808
Directory /workspace/10.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/11.prim_async_fatal_alert.962046891
Short name T56
Test name
Test status
Simulation time 30115623 ps
CPU time 0.41 seconds
Started Jul 21 04:23:20 PM PDT 24
Finished Jul 21 04:23:21 PM PDT 24
Peak memory 145024 kb
Host smart-57bd1bed-0a6a-46a1-bcd2-091fef35b578
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=962046891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_async_fatal_alert.962046891
Directory /workspace/11.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/12.prim_async_fatal_alert.1289270859
Short name T50
Test name
Test status
Simulation time 30607899 ps
CPU time 0.4 seconds
Started Jul 21 04:23:58 PM PDT 24
Finished Jul 21 04:23:59 PM PDT 24
Peak memory 145440 kb
Host smart-9d8f34d2-de18-4ca9-854e-ffee2fb296cd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1289270859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_async_fatal_alert.1289270859
Directory /workspace/12.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/13.prim_async_fatal_alert.3058686813
Short name T46
Test name
Test status
Simulation time 29196329 ps
CPU time 0.39 seconds
Started Jul 21 04:23:59 PM PDT 24
Finished Jul 21 04:24:00 PM PDT 24
Peak memory 145064 kb
Host smart-6747e5c9-ad99-4cbd-b3e8-3327beceff9d
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3058686813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_async_fatal_alert.3058686813
Directory /workspace/13.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/14.prim_async_fatal_alert.427138373
Short name T47
Test name
Test status
Simulation time 28421244 ps
CPU time 0.39 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:23:07 PM PDT 24
Peak memory 144404 kb
Host smart-0fb9030e-ffa7-4b2f-a62f-306381985c68
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=427138373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_async_fatal_alert.427138373
Directory /workspace/14.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/17.prim_async_fatal_alert.2839594453
Short name T41
Test name
Test status
Simulation time 29232648 ps
CPU time 0.42 seconds
Started Jul 21 04:21:37 PM PDT 24
Finished Jul 21 04:21:37 PM PDT 24
Peak memory 145200 kb
Host smart-7fbb583f-ee76-4496-b268-5cc8ebf583fd
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2839594453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_async_fatal_alert.2839594453
Directory /workspace/17.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/19.prim_async_fatal_alert.3639051062
Short name T54
Test name
Test status
Simulation time 29584688 ps
CPU time 0.42 seconds
Started Jul 21 04:21:39 PM PDT 24
Finished Jul 21 04:21:39 PM PDT 24
Peak memory 145284 kb
Host smart-94cb5da4-4bdc-4409-a44f-a963d3e5b995
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3639051062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_async_fatal_alert.3639051062
Directory /workspace/19.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/2.prim_async_fatal_alert.4163992688
Short name T45
Test name
Test status
Simulation time 29161749 ps
CPU time 0.47 seconds
Started Jul 21 04:22:39 PM PDT 24
Finished Jul 21 04:22:40 PM PDT 24
Peak memory 144844 kb
Host smart-d6d96447-c6b6-4bbe-bc28-ddb58d57ffa5
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4163992688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4163992688
Directory /workspace/2.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/3.prim_async_fatal_alert.3415311090
Short name T53
Test name
Test status
Simulation time 30228160 ps
CPU time 0.43 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:23:09 PM PDT 24
Peak memory 144980 kb
Host smart-e000469e-7b6a-41b2-a14b-fad98cc1dd32
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3415311090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.3415311090
Directory /workspace/3.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/4.prim_async_fatal_alert.3675624701
Short name T55
Test name
Test status
Simulation time 29614894 ps
CPU time 0.41 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:23:09 PM PDT 24
Peak memory 144968 kb
Host smart-3025aec2-fb4a-4e72-8f62-ab5fa82c49db
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=3675624701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3675624701
Directory /workspace/4.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/6.prim_async_fatal_alert.2724795596
Short name T43
Test name
Test status
Simulation time 30599386 ps
CPU time 0.45 seconds
Started Jul 21 04:19:15 PM PDT 24
Finished Jul 21 04:19:16 PM PDT 24
Peak memory 145228 kb
Host smart-f00cacb3-ce5c-44af-86dc-80f6448e0ef8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=2724795596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.2724795596
Directory /workspace/6.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/7.prim_async_fatal_alert.1110762356
Short name T42
Test name
Test status
Simulation time 29215603 ps
CPU time 0.45 seconds
Started Jul 21 04:23:31 PM PDT 24
Finished Jul 21 04:23:32 PM PDT 24
Peak memory 143588 kb
Host smart-150ace84-672a-4832-8761-f49f553ec8d8
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=1110762356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.1110762356
Directory /workspace/7.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/8.prim_async_fatal_alert.4067511773
Short name T20
Test name
Test status
Simulation time 29747665 ps
CPU time 0.39 seconds
Started Jul 21 04:22:13 PM PDT 24
Finished Jul 21 04:22:14 PM PDT 24
Peak memory 145216 kb
Host smart-c6736ab3-f8cf-4e46-908b-1e8aa9c9c06f
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=4067511773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.4067511773
Directory /workspace/8.prim_async_fatal_alert/latest

Test location /workspace/coverage/fatal_alert/9.prim_async_fatal_alert.17928178
Short name T44
Test name
Test status
Simulation time 30974309 ps
CPU time 0.42 seconds
Started Jul 21 04:23:31 PM PDT 24
Finished Jul 21 04:23:32 PM PDT 24
Peak memory 143484 kb
Host smart-479ac3bc-11bd-457b-963b-5667245421e9
User root
Command /workspace/fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t
ools/sim.tcl +ntb_random_seed=17928178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.17928178
Directory /workspace/9.prim_async_fatal_alert/latest

Test location /workspace/coverage/sync_alert/0.prim_sync_alert.270467554
Short name T38
Test name
Test status
Simulation time 9028341 ps
CPU time 0.36 seconds
Started Jul 21 04:23:34 PM PDT 24
Finished Jul 21 04:23:34 PM PDT 24
Peak memory 145268 kb
Host smart-c014eceb-c005-4461-bf1d-be81974d9874
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=270467554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.270467554
Directory /workspace/0.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/1.prim_sync_alert.1116432250
Short name T33
Test name
Test status
Simulation time 10378103 ps
CPU time 0.39 seconds
Started Jul 21 04:22:20 PM PDT 24
Finished Jul 21 04:22:21 PM PDT 24
Peak memory 145412 kb
Host smart-e9f8dff5-f099-4db7-af7e-a2e6039d6f37
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1116432250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.1116432250
Directory /workspace/1.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/10.prim_sync_alert.2427909846
Short name T57
Test name
Test status
Simulation time 8735866 ps
CPU time 0.4 seconds
Started Jul 21 04:20:19 PM PDT 24
Finished Jul 21 04:20:19 PM PDT 24
Peak memory 145452 kb
Host smart-9e59db3b-48e3-4499-a30d-688565153187
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2427909846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_alert.2427909846
Directory /workspace/10.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/11.prim_sync_alert.4253750111
Short name T31
Test name
Test status
Simulation time 9409890 ps
CPU time 0.37 seconds
Started Jul 21 04:20:15 PM PDT 24
Finished Jul 21 04:20:16 PM PDT 24
Peak memory 145376 kb
Host smart-a3fe0683-5be3-465b-8193-49a23829ca8b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=4253750111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_alert.4253750111
Directory /workspace/11.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/14.prim_sync_alert.1810351279
Short name T36
Test name
Test status
Simulation time 9210471 ps
CPU time 0.42 seconds
Started Jul 21 04:23:02 PM PDT 24
Finished Jul 21 04:23:03 PM PDT 24
Peak memory 144364 kb
Host smart-ee934de7-2145-44f7-94ba-fe6da7ef659f
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1810351279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_alert.1810351279
Directory /workspace/14.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/15.prim_sync_alert.2006043358
Short name T58
Test name
Test status
Simulation time 8396762 ps
CPU time 0.39 seconds
Started Jul 21 04:22:35 PM PDT 24
Finished Jul 21 04:22:37 PM PDT 24
Peak memory 143524 kb
Host smart-7b078ea7-efa1-4588-a921-f89cd9532c78
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2006043358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_alert.2006043358
Directory /workspace/15.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/16.prim_sync_alert.3538398840
Short name T32
Test name
Test status
Simulation time 8666590 ps
CPU time 0.47 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:38 PM PDT 24
Peak memory 142592 kb
Host smart-655d9e35-9249-4e51-9724-b3b48f006554
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3538398840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_alert.3538398840
Directory /workspace/16.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/17.prim_sync_alert.2041320946
Short name T27
Test name
Test status
Simulation time 9065770 ps
CPU time 0.39 seconds
Started Jul 21 04:21:05 PM PDT 24
Finished Jul 21 04:21:06 PM PDT 24
Peak memory 145580 kb
Host smart-63362b28-de15-4719-9b20-4811b4ec11f7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2041320946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_alert.2041320946
Directory /workspace/17.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/18.prim_sync_alert.1183840608
Short name T34
Test name
Test status
Simulation time 8840483 ps
CPU time 0.42 seconds
Started Jul 21 04:22:40 PM PDT 24
Finished Jul 21 04:22:42 PM PDT 24
Peak memory 144152 kb
Host smart-89c30be7-2f6e-40a6-b4c5-d3c85eb39a8b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1183840608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_alert.1183840608
Directory /workspace/18.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/19.prim_sync_alert.2183893511
Short name T35
Test name
Test status
Simulation time 8648415 ps
CPU time 0.51 seconds
Started Jul 21 04:23:37 PM PDT 24
Finished Jul 21 04:23:38 PM PDT 24
Peak memory 144308 kb
Host smart-02f9c71f-0801-4319-bdbb-59d1e4e2638a
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=2183893511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_alert.2183893511
Directory /workspace/19.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/2.prim_sync_alert.3861726286
Short name T28
Test name
Test status
Simulation time 8805566 ps
CPU time 0.41 seconds
Started Jul 21 04:18:54 PM PDT 24
Finished Jul 21 04:18:55 PM PDT 24
Peak memory 145452 kb
Host smart-2bc82945-66b4-4aa0-b7f0-8ae6b34b78d7
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3861726286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.3861726286
Directory /workspace/2.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/3.prim_sync_alert.1721906495
Short name T59
Test name
Test status
Simulation time 10228791 ps
CPU time 0.38 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:22:51 PM PDT 24
Peak memory 145416 kb
Host smart-5a079de4-2f8e-4b93-a436-0afc02849fc5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1721906495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.1721906495
Directory /workspace/3.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/4.prim_sync_alert.3872213089
Short name T60
Test name
Test status
Simulation time 8776207 ps
CPU time 0.38 seconds
Started Jul 21 04:22:49 PM PDT 24
Finished Jul 21 04:22:51 PM PDT 24
Peak memory 145408 kb
Host smart-1ec1ad7e-b307-47d1-81ba-fc20dc7be73b
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3872213089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.3872213089
Directory /workspace/4.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/5.prim_sync_alert.1076879536
Short name T39
Test name
Test status
Simulation time 8295068 ps
CPU time 0.37 seconds
Started Jul 21 04:23:33 PM PDT 24
Finished Jul 21 04:23:34 PM PDT 24
Peak memory 145256 kb
Host smart-8f78901c-0f49-4469-b227-f4cbd88ef96c
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=1076879536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.1076879536
Directory /workspace/5.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/6.prim_sync_alert.3350307451
Short name T26
Test name
Test status
Simulation time 9097120 ps
CPU time 0.39 seconds
Started Jul 21 04:20:10 PM PDT 24
Finished Jul 21 04:20:11 PM PDT 24
Peak memory 145624 kb
Host smart-8a4cb9e1-0e6c-40af-a127-25e2ea700af6
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3350307451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3350307451
Directory /workspace/6.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/7.prim_sync_alert.3109100137
Short name T30
Test name
Test status
Simulation time 8479298 ps
CPU time 0.41 seconds
Started Jul 21 04:22:34 PM PDT 24
Finished Jul 21 04:22:35 PM PDT 24
Peak memory 143876 kb
Host smart-1ece528b-d25c-49de-8101-830031cb03d9
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3109100137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.3109100137
Directory /workspace/7.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/8.prim_sync_alert.3665855043
Short name T37
Test name
Test status
Simulation time 8639294 ps
CPU time 0.39 seconds
Started Jul 21 04:20:32 PM PDT 24
Finished Jul 21 04:20:33 PM PDT 24
Peak memory 145600 kb
Host smart-ed5b70af-c9c2-44fb-a33a-dc99776418d5
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=3665855043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.3665855043
Directory /workspace/8.prim_sync_alert/latest

Test location /workspace/coverage/sync_alert/9.prim_sync_alert.703629850
Short name T40
Test name
Test status
Simulation time 8773005 ps
CPU time 0.37 seconds
Started Jul 21 04:23:19 PM PDT 24
Finished Jul 21 04:23:20 PM PDT 24
Peak memory 145404 kb
Host smart-3a1047eb-bb10-4a74-9845-c4b7ebc997d0
User root
Command /workspace/sync_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/to
ols/sim.tcl +ntb_random_seed=703629850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.703629850
Directory /workspace/9.prim_sync_alert/latest

Test location /workspace/coverage/sync_fatal_alert/0.prim_sync_fatal_alert.69822289
Short name T66
Test name
Test status
Simulation time 27306182 ps
CPU time 0.38 seconds
Started Jul 21 04:23:50 PM PDT 24
Finished Jul 21 04:23:51 PM PDT 24
Peak memory 145412 kb
Host smart-ddd83861-d15b-4e87-a28b-3656afd0d28b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=69822289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.69822289
Directory /workspace/0.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/1.prim_sync_fatal_alert.1577267949
Short name T65
Test name
Test status
Simulation time 28844338 ps
CPU time 0.4 seconds
Started Jul 21 04:21:09 PM PDT 24
Finished Jul 21 04:21:10 PM PDT 24
Peak memory 145432 kb
Host smart-4914f6db-94a3-4913-a80b-44ef7acd3618
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1577267949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.1577267949
Directory /workspace/1.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/10.prim_sync_fatal_alert.61824791
Short name T61
Test name
Test status
Simulation time 26664563 ps
CPU time 0.39 seconds
Started Jul 21 04:23:14 PM PDT 24
Finished Jul 21 04:23:15 PM PDT 24
Peak memory 145432 kb
Host smart-f604dfbd-4f6a-4602-b1b8-a4756cad8a40
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=61824791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 10.prim_sync_fatal_alert.61824791
Directory /workspace/10.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/11.prim_sync_fatal_alert.1899894510
Short name T6
Test name
Test status
Simulation time 27633713 ps
CPU time 0.41 seconds
Started Jul 21 04:23:14 PM PDT 24
Finished Jul 21 04:23:15 PM PDT 24
Peak memory 145420 kb
Host smart-e4246320-7531-458e-9491-da3b1f8a42fe
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1899894510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 11.prim_sync_fatal_alert.1899894510
Directory /workspace/11.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/12.prim_sync_fatal_alert.2174912210
Short name T69
Test name
Test status
Simulation time 26493941 ps
CPU time 0.38 seconds
Started Jul 21 04:23:10 PM PDT 24
Finished Jul 21 04:23:11 PM PDT 24
Peak memory 145256 kb
Host smart-5c40d10b-4364-4825-9e38-e3e9809b8474
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2174912210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 12.prim_sync_fatal_alert.2174912210
Directory /workspace/12.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/13.prim_sync_fatal_alert.1609901901
Short name T76
Test name
Test status
Simulation time 28605181 ps
CPU time 0.4 seconds
Started Jul 21 04:19:01 PM PDT 24
Finished Jul 21 04:19:02 PM PDT 24
Peak memory 145460 kb
Host smart-941f6619-5990-4ddd-b794-fd78fef5fa22
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1609901901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 13.prim_sync_fatal_alert.1609901901
Directory /workspace/13.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/14.prim_sync_fatal_alert.1672770147
Short name T71
Test name
Test status
Simulation time 28441719 ps
CPU time 0.39 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:23:06 PM PDT 24
Peak memory 145168 kb
Host smart-b50ff651-e46e-470a-a692-e29d77fcc525
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1672770147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 14.prim_sync_fatal_alert.1672770147
Directory /workspace/14.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/15.prim_sync_fatal_alert.689966190
Short name T5
Test name
Test status
Simulation time 28388508 ps
CPU time 0.4 seconds
Started Jul 21 04:19:31 PM PDT 24
Finished Jul 21 04:19:32 PM PDT 24
Peak memory 145480 kb
Host smart-2e872858-baf3-42d0-b8d0-9897f19adf2d
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=689966190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 15.prim_sync_fatal_alert.689966190
Directory /workspace/15.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/16.prim_sync_fatal_alert.711579654
Short name T78
Test name
Test status
Simulation time 26128599 ps
CPU time 0.41 seconds
Started Jul 21 04:18:59 PM PDT 24
Finished Jul 21 04:19:00 PM PDT 24
Peak memory 144716 kb
Host smart-58b0597e-d1ba-4f6d-a896-136e23051df4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=711579654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 16.prim_sync_fatal_alert.711579654
Directory /workspace/16.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/17.prim_sync_fatal_alert.1598414147
Short name T75
Test name
Test status
Simulation time 28397272 ps
CPU time 0.4 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:23:07 PM PDT 24
Peak memory 145132 kb
Host smart-14403342-3e60-4a1b-8bc2-e98ed4cafa23
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1598414147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 17.prim_sync_fatal_alert.1598414147
Directory /workspace/17.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/18.prim_sync_fatal_alert.3657710789
Short name T67
Test name
Test status
Simulation time 26759849 ps
CPU time 0.39 seconds
Started Jul 21 04:23:06 PM PDT 24
Finished Jul 21 04:23:07 PM PDT 24
Peak memory 145100 kb
Host smart-43bb2033-3b68-4fb8-bc9f-eddd613192ef
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3657710789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 18.prim_sync_fatal_alert.3657710789
Directory /workspace/18.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/19.prim_sync_fatal_alert.3169158053
Short name T64
Test name
Test status
Simulation time 27852432 ps
CPU time 0.42 seconds
Started Jul 21 04:19:32 PM PDT 24
Finished Jul 21 04:19:33 PM PDT 24
Peak memory 145276 kb
Host smart-a1f2a90b-77fa-4bcc-b157-c452e61a3a9e
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3169158053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 19.prim_sync_fatal_alert.3169158053
Directory /workspace/19.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/2.prim_sync_fatal_alert.2351094954
Short name T73
Test name
Test status
Simulation time 28097257 ps
CPU time 0.49 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:38 PM PDT 24
Peak memory 142880 kb
Host smart-a56b7021-9263-446e-9894-5388a428c6ae
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2351094954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.2351094954
Directory /workspace/2.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/3.prim_sync_fatal_alert.3924038045
Short name T72
Test name
Test status
Simulation time 27170346 ps
CPU time 0.42 seconds
Started Jul 21 04:20:16 PM PDT 24
Finished Jul 21 04:20:17 PM PDT 24
Peak memory 145472 kb
Host smart-4c339cc9-96f5-4f02-9505-7e6d138e2b7b
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3924038045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.3924038045
Directory /workspace/3.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/4.prim_sync_fatal_alert.2649944143
Short name T68
Test name
Test status
Simulation time 25237314 ps
CPU time 0.5 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:38 PM PDT 24
Peak memory 143040 kb
Host smart-de70fa91-5bcf-4d87-870a-c82315fbb8a7
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2649944143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2649944143
Directory /workspace/4.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/5.prim_sync_fatal_alert.1125251790
Short name T77
Test name
Test status
Simulation time 26900166 ps
CPU time 0.4 seconds
Started Jul 21 04:18:53 PM PDT 24
Finished Jul 21 04:18:54 PM PDT 24
Peak memory 145444 kb
Host smart-277a3565-fbbc-42ac-86cb-5949d3683c00
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1125251790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1125251790
Directory /workspace/5.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/6.prim_sync_fatal_alert.365469386
Short name T70
Test name
Test status
Simulation time 30053618 ps
CPU time 0.4 seconds
Started Jul 21 04:24:17 PM PDT 24
Finished Jul 21 04:24:18 PM PDT 24
Peak memory 145256 kb
Host smart-7a7628f1-e5cb-4446-9baf-f47315a34202
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=365469386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.365469386
Directory /workspace/6.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/7.prim_sync_fatal_alert.2243232274
Short name T63
Test name
Test status
Simulation time 27815529 ps
CPU time 0.43 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:23:09 PM PDT 24
Peak memory 145200 kb
Host smart-c3a55079-f8a0-497a-b139-f2f7722f8ad8
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2243232274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.2243232274
Directory /workspace/7.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/8.prim_sync_fatal_alert.854553757
Short name T62
Test name
Test status
Simulation time 25921889 ps
CPU time 0.51 seconds
Started Jul 21 04:18:06 PM PDT 24
Finished Jul 21 04:18:07 PM PDT 24
Peak memory 144592 kb
Host smart-5c3c2fdd-edfe-4bb5-a56e-022c184ff2db
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=854553757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.854553757
Directory /workspace/8.prim_sync_fatal_alert/latest

Test location /workspace/coverage/sync_fatal_alert/9.prim_sync_fatal_alert.3644530694
Short name T74
Test name
Test status
Simulation time 27287725 ps
CPU time 0.46 seconds
Started Jul 21 04:19:15 PM PDT 24
Finished Jul 21 04:19:16 PM PDT 24
Peak memory 145240 kb
Host smart-38aef8e4-0731-4374-b40e-0709c1327cb4
User root
Command /workspace/sync_fatal_alert/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3644530694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3644530694
Directory /workspace/9.prim_sync_fatal_alert/latest
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