Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_sender	95.52	100.00	100.00	100.00	100.00	95.83	77.27

---

Module Instance : prim_alert_tb.i_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	193	32	32	100.00
ALWAYS	276	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	1	1
145	1	1
146	1	1
163	1	1
167	1	1
171	1	1
172	1	1
175	1	1
177	1	1
178	1	1
182	1	1
183	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
214	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE
226	1	1
227	1	1
229	1	1
230	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
242	1	1
246	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
282	1	1
283	1	1
284	1	1
285	1	1

---

Cond Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (ack_sigint | ping_sigint)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (alert_req | alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (alert_clr ? 1'b0 : alert_req_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (alert_test_i | alert_test_set_q)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (alert_clr ? 1'b0 : alert_test_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (alert_req_trigger | alert_test_trigger)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       177
 EXPRESSION (ping_set_q | ping_event)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (ping_clr ? 1'b0 : ping_trigger)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       182
 EXPRESSION (alert_clr & alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       202
 EXPRESSION (alert_trigger || ping_trigger)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (alert_trigger ? AlertHsPhase1 : PingHsPhase1)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T12,T13	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_ack_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_alert_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertHsPhase1	203	Covered	T1,T2,T3
AlertHsPhase2	211	Covered	T1,T2,T3
Idle	246	Covered	T1,T2,T3
Pause0	220	Covered	T1,T2,T3
Pause1	242	Covered	T1,T2,T3
PingHsPhase1	203	Covered	T1,T2,T3
PingHsPhase2	227	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertHsPhase1->AlertHsPhase2	211	Covered	T1,T2,T3
AlertHsPhase1->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Pause0	220	Covered	T1,T2,T3
Idle->AlertHsPhase1	203	Covered	T1,T2,T3
Idle->PingHsPhase1	203	Covered	T1,T2,T3
Pause0->Idle	256	Covered	T5,T28,T29
Pause0->Pause1	242	Covered	T1,T2,T3
Pause1->Idle	246	Covered	T1,T2,T3
PingHsPhase1->Idle	256	Covered	T2,T9,T7
PingHsPhase1->PingHsPhase2	227	Covered	T1,T2,T3
PingHsPhase2->Idle	256	Covered	T1,T3,T9
PingHsPhase2->Pause0	237	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	172	2	2	100.00
TERNARY	178	2	2	100.00
TERNARY	167	2	2	100.00
CASE	199	14	13	92.86
IF	255	2	2	100.00
IF	276	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	(ping_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	199	case (state_q)
-2-:	202	if ((alert_trigger || ping_trigger))
-3-:	203	(alert_trigger) ? 
-4-:	210	if (ack_level)
-5-:	219	if ((!ack_level))
-6-:	226	if (ack_level)
-7-:	235	if ((!ack_level))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	1	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	0	-	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	1	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	0	-	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	1	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	0	-	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	1	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	0	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	255	if (sigint_detected)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	276	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	17	77.27
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	17	77.27

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertHs_A	156819	1116	0	0
AlertPKnownO_A	156819	119396	0	0
AlertState0_A	156819	119396	0	0
AlertTest1_A	156819	80	0	0
AlertTestHs_A	156819	80	0	0
gen_async_assert.DiffEncoding_A	82958	57177	0	0
gen_async_assert.InBandInitFsm_A	82958	120	0	160
gen_async_assert.InBandInitPing_A	82958	120	0	160
gen_async_assert.PingHs_A	82958	383	0	0
gen_async_assert.SigIntAck_A	82958	120	0	200
gen_async_assert.SigIntPing_A	82958	120	0	200
gen_fatal_assert.AlertState1_A	115797	6464	0	0
gen_fatal_assert.AlertState2_A	115797	47139	0	0
gen_fatal_assert.AlertState3_A	115797	4310	0	0
gen_recov_assert.AlertState1_A	41022	6721	0	0
gen_recov_assert.AlertState2_A	41022	0	0	0
gen_sync_assert.DiffEncoding_A	73861	51273	0	0
gen_sync_assert.InBandInitFsm_A	73861	0	0	0
gen_sync_assert.InBandInitPing_A	73861	0	0	0
gen_sync_assert.PingHs_A	73861	368	0	0
gen_sync_assert.SigIntAck_A	73861	0	0	0
gen_sync_assert.SigIntPing_A	73861	0	0	0

AlertHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156819	1116	0	0
T1	1066	16	0	0
T2	1111	15	0	0
T3	1156	17	0	0
T7	1176	16	0	0
T9	1130	14	0	0
T10	1275	16	0	0
T12	1207	14	0	0
T19	1109	18	0	0
T20	1104	16	0	0
T21	1012	15	0	0

AlertPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156819	119396	0	0
T1	1066	1009	0	0
T2	1111	1039	0	0
T3	1156	1091	0	0
T7	1176	1088	0	0
T9	1130	1040	0	0
T10	1275	1086	0	0
T12	1207	1033	0	0
T19	1109	1017	0	0
T20	1104	1008	0	0
T21	1012	952	0	0

AlertState0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156819	119396	0	0
T1	1066	1009	0	0
T2	1111	1039	0	0
T3	1156	1091	0	0
T7	1176	1088	0	0
T9	1130	1040	0	0
T10	1275	1086	0	0
T12	1207	1033	0	0
T19	1109	1017	0	0
T20	1104	1008	0	0
T21	1012	952	0	0

AlertTest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156819	80	0	0
T1	1066	1	0	0
T2	1111	1	0	0
T3	1156	1	0	0
T7	1176	1	0	0
T9	1130	1	0	0
T10	1275	1	0	0
T12	1207	1	0	0
T19	1109	1	0	0
T20	1104	1	0	0
T21	1012	1	0	0

AlertTestHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156819	80	0	0
T1	1066	1	0	0
T2	1111	1	0	0
T3	1156	1	0	0
T7	1176	1	0	0
T9	1130	1	0	0
T10	1275	1	0	0
T12	1207	1	0	0
T19	1109	1	0	0
T20	1104	1	0	0
T21	1012	1	0	0

gen_async_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82958	57177	0	0
T1	1066	899	0	0
T2	1111	934	0	0
T3	1156	958	0	0
T7	1176	937	0	0
T9	1130	907	0	0
T10	1275	931	0	0
T12	1207	914	0	0
T19	1109	898	0	0
T20	1104	888	0	0
T21	1012	867	0	0

gen_async_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82958	120	0	160
T1	1066	3	0	4
T2	1111	3	0	4
T3	1156	4	0	4
T7	1176	3	0	4
T9	1130	2	0	4
T10	1275	3	0	4
T12	1207	4	0	4
T19	1109	4	0	4
T20	1104	3	0	4
T21	1012	3	0	4

gen_async_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82958	120	0	160
T1	1066	3	0	4
T2	1111	3	0	4
T3	1156	4	0	4
T7	1176	3	0	4
T9	1130	2	0	4
T10	1275	3	0	4
T12	1207	4	0	4
T19	1109	4	0	4
T20	1104	3	0	4
T21	1012	3	0	4

gen_async_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82958	383	0	0
T1	1066	9	0	0
T2	1111	10	0	0
T3	1156	9	0	0
T7	1176	9	0	0
T9	1130	10	0	0
T10	1275	10	0	0
T12	1207	10	0	0
T19	1109	10	0	0
T20	1104	9	0	0
T21	1012	10	0	0

gen_async_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82958	120	0	200
T1	1066	3	0	5
T2	1111	3	0	5
T3	1156	4	0	5
T7	1176	3	0	5
T9	1130	2	0	5
T10	1275	3	0	5
T12	1207	4	0	5
T19	1109	4	0	5
T20	1104	3	0	5
T21	1012	3	0	5

gen_async_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82958	120	0	200
T1	1066	3	0	5
T2	1111	3	0	5
T3	1156	4	0	5
T7	1176	3	0	5
T9	1130	2	0	5
T10	1275	3	0	5
T12	1207	4	0	5
T19	1109	4	0	5
T20	1104	3	0	5
T21	1012	3	0	5

gen_fatal_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115797	6464	0	0
T4	3017	231	0	0
T5	2887	247	0	0
T14	3147	191	0	0
T23	3009	251	0	0
T24	2929	242	0	0
T25	2992	255	0	0
T40	3104	278	0	0
T41	3085	260	0	0
T42	3012	215	0	0
T43	2956	248	0	0

gen_fatal_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115797	47139	0	0
T4	3017	1260	0	0
T5	2887	1136	0	0
T14	3147	1328	0	0
T23	3009	1265	0	0
T24	2929	1270	0	0
T25	2992	1247	0	0
T40	3104	1463	0	0
T41	3085	1328	0	0
T42	3012	1210	0	0
T43	2956	1245	0	0

gen_fatal_assert.AlertState3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115797	4310	0	0
T4	3017	67	0	0
T5	2887	58	0	0
T14	3147	70	0	0
T23	3009	63	0	0
T24	2929	65	0	0
T25	2992	63	0	0
T40	3104	74	0	0
T41	3085	67	0	0
T42	3012	63	0	0
T43	2956	63	0	0

gen_recov_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41022	6721	0	0
T1	1066	268	0	0
T2	1111	225	0	0
T3	1156	282	0	0
T7	1176	254	0	0
T9	1130	229	0	0
T10	1275	268	0	0
T12	1207	228	0	0
T19	1109	294	0	0
T20	1104	256	0	0
T21	1012	237	0	0

gen_recov_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41022	0	0	0

gen_sync_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73861	51273	0	0
T26	953	800	0	0
T27	912	761	0	0
T28	871	728	0	0
T29	967	814	0	0
T30	808	705	0	0
T31	1005	742	0	0
T36	880	762	0	0
T37	929	775	0	0
T38	844	719	0	0
T39	776	661	0	0

gen_sync_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73861	0	0	0

gen_sync_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73861	0	0	0

gen_sync_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73861	368	0	0
T26	953	8	0	0
T27	912	9	0	0
T28	871	8	0	0
T29	967	9	0	0
T30	808	9	0	0
T31	1005	8	0	0
T36	880	10	0	0
T37	929	10	0	0
T38	844	10	0	0
T39	776	10	0	0

gen_sync_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73861	0	0	0

gen_sync_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73861	0	0	0