Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T11
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T10	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T12
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T3,T13,T14
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T1,T3,T7
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T15,T9,T16

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	154485	116503	0	158
AlertKnownO_A	155185	118188	0	0
InBandInitRequest_A	155185	4112	0	0
InBandInitSequence_A	155185	405	0	0
InitReq_A	155185	769	0	0
IntegFailKnownO_A	155185	118188	0	0
NoSpuriousAlertsDuringInit_A	155185	16415	0	0
NoSpuriousPingOksDuringInit_A	155185	16050	0	0
PingDiffOk_A	154311	117314	0	0
PingOkBypassDuringInit_A	155185	41	0	40
PingOkKnownO_A	155185	118188	0	0
PingPKnownO_A	155185	118188	0	0
PingPending_A	155185	827	0	119
PingRequest0_A	155185	0	0	0
PingResponse0_A	155185	771	0	0
gen_async_assert.Alert_A	81596	1392	0	0
gen_async_assert.PingResponse1_A	81596	323	0	0
gen_async_assert.SigInt_A	81596	244	0	94
gen_sync_assert.Alert_A	73589	3127	0	0
gen_sync_assert.PingResponse1_A	73589	355	0	0
gen_sync_assert.SigInt_A	73589	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154485	116503	0	158
T1	1312	1130	0	2
T2	1065	994	0	2
T3	1241	1082	0	2
T7	1054	985	0	2
T10	1217	1053	0	2
T11	1067	980	0	2
T12	1197	1116	0	2
T17	957	900	0	2
T18	1060	989	0	2
T19	1091	1026	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	118188	0	0
T1	1327	1149	0	0
T2	1081	1012	0	0
T3	1256	1101	0	0
T7	1069	1002	0	0
T10	1232	1072	0	0
T11	1082	997	0	0
T12	1212	1133	0	0
T17	971	916	0	0
T18	1075	1006	0	0
T19	1106	1043	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	4112	0	0
T1	1327	84	0	0
T2	1081	38	0	0
T3	1256	61	0	0
T7	1069	19	0	0
T10	1232	66	0	0
T11	1082	46	0	0
T12	1212	69	0	0
T17	971	12	0	0
T18	1075	42	0	0
T19	1106	48	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	405	0	0
T1	1327	3	0	0
T2	1081	1	0	0
T3	1256	3	0	0
T7	1069	1	0	0
T10	1232	2	0	0
T11	1082	3	0	0
T12	1212	1	0	0
T15	0	1	0	0
T17	971	0	0	0
T18	1075	1	0	0
T19	1106	1	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	769	0	0
T1	1327	15	0	0
T2	1081	7	0	0
T3	1256	12	0	0
T7	1069	7	0	0
T10	1232	11	0	0
T11	1082	10	0	0
T12	1212	16	0	0
T17	971	3	0	0
T18	1075	9	0	0
T19	1106	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	118188	0	0
T1	1327	1149	0	0
T2	1081	1012	0	0
T3	1256	1101	0	0
T7	1069	1002	0	0
T10	1232	1072	0	0
T11	1082	997	0	0
T12	1212	1133	0	0
T17	971	916	0	0
T18	1075	1006	0	0
T19	1106	1043	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	16415	0	0
T1	1327	299	0	0
T2	1081	144	0	0
T3	1256	242	0	0
T7	1069	145	0	0
T10	1232	236	0	0
T11	1082	190	0	0
T12	1212	310	0	0
T17	971	70	0	0
T18	1075	188	0	0
T19	1106	183	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	16050	0	0
T1	1327	295	0	0
T2	1081	144	0	0
T3	1256	231	0	0
T7	1069	144	0	0
T10	1232	225	0	0
T11	1082	165	0	0
T12	1212	304	0	0
T17	971	68	0	0
T18	1075	187	0	0
T19	1106	183	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154311	117314	0	0
T1	1312	1134	0	0
T2	1067	998	0	0
T3	1238	1083	0	0
T7	1055	988	0	0
T10	1217	1057	0	0
T11	1068	983	0	0
T12	1198	1119	0	0
T17	958	903	0	0
T18	1062	993	0	0
T19	1092	1029	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	41	0	40
T1	1327	2	0	0
T2	1081	0	0	0
T3	1256	0	0	0
T7	1069	0	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	1232	0	0	0
T11	1082	1	0	0
T12	1212	0	0	0
T13	0	1	0	0
T17	971	0	0	0
T18	1075	1	0	0
T19	1106	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	3	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	118188	0	0
T1	1327	1149	0	0
T2	1081	1012	0	0
T3	1256	1101	0	0
T7	1069	1002	0	0
T10	1232	1072	0	0
T11	1082	997	0	0
T12	1212	1133	0	0
T17	971	916	0	0
T18	1075	1006	0	0
T19	1106	1043	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	118188	0	0
T1	1327	1149	0	0
T2	1081	1012	0	0
T3	1256	1101	0	0
T7	1069	1002	0	0
T10	1232	1072	0	0
T11	1082	997	0	0
T12	1212	1133	0	0
T17	971	916	0	0
T18	1075	1006	0	0
T19	1106	1043	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	827	0	119
T1	1327	11	0	1
T2	1081	11	0	1
T3	1256	11	0	1
T7	1069	11	0	1
T10	1232	11	0	1
T11	1082	11	0	1
T12	1212	11	0	1
T17	971	11	0	1
T18	1075	11	0	1
T19	1106	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155185	771	0	0
T1	1327	10	0	0
T2	1081	10	0	0
T3	1256	10	0	0
T7	1069	9	0	0
T10	1232	10	0	0
T11	1082	10	0	0
T12	1212	10	0	0
T17	971	10	0	0
T18	1075	10	0	0
T19	1106	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81596	1392	0	0
T1	1327	5	0	0
T2	1081	7	0	0
T3	1256	4	0	0
T7	1069	10	0	0
T10	1232	3	0	0
T11	1082	6	0	0
T12	1212	4	0	0
T17	971	10	0	0
T18	1075	7	0	0
T19	1106	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81596	323	0	0
T1	1327	7	0	0
T2	1081	10	0	0
T3	1256	10	0	0
T7	1069	9	0	0
T10	1232	9	0	0
T11	1082	9	0	0
T12	1212	7	0	0
T17	971	9	0	0
T18	1075	9	0	0
T19	1106	10	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81596	244	0	94
T1	1327	5	0	2
T2	1081	6	0	2
T3	1256	6	0	2
T7	1069	7	0	3
T10	1232	6	0	3
T11	1082	6	0	3
T12	1212	6	0	3
T17	971	7	0	3
T18	1075	5	0	2
T19	1106	7	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73589	3127	0	0
T14	987	9	0	0
T24	974	12	0	0
T25	1011	12	0	0
T26	899	13	0	0
T34	989	10	0	0
T35	998	9	0	0
T36	832	10	0	0
T37	911	9	0	0
T38	934	9	0	0
T39	908	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73589	355	0	0
T14	987	9	0	0
T24	974	9	0	0
T25	1011	8	0	0
T26	899	7	0	0
T34	989	10	0	0
T35	998	8	0	0
T36	832	10	0	0
T37	911	8	0	0
T38	934	9	0	0
T39	908	7	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73589	40	0	0
T14	987	1	0	0
T24	974	1	0	0
T25	1011	1	0	0
T26	899	1	0	0
T34	989	1	0	0
T35	998	1	0	0
T36	832	1	0	0
T37	911	1	0	0
T38	934	1	0	0
T39	908	1	0	0