Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T8,T9,T10

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T2,T3,T14
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T12,T15,T16
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T1,T17,T13
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T17,T18,T19

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	155492	117056	0	158
AlertKnownO_A	156190	118757	0	0
InBandInitRequest_A	156190	4032	0	0
InBandInitSequence_A	156190	436	0	0
InitReq_A	156190	779	0	0
IntegFailKnownO_A	156190	118757	0	0
NoSpuriousAlertsDuringInit_A	156190	16420	0	0
NoSpuriousPingOksDuringInit_A	156190	16062	0	0
PingDiffOk_A	155274	117841	0	0
PingOkBypassDuringInit_A	156190	51	0	40
PingOkKnownO_A	156190	118757	0	0
PingPKnownO_A	156190	118757	0	0
PingPending_A	156190	827	0	119
PingRequest0_A	156190	0	0	0
PingResponse0_A	156190	762	0	0
gen_async_assert.Alert_A	82086	1409	0	0
gen_async_assert.PingResponse1_A	82086	326	0	0
gen_async_assert.SigInt_A	82086	248	0	91
gen_sync_assert.Alert_A	74104	3128	0	0
gen_sync_assert.PingResponse1_A	74104	347	0	0
gen_sync_assert.SigInt_A	74104	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155492	117056	0	158
T1	1046	966	0	2
T2	1083	999	0	2
T3	1105	1035	0	2
T4	1081	991	0	2
T5	1004	948	0	2
T7	993	916	0	2
T11	1182	1073	0	2
T14	1047	989	0	2
T17	1092	1030	0	2
T20	1101	1005	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	118757	0	0
T1	1060	982	0	0
T2	1099	1017	0	0
T3	1119	1051	0	0
T4	1096	1008	0	0
T5	1019	965	0	0
T7	1009	934	0	0
T11	1198	1093	0	0
T14	1061	1005	0	0
T17	1107	1047	0	0
T20	1117	1023	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	4032	0	0
T1	1060	26	0	0
T2	1099	42	0	0
T3	1119	41	0	0
T4	1096	55	0	0
T5	1019	37	0	0
T7	1009	22	0	0
T11	1198	62	0	0
T14	1061	40	0	0
T17	1107	49	0	0
T20	1117	71	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	436	0	0
T1	1060	1	0	0
T2	1099	2	0	0
T3	1119	1	0	0
T4	1096	4	0	0
T5	1019	1	0	0
T7	1009	1	0	0
T11	1198	1	0	0
T14	1061	1	0	0
T17	1107	3	0	0
T20	1117	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	779	0	0
T1	1060	6	0	0
T2	1099	8	0	0
T3	1119	12	0	0
T4	1096	9	0	0
T5	1019	8	0	0
T7	1009	3	0	0
T11	1198	14	0	0
T14	1061	9	0	0
T17	1107	10	0	0
T20	1117	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	118757	0	0
T1	1060	982	0	0
T2	1099	1017	0	0
T3	1119	1051	0	0
T4	1096	1008	0	0
T5	1019	965	0	0
T7	1009	934	0	0
T11	1198	1093	0	0
T14	1061	1005	0	0
T17	1107	1047	0	0
T20	1117	1023	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	16420	0	0
T1	1060	128	0	0
T2	1099	166	0	0
T3	1119	236	0	0
T4	1096	178	0	0
T5	1019	160	0	0
T7	1009	70	0	0
T11	1198	283	0	0
T14	1061	176	0	0
T17	1107	198	0	0
T20	1117	182	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	16062	0	0
T1	1060	128	0	0
T2	1099	166	0	0
T3	1119	218	0	0
T4	1096	161	0	0
T5	1019	147	0	0
T7	1009	61	0	0
T11	1198	260	0	0
T14	1061	175	0	0
T17	1107	197	0	0
T20	1117	179	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155274	117841	0	0
T1	1042	964	0	0
T2	1082	1000	0	0
T3	1102	1034	0	0
T4	1081	993	0	0
T5	1002	948	0	0
T7	995	920	0	0
T11	1180	1075	0	0
T14	1045	989	0	0
T17	1102	1042	0	0
T20	1101	1007	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	51	0	40
T4	1096	2	0	0
T5	1019	0	0	0
T6	1072	0	0	0
T7	1009	0	0	0
T11	1198	1	0	0
T14	1061	1	0	0
T17	1107	1	0	0
T20	1117	1	0	0
T21	1139	1	0	0
T22	1075	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	118757	0	0
T1	1060	982	0	0
T2	1099	1017	0	0
T3	1119	1051	0	0
T4	1096	1008	0	0
T5	1019	965	0	0
T7	1009	934	0	0
T11	1198	1093	0	0
T14	1061	1005	0	0
T17	1107	1047	0	0
T20	1117	1023	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	118757	0	0
T1	1060	982	0	0
T2	1099	1017	0	0
T3	1119	1051	0	0
T4	1096	1008	0	0
T5	1019	965	0	0
T7	1009	934	0	0
T11	1198	1093	0	0
T14	1061	1005	0	0
T17	1107	1047	0	0
T20	1117	1023	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	827	0	119
T1	1060	11	0	1
T2	1099	11	0	1
T3	1119	11	0	1
T4	1096	11	0	1
T5	1019	11	0	1
T7	1009	11	0	1
T11	1198	11	0	1
T14	1061	11	0	1
T17	1107	10	0	1
T20	1117	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156190	762	0	0
T1	1060	10	0	0
T2	1099	10	0	0
T3	1119	10	0	0
T4	1096	9	0	0
T5	1019	8	0	0
T7	1009	10	0	0
T11	1198	10	0	0
T14	1061	10	0	0
T17	1107	10	0	0
T20	1117	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82086	1409	0	0
T1	1060	7	0	0
T2	1099	7	0	0
T3	1119	5	0	0
T4	1096	10	0	0
T5	1019	7	0	0
T7	1009	11	0	0
T11	1198	4	0	0
T14	1061	6	0	0
T17	1107	10	0	0
T20	1117	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82086	326	0	0
T1	1060	10	0	0
T2	1099	10	0	0
T3	1119	8	0	0
T4	1096	6	0	0
T5	1019	8	0	0
T7	1009	10	0	0
T11	1198	8	0	0
T14	1061	9	0	0
T17	1107	9	0	0
T20	1117	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82086	248	0	91
T1	1060	7	0	3
T2	1099	6	0	2
T3	1119	6	0	3
T4	1096	6	0	2
T5	1019	5	0	3
T7	1009	6	0	3
T11	1198	8	0	3
T14	1061	7	0	2
T17	1107	7	0	0
T20	1117	6	0	3
T21	0	0	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74104	3128	0	0
T26	970	8	0	0
T27	1078	11	0	0
T28	997	11	0	0
T29	954	9	0	0
T30	935	9	0	0
T31	973	10	0	0
T32	908	9	0	0
T36	1021	8	0	0
T37	892	11	0	0
T38	952	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74104	347	0	0
T26	970	8	0	0
T27	1078	8	0	0
T28	997	9	0	0
T29	954	8	0	0
T30	935	9	0	0
T31	973	8	0	0
T32	908	9	0	0
T36	1021	6	0	0
T37	892	9	0	0
T38	952	8	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74104	40	0	0
T26	970	1	0	0
T27	1078	1	0	0
T28	997	1	0	0
T29	954	1	0	0
T30	935	1	0	0
T31	973	1	0	0
T32	908	1	0	0
T36	1021	1	0	0
T37	892	1	0	0
T38	952	1	0	0