Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T11

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T1,T12
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T13,T14,T15
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T3,T7,T16

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	152282	114807	0	158
AlertKnownO_A	152970	116463	0	0
InBandInitRequest_A	152970	3999	0	0
InBandInitSequence_A	152970	419	0	0
InitReq_A	152970	742	0	0
IntegFailKnownO_A	152970	116463	0	0
NoSpuriousAlertsDuringInit_A	152970	15816	0	0
NoSpuriousPingOksDuringInit_A	152970	15432	0	0
PingDiffOk_A	152079	115572	0	0
PingOkBypassDuringInit_A	152970	55	0	40
PingOkKnownO_A	152970	116463	0	0
PingPKnownO_A	152970	116463	0	0
PingPending_A	152970	828	0	119
PingRequest0_A	152970	0	0	0
PingResponse0_A	152970	774	0	0
gen_async_assert.Alert_A	79925	1339	0	0
gen_async_assert.PingResponse1_A	79925	332	0	0
gen_async_assert.SigInt_A	79925	241	0	94
gen_sync_assert.Alert_A	73045	3094	0	0
gen_sync_assert.PingResponse1_A	73045	348	0	0
gen_sync_assert.SigInt_A	73045	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152282	114807	0	158
T1	1113	995	0	2
T2	1161	1002	0	2
T3	1283	1123	0	2
T7	1058	990	0	2
T10	1127	1026	0	2
T13	1168	1095	0	2
T14	1120	1065	0	2
T16	994	933	0	2
T17	1116	1036	0	2
T18	1127	975	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	116463	0	0
T1	1128	1014	0	0
T2	1177	1022	0	0
T3	1297	1141	0	0
T7	1074	1008	0	0
T10	1142	1043	0	0
T13	1183	1112	0	0
T14	1134	1081	0	0
T16	1007	948	0	0
T17	1132	1054	0	0
T18	1143	995	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	3999	0	0
T1	1128	28	0	0
T2	1177	37	0	0
T3	1297	81	0	0
T7	1074	46	0	0
T10	1142	21	0	0
T13	1183	63	0	0
T14	1134	78	0	0
T16	1007	31	0	0
T17	1132	63	0	0
T18	1143	21	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	419	0	0
T2	1177	1	0	0
T3	1297	4	0	0
T7	1074	0	0	0
T8	1104	4	0	0
T9	0	1	0	0
T10	1142	1	0	0
T13	1183	2	0	0
T14	1134	5	0	0
T16	1007	2	0	0
T17	1132	4	0	0
T18	1143	0	0	0
T19	0	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	742	0	0
T1	1128	7	0	0
T2	1177	9	0	0
T3	1297	13	0	0
T7	1074	9	0	0
T10	1142	9	0	0
T13	1183	13	0	0
T14	1134	13	0	0
T16	1007	6	0	0
T17	1132	10	0	0
T18	1143	5	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	116463	0	0
T1	1128	1014	0	0
T2	1177	1022	0	0
T3	1297	1141	0	0
T7	1074	1008	0	0
T10	1142	1043	0	0
T13	1183	1112	0	0
T14	1134	1081	0	0
T16	1007	948	0	0
T17	1132	1054	0	0
T18	1143	995	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	15816	0	0
T1	1128	162	0	0
T2	1177	190	0	0
T3	1297	272	0	0
T7	1074	178	0	0
T10	1142	180	0	0
T13	1183	248	0	0
T14	1134	249	0	0
T16	1007	124	0	0
T17	1132	200	0	0
T18	1143	124	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	15432	0	0
T1	1128	145	0	0
T2	1177	178	0	0
T3	1297	267	0	0
T7	1074	176	0	0
T10	1142	150	0	0
T13	1183	247	0	0
T14	1134	238	0	0
T16	1007	121	0	0
T17	1132	197	0	0
T18	1143	124	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152079	115572	0	0
T1	1110	996	0	0
T2	1162	1007	0	0
T3	1279	1123	0	0
T7	1060	994	0	0
T10	1125	1026	0	0
T13	1170	1099	0	0
T14	1117	1064	0	0
T16	991	932	0	0
T17	1122	1044	0	0
T18	1127	979	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	55	0	40
T2	1177	1	0	0
T3	1297	1	0	0
T7	1074	1	0	0
T8	1104	1	0	0
T10	1142	0	0	0
T13	1183	1	0	0
T14	1134	1	0	0
T16	1007	3	0	0
T17	1132	1	0	0
T18	1143	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	0	0	1
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	116463	0	0
T1	1128	1014	0	0
T2	1177	1022	0	0
T3	1297	1141	0	0
T7	1074	1008	0	0
T10	1142	1043	0	0
T13	1183	1112	0	0
T14	1134	1081	0	0
T16	1007	948	0	0
T17	1132	1054	0	0
T18	1143	995	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	116463	0	0
T1	1128	1014	0	0
T2	1177	1022	0	0
T3	1297	1141	0	0
T7	1074	1008	0	0
T10	1142	1043	0	0
T13	1183	1112	0	0
T14	1134	1081	0	0
T16	1007	948	0	0
T17	1132	1054	0	0
T18	1143	995	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	828	0	119
T1	1128	11	0	1
T2	1177	11	0	1
T3	1297	11	0	1
T7	1074	11	0	1
T10	1142	11	0	1
T13	1183	11	0	1
T14	1134	11	0	1
T16	1007	11	0	1
T17	1132	11	0	1
T18	1143	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152970	774	0	0
T1	1128	10	0	0
T2	1177	10	0	0
T3	1297	10	0	0
T7	1074	9	0	0
T10	1142	10	0	0
T13	1183	10	0	0
T14	1134	10	0	0
T16	1007	10	0	0
T17	1132	10	0	0
T18	1143	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79925	1339	0	0
T1	1128	9	0	0
T2	1177	9	0	0
T3	1297	6	0	0
T7	1074	8	0	0
T10	1142	9	0	0
T13	1183	8	0	0
T14	1134	5	0	0
T16	1007	11	0	0
T17	1132	6	0	0
T18	1143	9	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79925	332	0	0
T1	1128	9	0	0
T2	1177	8	0	0
T3	1297	7	0	0
T7	1074	8	0	0
T10	1142	10	0	0
T13	1183	9	0	0
T14	1134	9	0	0
T16	1007	7	0	0
T17	1132	8	0	0
T18	1143	10	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79925	241	0	94
T1	1128	8	0	2
T2	1177	8	0	2
T3	1297	6	0	3
T7	1074	7	0	2
T10	1142	5	0	3
T13	1183	6	0	3
T14	1134	5	0	3
T16	1007	5	0	3
T17	1132	6	0	0
T18	1143	6	0	3
T19	0	0	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73045	3094	0	0
T22	927	10	0	0
T23	886	10	0	0
T24	789	10	0	0
T25	1004	10	0	0
T26	915	11	0	0
T27	1001	9	0	0
T28	885	10	0	0
T32	945	8	0	0
T33	965	12	0	0
T34	944	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73045	348	0	0
T22	927	9	0	0
T23	886	8	0	0
T24	789	9	0	0
T25	1004	8	0	0
T26	915	8	0	0
T27	1001	7	0	0
T28	885	7	0	0
T32	945	8	0	0
T33	965	9	0	0
T34	944	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73045	40	0	0
T22	927	1	0	0
T23	886	1	0	0
T24	789	1	0	0
T25	1004	1	0	0
T26	915	1	0	0
T27	1001	1	0	0
T28	885	1	0	0
T32	945	1	0	0
T33	965	1	0	0
T34	944	1	0	0