Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T9,T10	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T7,T11
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T9,T12,T13
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T14,T8,T9
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T7,T15,T16

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	154341	116136	0	160
AlertKnownO_A	155045	117834	0	0
InBandInitRequest_A	155045	3979	0	0
InBandInitSequence_A	155045	391	0	0
InitReq_A	155045	747	0	0
IntegFailKnownO_A	155045	117834	0	0
NoSpuriousAlertsDuringInit_A	155045	16372	0	0
NoSpuriousPingOksDuringInit_A	155045	15966	0	0
PingDiffOk_A	154167	116956	0	0
PingOkBypassDuringInit_A	155045	53	0	40
PingOkKnownO_A	155045	117834	0	0
PingPKnownO_A	155045	117834	0	0
PingPending_A	155045	838	0	120
PingRequest0_A	155045	0	0	0
PingResponse0_A	155045	775	0	0
gen_async_assert.Alert_A	82527	1359	0	0
gen_async_assert.PingResponse1_A	82527	330	0	0
gen_async_assert.SigInt_A	82527	264	0	89
gen_sync_assert.Alert_A	72518	3100	0	0
gen_sync_assert.PingResponse1_A	72518	353	0	0
gen_sync_assert.SigInt_A	72518	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154341	116136	0	160
T1	1141	1046	0	2
T2	1033	966	0	2
T3	1069	984	0	2
T7	1047	984	0	2
T8	1226	1090	0	2
T9	1229	1073	0	2
T11	1115	1052	0	2
T14	1069	1006	0	2
T15	1123	1024	0	2
T17	1051	997	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	117834	0	0
T1	1156	1063	0	0
T2	1046	981	0	0
T3	1084	1001	0	0
T7	1060	999	0	0
T8	1241	1109	0	0
T9	1243	1091	0	0
T11	1129	1068	0	0
T14	1085	1024	0	0
T15	1138	1041	0	0
T17	1065	1013	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	3979	0	0
T1	1156	55	0	0
T2	1046	41	0	0
T3	1084	40	0	0
T7	1060	29	0	0
T8	1241	75	0	0
T9	1243	59	0	0
T11	1129	44	0	0
T14	1085	42	0	0
T15	1138	38	0	0
T17	1065	60	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	391	0	0
T1	1156	2	0	0
T2	1046	2	0	0
T3	1084	1	0	0
T7	1060	1	0	0
T8	1241	5	0	0
T9	1243	1	0	0
T11	1129	1	0	0
T14	1085	3	0	0
T15	1138	0	0	0
T17	1065	3	0	0
T18	0	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	747	0	0
T1	1156	10	0	0
T2	1046	7	0	0
T3	1084	8	0	0
T7	1060	7	0	0
T8	1241	14	0	0
T9	1243	11	0	0
T11	1129	11	0	0
T14	1085	7	0	0
T15	1138	9	0	0
T17	1065	11	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	117834	0	0
T1	1156	1063	0	0
T2	1046	981	0	0
T3	1084	1001	0	0
T7	1060	999	0	0
T8	1241	1109	0	0
T9	1243	1091	0	0
T11	1129	1068	0	0
T14	1085	1024	0	0
T15	1138	1041	0	0
T17	1065	1013	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	16372	0	0
T1	1156	206	0	0
T2	1046	144	0	0
T3	1084	166	0	0
T7	1060	150	0	0
T8	1241	269	0	0
T9	1243	237	0	0
T11	1129	216	0	0
T14	1085	146	0	0
T15	1138	180	0	0
T17	1065	216	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	15966	0	0
T1	1156	190	0	0
T2	1046	131	0	0
T3	1084	164	0	0
T7	1060	139	0	0
T8	1241	251	0	0
T9	1243	226	0	0
T11	1129	202	0	0
T14	1085	130	0	0
T15	1138	178	0	0
T17	1065	196	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154167	116956	0	0
T1	1138	1045	0	0
T2	1033	968	0	0
T3	1069	986	0	0
T7	1044	983	0	0
T8	1227	1095	0	0
T9	1227	1075	0	0
T11	1113	1052	0	0
T14	1069	1008	0	0
T15	1121	1024	0	0
T17	1052	1000	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	53	0	40
T1	0	0	0	1
T2	1046	2	0	0
T3	1084	0	0	0
T7	1060	0	0	0
T8	1241	1	0	0
T9	1243	1	0	0
T10	0	2	0	0
T11	1129	0	0	0
T14	1085	1	0	0
T15	1138	0	0	0
T17	1065	0	0	0
T18	1092	1	0	0
T19	0	3	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	117834	0	0
T1	1156	1063	0	0
T2	1046	981	0	0
T3	1084	1001	0	0
T7	1060	999	0	0
T8	1241	1109	0	0
T9	1243	1091	0	0
T11	1129	1068	0	0
T14	1085	1024	0	0
T15	1138	1041	0	0
T17	1065	1013	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	117834	0	0
T1	1156	1063	0	0
T2	1046	981	0	0
T3	1084	1001	0	0
T7	1060	999	0	0
T8	1241	1109	0	0
T9	1243	1091	0	0
T11	1129	1068	0	0
T14	1085	1024	0	0
T15	1138	1041	0	0
T17	1065	1013	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	838	0	120
T1	1156	11	0	1
T2	1046	11	0	1
T3	1084	11	0	1
T7	1060	11	0	1
T8	1241	11	0	1
T9	1243	11	0	1
T11	1129	11	0	1
T14	1085	11	0	1
T15	1138	11	0	1
T17	1065	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155045	775	0	0
T1	1156	8	0	0
T2	1046	10	0	0
T3	1084	9	0	0
T7	1060	9	0	0
T8	1241	10	0	0
T9	1243	10	0	0
T11	1129	8	0	0
T14	1085	10	0	0
T15	1138	10	0	0
T17	1065	9	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82527	1359	0	0
T1	1156	10	0	0
T2	1046	10	0	0
T3	1084	5	0	0
T7	1060	10	0	0
T8	1241	6	0	0
T9	1243	6	0	0
T11	1129	6	0	0
T14	1085	9	0	0
T15	1138	7	0	0
T17	1065	8	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82527	330	0	0
T1	1156	8	0	0
T2	1046	8	0	0
T3	1084	9	0	0
T7	1060	9	0	0
T8	1241	8	0	0
T9	1243	9	0	0
T11	1129	8	0	0
T14	1085	9	0	0
T15	1138	9	0	0
T17	1065	7	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82527	264	0	89
T1	1156	6	0	3
T2	1046	6	0	2
T3	1084	7	0	2
T7	1060	5	0	2
T8	1241	6	0	2
T9	1243	8	0	3
T11	1129	5	0	2
T14	1085	7	0	2
T15	1138	6	0	3
T17	1065	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72518	3100	0	0
T13	961	9	0	0
T23	1038	9	0	0
T24	937	8	0	0
T25	830	10	0	0
T26	794	12	0	0
T27	857	10	0	0
T32	872	6	0	0
T33	833	9	0	0
T34	999	11	0	0
T35	933	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72518	353	0	0
T13	961	10	0	0
T23	1038	9	0	0
T24	937	9	0	0
T25	830	9	0	0
T26	794	8	0	0
T27	857	9	0	0
T32	872	9	0	0
T33	833	10	0	0
T34	999	8	0	0
T35	933	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72518	40	0	0
T13	961	1	0	0
T23	1038	1	0	0
T24	937	1	0	0
T25	830	1	0	0
T26	794	1	0	0
T27	857	1	0	0
T32	872	1	0	0
T33	833	1	0	0
T34	999	1	0	0
T35	933	1	0	0