Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T2,T6,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T6,T9
1	0	Covered	T10,T11,T12

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T13,T14	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T13
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T2,T9,T15
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T2,T16,T17
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T2,T7,T15

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	149308	113252	0	156
AlertKnownO_A	149984	114874	0	0
InBandInitRequest_A	149984	4317	0	0
InBandInitSequence_A	149984	436	0	0
InitReq_A	149984	791	0	0
IntegFailKnownO_A	149984	114874	0	0
NoSpuriousAlertsDuringInit_A	149984	16234	0	0
NoSpuriousPingOksDuringInit_A	149984	15912	0	0
PingDiffOk_A	149121	114011	0	0
PingOkBypassDuringInit_A	149984	61	0	40
PingOkKnownO_A	149984	114874	0	0
PingPKnownO_A	149984	114874	0	0
PingPending_A	149984	818	0	118
PingRequest0_A	149984	0	0	0
PingResponse0_A	149984	758	0	0
gen_async_assert.Alert_A	77166	1258	0	0
gen_async_assert.PingResponse1_A	77166	305	0	0
gen_async_assert.SigInt_A	77166	249	0	87
gen_sync_assert.Alert_A	72818	3070	0	0
gen_sync_assert.PingResponse1_A	72818	341	0	0
gen_sync_assert.SigInt_A	72818	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149308	113252	0	156
T1	1060	985	0	2
T2	1263	1139	0	2
T3	1085	995	0	2
T8	1099	1008	0	2
T13	1168	1028	0	2
T14	1127	1015	0	2
T16	1124	1072	0	2
T17	1040	964	0	2
T18	1168	1082	0	2
T19	1011	955	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	114874	0	0
T1	1075	1002	0	0
T2	1279	1159	0	0
T3	1099	1011	0	0
T8	1114	1025	0	0
T13	1182	1046	0	0
T14	1142	1034	0	0
T16	1140	1090	0	0
T17	1054	980	0	0
T18	1183	1099	0	0
T19	1026	972	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	4317	0	0
T1	1075	58	0	0
T2	1279	93	0	0
T3	1099	37	0	0
T8	1114	42	0	0
T13	1182	55	0	0
T14	1142	25	0	0
T16	1140	75	0	0
T17	1054	36	0	0
T18	1183	75	0	0
T19	1026	31	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	436	0	0
T1	1075	2	0	0
T2	1279	6	0	0
T3	1099	2	0	0
T6	0	1	0	0
T8	1114	2	0	0
T13	1182	2	0	0
T14	1142	1	0	0
T16	1140	1	0	0
T17	1054	1	0	0
T18	1183	4	0	0
T19	1026	0	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	791	0	0
T1	1075	10	0	0
T2	1279	16	0	0
T3	1099	7	0	0
T8	1114	7	0	0
T13	1182	10	0	0
T14	1142	7	0	0
T16	1140	12	0	0
T17	1054	6	0	0
T18	1183	12	0	0
T19	1026	7	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	114874	0	0
T1	1075	1002	0	0
T2	1279	1159	0	0
T3	1099	1011	0	0
T8	1114	1025	0	0
T13	1182	1046	0	0
T14	1142	1034	0	0
T16	1140	1090	0	0
T17	1054	980	0	0
T18	1183	1099	0	0
T19	1026	972	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	16234	0	0
T1	1075	195	0	0
T2	1279	320	0	0
T3	1099	143	0	0
T8	1114	147	0	0
T13	1182	201	0	0
T14	1142	154	0	0
T16	1140	234	0	0
T17	1054	124	0	0
T18	1183	233	0	0
T19	1026	145	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	15912	0	0
T1	1075	190	0	0
T2	1279	317	0	0
T3	1099	142	0	0
T8	1114	136	0	0
T13	1182	197	0	0
T14	1142	153	0	0
T16	1140	231	0	0
T17	1054	123	0	0
T18	1183	229	0	0
T19	1026	142	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149121	114011	0	0
T1	1058	985	0	0
T2	1266	1146	0	0
T3	1083	995	0	0
T8	1096	1007	0	0
T13	1166	1030	0	0
T14	1125	1017	0	0
T16	1126	1076	0	0
T17	1038	964	0	0
T18	1167	1083	0	0
T19	1014	960	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	61	0	40
T1	1075	3	0	1
T2	1279	0	0	0
T3	1099	1	0	0
T6	0	1	0	0
T8	1114	0	0	0
T11	0	0	0	1
T13	1182	2	0	0
T14	1142	1	0	0
T16	1140	1	0	0
T17	1054	1	0	0
T18	1183	2	0	0
T19	1026	1	0	0
T20	0	1	0	0
T21	0	0	0	1
T22	0	0	0	1
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	114874	0	0
T1	1075	1002	0	0
T2	1279	1159	0	0
T3	1099	1011	0	0
T8	1114	1025	0	0
T13	1182	1046	0	0
T14	1142	1034	0	0
T16	1140	1090	0	0
T17	1054	980	0	0
T18	1183	1099	0	0
T19	1026	972	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	114874	0	0
T1	1075	1002	0	0
T2	1279	1159	0	0
T3	1099	1011	0	0
T8	1114	1025	0	0
T13	1182	1046	0	0
T14	1142	1034	0	0
T16	1140	1090	0	0
T17	1054	980	0	0
T18	1183	1099	0	0
T19	1026	972	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	818	0	118
T1	1075	11	0	1
T2	1279	11	0	1
T3	1099	11	0	1
T8	1114	11	0	1
T13	1182	11	0	1
T14	1142	11	0	1
T16	1140	11	0	1
T17	1054	11	0	1
T18	1183	11	0	1
T19	1026	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149984	758	0	0
T1	1075	10	0	0
T2	1279	9	0	0
T3	1099	10	0	0
T8	1114	10	0	0
T13	1182	10	0	0
T14	1142	10	0	0
T16	1140	10	0	0
T17	1054	10	0	0
T18	1183	10	0	0
T19	1026	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77166	1258	0	0
T1	1075	8	0	0
T2	1279	5	0	0
T3	1099	7	0	0
T8	1114	9	0	0
T13	1182	9	0	0
T14	1142	7	0	0
T16	1140	6	0	0
T17	1054	9	0	0
T18	1183	7	0	0
T19	1026	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77166	305	0	0
T1	1075	6	0	0
T2	1279	8	0	0
T3	1099	9	0	0
T8	1114	10	0	0
T13	1182	7	0	0
T14	1142	9	0	0
T16	1140	8	0	0
T17	1054	9	0	0
T18	1183	7	0	0
T19	1026	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77166	249	0	87
T1	1075	6	0	3
T2	1279	6	0	2
T3	1099	7	0	3
T8	1114	5	0	2
T13	1182	6	0	2
T14	1142	7	0	2
T16	1140	7	0	2
T17	1054	7	0	2
T18	1183	8	0	3
T19	1026	8	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72818	3070	0	0
T10	847	11	0	0
T21	925	9	0	0
T22	978	9	0	0
T23	892	8	0	0
T24	1036	9	0	0
T29	878	10	0	0
T30	979	10	0	0
T31	1019	10	0	0
T32	866	9	0	0
T33	1003	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72818	341	0	0
T10	847	8	0	0
T21	925	9	0	0
T22	978	8	0	0
T23	892	7	0	0
T24	1036	8	0	0
T29	878	9	0	0
T30	979	10	0	0
T31	1019	9	0	0
T32	866	9	0	0
T33	1003	8	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72818	40	0	0
T10	847	1	0	0
T21	925	1	0	0
T22	978	1	0	0
T23	892	1	0	0
T24	1036	1	0	0
T29	878	1	0	0
T30	979	1	0	0
T31	1019	1	0	0
T32	866	1	0	0
T33	1003	1	0	0