Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	94.30	100.00	94.74	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.30	100.00	94.74	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T8,T7	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T2,T3,T8
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T8,T9,T10
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T11,T12,T13
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T3,T14,T15

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	153863	115462	0	158
AlertKnownO_A	154553	117145	0	0
InBandInitRequest_A	154553	4213	0	0
InBandInitSequence_A	154553	421	0	0
InitReq_A	154553	759	0	0
IntegFailKnownO_A	154553	117145	0	0
NoSpuriousAlertsDuringInit_A	154553	16476	0	0
NoSpuriousPingOksDuringInit_A	154553	16170	0	0
PingDiffOk_A	153628	116220	0	0
PingOkBypassDuringInit_A	154553	40	0	40
PingOkKnownO_A	154553	117145	0	0
PingPKnownO_A	154553	117145	0	0
PingPending_A	154553	828	0	119
PingRequest0_A	154553	0	0	0
PingResponse0_A	154553	768	0	0
gen_async_assert.Alert_A	81457	1336	0	0
gen_async_assert.PingResponse1_A	81457	321	0	0
gen_async_assert.SigInt_A	81457	251	0	90
gen_sync_assert.Alert_A	73096	3087	0	0
gen_sync_assert.PingResponse1_A	73096	353	0	0
gen_sync_assert.SigInt_A	73096	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153863	115462	0	158
T1	1103	1019	0	2
T2	1134	1057	0	2
T3	1179	1037	0	2
T7	1193	1042	0	2
T8	1172	1049	0	2
T16	1090	1023	0	2
T17	1166	1079	0	2
T18	1092	1033	0	2
T19	1137	999	0	2
T20	1134	1062	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	117145	0	0
T1	1118	1036	0	0
T2	1149	1074	0	0
T3	1192	1053	0	0
T7	1207	1060	0	0
T8	1186	1067	0	0
T16	1104	1039	0	0
T17	1180	1095	0	0
T18	1108	1051	0	0
T19	1152	1018	0	0
T20	1149	1079	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	4213	0	0
T1	1118	33	0	0
T2	1149	77	0	0
T3	1192	62	0	0
T7	1207	47	0	0
T8	1186	58	0	0
T16	1104	46	0	0
T17	1180	78	0	0
T18	1108	46	0	0
T19	1152	48	0	0
T20	1149	79	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	421	0	0
T1	1118	1	0	0
T2	1149	3	0	0
T3	1192	3	0	0
T7	1207	2	0	0
T8	1186	2	0	0
T16	1104	2	0	0
T17	1180	5	0	0
T18	1108	2	0	0
T19	1152	1	0	0
T20	1149	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	759	0	0
T1	1118	10	0	0
T2	1149	12	0	0
T3	1192	10	0	0
T7	1207	8	0	0
T8	1186	10	0	0
T16	1104	10	0	0
T17	1180	13	0	0
T18	1108	9	0	0
T19	1152	9	0	0
T20	1149	13	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	117145	0	0
T1	1118	1036	0	0
T2	1149	1074	0	0
T3	1192	1053	0	0
T7	1207	1060	0	0
T8	1186	1067	0	0
T16	1104	1039	0	0
T17	1180	1095	0	0
T18	1108	1051	0	0
T19	1152	1018	0	0
T20	1149	1079	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	16476	0	0
T1	1118	194	0	0
T2	1149	236	0	0
T3	1192	201	0	0
T7	1207	185	0	0
T8	1186	213	0	0
T16	1104	200	0	0
T17	1180	257	0	0
T18	1108	182	0	0
T19	1152	194	0	0
T20	1149	255	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	16170	0	0
T1	1118	183	0	0
T2	1149	227	0	0
T3	1192	188	0	0
T7	1207	182	0	0
T8	1186	212	0	0
T16	1104	195	0	0
T17	1180	255	0	0
T18	1108	180	0	0
T19	1152	189	0	0
T20	1149	225	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153628	116220	0	0
T1	1106	1024	0	0
T2	1134	1059	0	0
T3	1174	1035	0	0
T7	1189	1042	0	0
T8	1174	1055	0	0
T16	1087	1022	0	0
T17	1162	1077	0	0
T18	1092	1035	0	0
T19	1138	1004	0	0
T20	1136	1066	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	40	0	40
T1	0	0	0	1
T7	1207	0	0	0
T8	1186	1	0	0
T10	0	0	0	1
T16	1104	1	0	0
T17	1180	2	0	0
T18	1108	0	0	0
T19	1152	0	0	0
T20	1149	1	0	0
T21	1116	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	1151	0	0	0
T28	1089	0	0	0
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1
T36	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	117145	0	0
T1	1118	1036	0	0
T2	1149	1074	0	0
T3	1192	1053	0	0
T7	1207	1060	0	0
T8	1186	1067	0	0
T16	1104	1039	0	0
T17	1180	1095	0	0
T18	1108	1051	0	0
T19	1152	1018	0	0
T20	1149	1079	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	117145	0	0
T1	1118	1036	0	0
T2	1149	1074	0	0
T3	1192	1053	0	0
T7	1207	1060	0	0
T8	1186	1067	0	0
T16	1104	1039	0	0
T17	1180	1095	0	0
T18	1108	1051	0	0
T19	1152	1018	0	0
T20	1149	1079	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	828	0	119
T1	1118	11	0	1
T2	1149	11	0	1
T3	1192	11	0	1
T7	1207	11	0	1
T8	1186	11	0	1
T16	1104	11	0	1
T17	1180	11	0	1
T18	1108	11	0	1
T19	1152	11	0	1
T20	1149	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154553	768	0	0
T1	1118	8	0	0
T2	1149	10	0	0
T3	1192	9	0	0
T7	1207	9	0	0
T8	1186	10	0	0
T16	1104	10	0	0
T17	1180	10	0	0
T18	1108	10	0	0
T19	1152	9	0	0
T20	1149	9	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81457	1336	0	0
T1	1118	8	0	0
T2	1149	5	0	0
T3	1192	7	0	0
T7	1207	7	0	0
T8	1186	6	0	0
T16	1104	6	0	0
T17	1180	5	0	0
T18	1108	9	0	0
T19	1152	7	0	0
T20	1149	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81457	321	0	0
T1	1118	8	0	0
T2	1149	9	0	0
T3	1192	8	0	0
T7	1207	8	0	0
T8	1186	9	0	0
T16	1104	7	0	0
T17	1180	8	0	0
T18	1108	9	0	0
T19	1152	7	0	0
T20	1149	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81457	251	0	90
T1	1118	7	0	2
T2	1149	8	0	2
T3	1192	5	0	2
T7	1207	6	0	2
T8	1186	8	0	1
T16	1104	5	0	2
T17	1180	5	0	3
T18	1108	8	0	2
T19	1152	6	0	2
T20	1149	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73096	3087	0	0
T29	880	10	0	0
T30	919	12	0	0
T31	1004	10	0	0
T37	851	11	0	0
T38	937	8	0	0
T39	917	11	0	0
T40	908	9	0	0
T41	925	9	0	0
T42	918	12	0	0
T43	980	12	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73096	353	0	0
T29	880	9	0	0
T30	919	9	0	0
T31	1004	9	0	0
T37	851	9	0	0
T38	937	9	0	0
T39	917	9	0	0
T40	908	8	0	0
T41	925	9	0	0
T42	918	10	0	0
T43	980	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73096	40	0	0
T29	880	1	0	0
T30	919	1	0	0
T31	1004	1	0	0
T37	851	1	0	0
T38	937	1	0	0
T39	917	1	0	0
T40	908	1	0	0
T41	925	1	0	0
T42	918	1	0	0
T43	980	1	0	0