Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T7,T8,T9
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T9
1	0	Covered	T10,T11,T5

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T12	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T13,T14,T15
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T2,T16,T17
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T8,T16,T13

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	155410	117012	0	160
AlertKnownO_A	156114	118704	0	0
InBandInitRequest_A	156114	3930	0	0
InBandInitSequence_A	156114	398	0	0
InitReq_A	156114	744	0	0
IntegFailKnownO_A	156114	118704	0	0
NoSpuriousAlertsDuringInit_A	156114	16135	0	0
NoSpuriousPingOksDuringInit_A	156114	15797	0	0
PingDiffOk_A	155212	117802	0	0
PingOkBypassDuringInit_A	156114	38	0	40
PingOkKnownO_A	156114	118704	0	0
PingPKnownO_A	156114	118704	0	0
PingPending_A	156114	839	0	120
PingRequest0_A	156114	0	0	0
PingResponse0_A	156114	779	0	0
gen_async_assert.Alert_A	82646	1389	0	0
gen_async_assert.PingResponse1_A	82646	344	0	0
gen_async_assert.SigInt_A	82646	248	0	96
gen_sync_assert.Alert_A	73468	3165	0	0
gen_sync_assert.PingResponse1_A	73468	349	0	0
gen_sync_assert.SigInt_A	73468	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155410	117012	0	160
T1	1091	1000	0	2
T2	1214	1095	0	2
T3	1149	1023	0	2
T7	1037	982	0	2
T8	1040	973	0	2
T12	1121	974	0	2
T18	1047	972	0	2
T19	1068	977	0	2
T20	1164	1068	0	2
T21	1176	1011	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	118704	0	0
T1	1106	1017	0	0
T2	1229	1114	0	0
T3	1163	1041	0	0
T7	1051	998	0	0
T8	1055	990	0	0
T12	1136	993	0	0
T18	1061	988	0	0
T19	1082	993	0	0
T20	1178	1084	0	0
T21	1190	1029	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	3930	0	0
T1	1106	28	0	0
T2	1229	56	0	0
T3	1163	55	0	0
T7	1051	34	0	0
T8	1055	40	0	0
T12	1136	48	0	0
T18	1061	44	0	0
T19	1082	43	0	0
T20	1178	45	0	0
T21	1190	46	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	398	0	0
T2	1229	1	0	0
T3	1163	3	0	0
T7	1051	1	0	0
T8	1055	1	0	0
T9	1125	2	0	0
T12	1136	2	0	0
T18	1061	1	0	0
T19	1082	2	0	0
T20	1178	0	0	0
T21	1190	2	0	0
T22	0	2	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	744	0	0
T1	1106	9	0	0
T2	1229	12	0	0
T3	1163	10	0	0
T7	1051	6	0	0
T8	1055	9	0	0
T12	1136	7	0	0
T18	1061	7	0	0
T19	1082	7	0	0
T20	1178	11	0	0
T21	1190	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	118704	0	0
T1	1106	1017	0	0
T2	1229	1114	0	0
T3	1163	1041	0	0
T7	1051	998	0	0
T8	1055	990	0	0
T12	1136	993	0	0
T18	1061	988	0	0
T19	1082	993	0	0
T20	1178	1084	0	0
T21	1190	1029	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	16135	0	0
T1	1106	183	0	0
T2	1229	249	0	0
T3	1163	218	0	0
T7	1051	129	0	0
T8	1055	184	0	0
T12	1136	151	0	0
T18	1061	142	0	0
T19	1082	151	0	0
T20	1178	210	0	0
T21	1190	199	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	15797	0	0
T1	1106	181	0	0
T2	1229	230	0	0
T3	1163	216	0	0
T7	1051	127	0	0
T8	1055	168	0	0
T12	1136	149	0	0
T18	1061	142	0	0
T19	1082	150	0	0
T20	1178	208	0	0
T21	1190	196	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155212	117802	0	0
T1	1089	1000	0	0
T2	1211	1096	0	0
T3	1144	1022	0	0
T7	1037	984	0	0
T8	1043	978	0	0
T12	1122	979	0	0
T18	1046	973	0	0
T19	1067	978	0	0
T20	1159	1065	0	0
T21	1176	1015	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	38	0	40
T3	1163	2	0	0
T7	1051	0	0	0
T8	1055	2	0	0
T9	1125	0	0	0
T11	0	0	0	1
T12	1136	2	0	0
T15	0	1	0	0
T16	0	2	0	0
T18	1061	0	0	0
T19	1082	1	0	0
T20	1178	0	0	0
T21	1190	1	0	0
T22	1158	2	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	118704	0	0
T1	1106	1017	0	0
T2	1229	1114	0	0
T3	1163	1041	0	0
T7	1051	998	0	0
T8	1055	990	0	0
T12	1136	993	0	0
T18	1061	988	0	0
T19	1082	993	0	0
T20	1178	1084	0	0
T21	1190	1029	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	118704	0	0
T1	1106	1017	0	0
T2	1229	1114	0	0
T3	1163	1041	0	0
T7	1051	998	0	0
T8	1055	990	0	0
T12	1136	993	0	0
T18	1061	988	0	0
T19	1082	993	0	0
T20	1178	1084	0	0
T21	1190	1029	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	839	0	120
T1	1106	11	0	1
T2	1229	11	0	1
T3	1163	11	0	1
T7	1051	11	0	1
T8	1055	11	0	1
T12	1136	11	0	1
T18	1061	11	0	1
T19	1082	11	0	1
T20	1178	11	0	1
T21	1190	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156114	779	0	0
T1	1106	10	0	0
T2	1229	10	0	0
T3	1163	10	0	0
T7	1051	9	0	0
T8	1055	9	0	0
T12	1136	10	0	0
T18	1061	10	0	0
T19	1082	10	0	0
T20	1178	10	0	0
T21	1190	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82646	1389	0	0
T1	1106	8	0	0
T2	1229	7	0	0
T3	1163	5	0	0
T7	1051	9	0	0
T8	1055	9	0	0
T12	1136	8	0	0
T18	1061	6	0	0
T19	1082	8	0	0
T20	1178	5	0	0
T21	1190	5	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82646	344	0	0
T1	1106	9	0	0
T2	1229	8	0	0
T3	1163	8	0	0
T7	1051	9	0	0
T8	1055	7	0	0
T12	1136	8	0	0
T18	1061	10	0	0
T19	1082	9	0	0
T20	1178	9	0	0
T21	1190	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82646	248	0	96
T1	1106	6	0	3
T2	1229	6	0	2
T3	1163	6	0	3
T7	1051	5	0	2
T8	1055	8	0	2
T12	1136	6	0	3
T18	1061	5	0	3
T19	1082	5	0	2
T20	1178	7	0	3
T21	1190	6	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73468	3165	0	0
T25	895	11	0	0
T26	1016	10	0	0
T27	911	11	0	0
T28	899	9	0	0
T34	993	11	0	0
T35	870	9	0	0
T36	928	11	0	0
T37	860	9	0	0
T38	866	11	0	0
T39	888	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73468	349	0	0
T25	895	8	0	0
T26	1016	8	0	0
T27	911	9	0	0
T28	899	8	0	0
T34	993	8	0	0
T35	870	9	0	0
T36	928	10	0	0
T37	860	8	0	0
T38	866	8	0	0
T39	888	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73468	40	0	0
T25	895	1	0	0
T26	1016	1	0	0
T27	911	1	0	0
T28	899	1	0	0
T34	993	1	0	0
T35	870	1	0	0
T36	928	1	0	0
T37	860	1	0	0
T38	866	1	0	0
T39	888	1	0	0