Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T7
1	0	Covered	T9,T10

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T11,T12	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T2,T3,T6
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T12
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T1,T3,T7
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T2,T6,T13

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	153292	116156	0	158
AlertKnownO_A	153986	117808	0	0
InBandInitRequest_A	153986	4192	0	0
InBandInitSequence_A	153986	408	0	0
InitReq_A	153986	809	0	0
IntegFailKnownO_A	153986	117808	0	0
NoSpuriousAlertsDuringInit_A	153986	16730	0	0
NoSpuriousPingOksDuringInit_A	153986	16367	0	0
PingDiffOk_A	153069	116891	0	0
PingOkBypassDuringInit_A	153986	40	0	40
PingOkKnownO_A	153986	117808	0	0
PingPKnownO_A	153986	117808	0	0
PingPending_A	153986	829	0	119
PingRequest0_A	153986	0	0	0
PingResponse0_A	153986	767	0	0
gen_async_assert.Alert_A	80563	1328	0	0
gen_async_assert.PingResponse1_A	80563	318	0	0
gen_async_assert.SigInt_A	80563	242	0	95
gen_sync_assert.Alert_A	73423	3106	0	0
gen_sync_assert.PingResponse1_A	73423	362	0	0
gen_sync_assert.SigInt_A	73423	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153292	116156	0	158
T1	1103	1027	0	2
T2	1181	1100	0	2
T3	1076	996	0	2
T6	1135	1041	0	2
T7	1190	1107	0	2
T8	1131	967	0	2
T11	1196	1036	0	2
T14	1111	1046	0	2
T15	1069	1010	0	2
T16	1228	1136	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	117808	0	0
T1	1119	1045	0	0
T2	1195	1116	0	0
T3	1091	1013	0	0
T6	1150	1058	0	0
T7	1206	1125	0	0
T8	1145	985	0	0
T11	1212	1056	0	0
T14	1126	1063	0	0
T15	1084	1027	0	0
T16	1243	1153	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	4192	0	0
T1	1119	63	0	0
T2	1195	93	0	0
T3	1091	53	0	0
T6	1150	55	0	0
T7	1206	65	0	0
T8	1145	49	0	0
T11	1212	88	0	0
T14	1126	55	0	0
T15	1084	42	0	0
T16	1243	54	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	408	0	0
T2	1195	5	0	0
T3	1091	2	0	0
T6	1150	0	0	0
T7	1206	1	0	0
T8	1145	4	0	0
T11	1212	3	0	0
T14	1126	1	0	0
T15	1084	1	0	0
T16	1243	1	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	1163	0	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	809	0	0
T1	1119	11	0	0
T2	1195	13	0	0
T3	1091	8	0	0
T6	1150	12	0	0
T7	1206	15	0	0
T8	1145	7	0	0
T11	1212	13	0	0
T14	1126	9	0	0
T15	1084	9	0	0
T16	1243	15	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	117808	0	0
T1	1119	1045	0	0
T2	1195	1116	0	0
T3	1091	1013	0	0
T6	1150	1058	0	0
T7	1206	1125	0	0
T8	1145	985	0	0
T11	1212	1056	0	0
T14	1126	1063	0	0
T15	1084	1027	0	0
T16	1243	1153	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	16730	0	0
T1	1119	209	0	0
T2	1195	250	0	0
T3	1091	158	0	0
T6	1150	233	0	0
T7	1206	289	0	0
T8	1145	153	0	0
T11	1212	257	0	0
T14	1126	185	0	0
T15	1084	173	0	0
T16	1243	296	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	16367	0	0
T1	1119	207	0	0
T2	1195	246	0	0
T3	1091	157	0	0
T6	1150	217	0	0
T7	1206	274	0	0
T8	1145	126	0	0
T11	1212	242	0	0
T14	1126	185	0	0
T15	1084	170	0	0
T16	1243	294	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153069	116891	0	0
T1	1103	1029	0	0
T2	1181	1102	0	0
T3	1077	999	0	0
T6	1134	1042	0	0
T7	1192	1111	0	0
T8	1127	967	0	0
T11	1196	1040	0	0
T14	1109	1046	0	0
T15	1069	1012	0	0
T16	1227	1137	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	40	0	40
T3	1091	1	0	0
T6	1150	2	0	0
T7	1206	0	0	0
T8	1145	1	0	0
T11	1212	1	0	0
T14	1126	0	0	0
T15	1084	0	0	0
T16	1243	2	0	0
T17	1049	0	0	0
T19	1163	1	0	0
T20	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	117808	0	0
T1	1119	1045	0	0
T2	1195	1116	0	0
T3	1091	1013	0	0
T6	1150	1058	0	0
T7	1206	1125	0	0
T8	1145	985	0	0
T11	1212	1056	0	0
T14	1126	1063	0	0
T15	1084	1027	0	0
T16	1243	1153	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	117808	0	0
T1	1119	1045	0	0
T2	1195	1116	0	0
T3	1091	1013	0	0
T6	1150	1058	0	0
T7	1206	1125	0	0
T8	1145	985	0	0
T11	1212	1056	0	0
T14	1126	1063	0	0
T15	1084	1027	0	0
T16	1243	1153	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	829	0	119
T1	1119	11	0	1
T2	1195	11	0	1
T3	1091	11	0	1
T6	1150	11	0	1
T7	1206	11	0	1
T8	1145	11	0	1
T11	1212	11	0	1
T14	1126	11	0	1
T15	1084	11	0	1
T16	1243	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153986	767	0	0
T1	1119	8	0	0
T2	1195	10	0	0
T3	1091	10	0	0
T6	1150	9	0	0
T7	1206	9	0	0
T8	1145	10	0	0
T11	1212	9	0	0
T14	1126	10	0	0
T15	1084	9	0	0
T16	1243	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80563	1328	0	0
T1	1119	6	0	0
T2	1195	6	0	0
T3	1091	7	0	0
T6	1150	7	0	0
T7	1206	5	0	0
T8	1145	11	0	0
T11	1212	4	0	0
T14	1126	6	0	0
T15	1084	8	0	0
T16	1243	6	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80563	318	0	0
T1	1119	8	0	0
T2	1195	8	0	0
T3	1091	9	0	0
T6	1150	7	0	0
T7	1206	8	0	0
T8	1145	8	0	0
T11	1212	8	0	0
T14	1126	10	0	0
T15	1084	8	0	0
T16	1243	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80563	242	0	95
T1	1119	6	0	3
T2	1195	6	0	2
T3	1091	6	0	3
T6	1150	7	0	3
T7	1206	8	0	2
T8	1145	6	0	3
T11	1212	7	0	2
T14	1126	5	0	2
T15	1084	6	0	2
T16	1243	5	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73423	3106	0	0
T9	906	11	0	0
T24	828	9	0	0
T25	873	9	0	0
T34	993	7	0	0
T35	998	9	0	0
T36	967	10	0	0
T37	980	11	0	0
T38	815	8	0	0
T39	924	10	0	0
T40	891	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73423	362	0	0
T9	906	9	0	0
T24	828	9	0	0
T25	873	6	0	0
T34	993	9	0	0
T35	998	9	0	0
T36	967	9	0	0
T37	980	10	0	0
T38	815	9	0	0
T39	924	9	0	0
T40	891	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73423	40	0	0
T9	906	1	0	0
T24	828	1	0	0
T25	873	1	0	0
T34	993	1	0	0
T35	998	1	0	0
T36	967	1	0	0
T37	980	1	0	0
T38	815	1	0	0
T39	924	1	0	0
T40	891	1	0	0