Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T6
1	0	Covered	T8,T9

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T11,T12	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T13
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T1,T14,T15
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T16,T17,T18

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	151797	114969	0	158
AlertKnownO_A	152497	116635	0	0
InBandInitRequest_A	152497	4057	0	0
InBandInitSequence_A	152497	415	0	0
InitReq_A	152497	770	0	0
IntegFailKnownO_A	152497	116635	0	0
NoSpuriousAlertsDuringInit_A	152497	16225	0	0
NoSpuriousPingOksDuringInit_A	152497	15808	0	0
PingDiffOk_A	151586	115724	0	0
PingOkBypassDuringInit_A	152497	34	0	40
PingOkKnownO_A	152497	116635	0	0
PingPKnownO_A	152497	116635	0	0
PingPending_A	152497	827	0	119
PingRequest0_A	152497	0	0	0
PingResponse0_A	152497	768	0	0
gen_async_assert.Alert_A	79325	1305	0	0
gen_async_assert.PingResponse1_A	79325	329	0	0
gen_async_assert.SigInt_A	79325	252	0	85
gen_sync_assert.Alert_A	73172	3101	0	0
gen_sync_assert.PingResponse1_A	73172	354	0	0
gen_sync_assert.SigInt_A	73172	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151797	114969	0	158
T1	1061	993	0	2
T2	1071	1010	0	2
T3	1104	1035	0	2
T6	1138	1079	0	2
T7	1111	1030	0	2
T10	1155	995	0	2
T14	1157	1093	0	2
T16	1090	1032	0	2
T19	1084	1006	0	2
T20	1129	1045	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	116635	0	0
T1	1076	1010	0	0
T2	1087	1028	0	0
T3	1119	1052	0	0
T6	1154	1097	0	0
T7	1126	1047	0	0
T10	1170	1014	0	0
T14	1172	1110	0	0
T16	1104	1048	0	0
T19	1099	1023	0	0
T20	1145	1063	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	4057	0	0
T1	1076	64	0	0
T2	1087	51	0	0
T3	1119	54	0	0
T6	1154	59	0	0
T7	1126	43	0	0
T10	1170	33	0	0
T14	1172	71	0	0
T16	1104	58	0	0
T19	1099	42	0	0
T20	1145	33	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	415	0	0
T1	1076	6	0	0
T2	1087	1	0	0
T3	1119	3	0	0
T6	1154	1	0	0
T7	1126	2	0	0
T10	1170	2	0	0
T14	1172	3	0	0
T16	1104	1	0	0
T19	1099	1	0	0
T20	1145	0	0	0
T21	0	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	770	0	0
T1	1076	10	0	0
T2	1087	12	0	0
T3	1119	11	0	0
T6	1154	14	0	0
T7	1126	9	0	0
T10	1170	8	0	0
T14	1172	13	0	0
T16	1104	11	0	0
T19	1099	9	0	0
T20	1145	10	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	116635	0	0
T1	1076	1010	0	0
T2	1087	1028	0	0
T3	1119	1052	0	0
T6	1154	1097	0	0
T7	1126	1047	0	0
T10	1170	1014	0	0
T14	1172	1110	0	0
T16	1104	1048	0	0
T19	1099	1023	0	0
T20	1145	1063	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	16225	0	0
T1	1076	195	0	0
T2	1087	239	0	0
T3	1119	214	0	0
T6	1154	266	0	0
T7	1126	185	0	0
T10	1170	184	0	0
T14	1172	248	0	0
T16	1104	214	0	0
T19	1099	174	0	0
T20	1145	206	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	15808	0	0
T1	1076	188	0	0
T2	1087	234	0	0
T3	1119	188	0	0
T6	1154	236	0	0
T7	1126	169	0	0
T10	1170	184	0	0
T14	1172	246	0	0
T16	1104	211	0	0
T19	1099	164	0	0
T20	1145	205	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151586	115724	0	0
T1	1060	994	0	0
T2	1072	1013	0	0
T3	1102	1035	0	0
T6	1136	1079	0	0
T7	1109	1030	0	0
T10	1153	997	0	0
T14	1159	1097	0	0
T16	1099	1043	0	0
T19	1084	1008	0	0
T20	1128	1046	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	34	0	40
T1	1076	1	0	0
T2	1087	2	0	0
T3	1119	0	0	0
T6	1154	0	0	0
T7	1126	0	0	0
T10	1170	0	0	0
T14	1172	0	0	0
T16	1104	0	0	0
T19	1099	0	0	0
T20	1145	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T28	0	2	0	0
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1
T35	0	0	0	1
T36	0	0	0	1
T37	0	0	0	1
T38	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	116635	0	0
T1	1076	1010	0	0
T2	1087	1028	0	0
T3	1119	1052	0	0
T6	1154	1097	0	0
T7	1126	1047	0	0
T10	1170	1014	0	0
T14	1172	1110	0	0
T16	1104	1048	0	0
T19	1099	1023	0	0
T20	1145	1063	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	116635	0	0
T1	1076	1010	0	0
T2	1087	1028	0	0
T3	1119	1052	0	0
T6	1154	1097	0	0
T7	1126	1047	0	0
T10	1170	1014	0	0
T14	1172	1110	0	0
T16	1104	1048	0	0
T19	1099	1023	0	0
T20	1145	1063	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	827	0	119
T1	1076	11	0	1
T2	1087	11	0	1
T3	1119	11	0	1
T6	1154	11	0	1
T7	1126	11	0	1
T10	1170	11	0	1
T14	1172	11	0	1
T16	1104	10	0	1
T19	1099	11	0	1
T20	1145	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152497	768	0	0
T1	1076	9	0	0
T2	1087	9	0	0
T3	1119	10	0	0
T6	1154	9	0	0
T7	1126	10	0	0
T10	1170	10	0	0
T14	1172	10	0	0
T16	1104	9	0	0
T19	1099	10	0	0
T20	1145	9	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79325	1305	0	0
T1	1076	9	0	0
T2	1087	5	0	0
T3	1119	7	0	0
T6	1154	6	0	0
T7	1126	5	0	0
T10	1170	7	0	0
T14	1172	6	0	0
T16	1104	8	0	0
T19	1099	6	0	0
T20	1145	7	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79325	329	0	0
T1	1076	6	0	0
T2	1087	6	0	0
T3	1119	8	0	0
T6	1154	9	0	0
T7	1126	10	0	0
T10	1170	10	0	0
T14	1172	9	0	0
T16	1104	8	0	0
T19	1099	10	0	0
T20	1145	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79325	252	0	85
T1	1076	8	0	2
T2	1087	6	0	3
T3	1119	6	0	3
T6	1154	6	0	3
T7	1126	6	0	3
T10	1170	7	0	2
T11	0	0	0	2
T14	1172	8	0	2
T16	1104	7	0	0
T19	1099	7	0	3
T20	1145	6	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73172	3101	0	0
T29	929	6	0	0
T30	1044	10	0	0
T31	995	9	0	0
T32	821	10	0	0
T33	977	11	0	0
T39	999	9	0	0
T40	910	8	0	0
T41	930	10	0	0
T42	894	10	0	0
T43	837	11	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73172	354	0	0
T29	929	7	0	0
T30	1044	7	0	0
T31	995	8	0	0
T32	821	7	0	0
T33	977	7	0	0
T39	999	10	0	0
T40	910	7	0	0
T41	930	8	0	0
T42	894	10	0	0
T43	837	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73172	40	0	0
T29	929	1	0	0
T30	1044	1	0	0
T31	995	1	0	0
T32	821	1	0	0
T33	977	1	0	0
T39	999	1	0	0
T40	910	1	0	0
T41	930	1	0	0
T42	894	1	0	0
T43	837	1	0	0