Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T10
1	0	Covered	T11,T12,T13

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T14,T15,T16	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T3,T9
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T17
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T18,T19,T20
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T21,T18,T22

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	152102	115052	0	158
AlertKnownO_A	152798	116706	0	0
InBandInitRequest_A	152798	4060	0	0
InBandInitSequence_A	152798	425	0	0
InitReq_A	152798	766	0	0
IntegFailKnownO_A	152798	116706	0	0
NoSpuriousAlertsDuringInit_A	152798	16056	0	0
NoSpuriousPingOksDuringInit_A	152798	15750	0	0
PingDiffOk_A	151891	115799	0	0
PingOkBypassDuringInit_A	152798	63	0	40
PingOkKnownO_A	152798	116706	0	0
PingPKnownO_A	152798	116706	0	0
PingPending_A	152798	828	0	119
PingRequest0_A	152798	0	0	0
PingResponse0_A	152798	768	0	0
gen_async_assert.Alert_A	79419	1300	0	0
gen_async_assert.PingResponse1_A	79419	323	0	0
gen_async_assert.SigInt_A	79419	240	0	99
gen_sync_assert.Alert_A	73379	3168	0	0
gen_sync_assert.PingResponse1_A	73379	348	0	0
gen_sync_assert.SigInt_A	73379	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152102	115052	0	158
T1	1077	1001	0	2
T2	1071	1008	0	2
T3	1085	987	0	2
T7	1068	994	0	2
T9	1112	1053	0	2
T14	1205	1058	0	2
T18	1043	967	0	2
T21	1103	1016	0	2
T23	1101	1016	0	2
T24	1091	1019	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	116706	0	0
T1	1092	1018	0	0
T2	1085	1024	0	0
T3	1099	1003	0	0
T7	1084	1012	0	0
T9	1127	1070	0	0
T14	1220	1077	0	0
T18	1058	984	0	0
T21	1118	1033	0	0
T23	1114	1031	0	0
T24	1107	1037	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	4060	0	0
T1	1092	59	0	0
T2	1085	33	0	0
T3	1099	32	0	0
T7	1084	45	0	0
T9	1127	56	0	0
T14	1220	47	0	0
T18	1058	47	0	0
T21	1118	60	0	0
T23	1114	29	0	0
T24	1107	57	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	425	0	0
T1	1092	1	0	0
T2	1085	1	0	0
T3	1099	1	0	0
T7	1084	1	0	0
T9	1127	1	0	0
T14	1220	1	0	0
T18	1058	2	0	0
T21	1118	4	0	0
T23	1114	1	0	0
T24	1107	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	766	0	0
T1	1092	9	0	0
T2	1085	7	0	0
T3	1099	7	0	0
T7	1084	10	0	0
T9	1127	11	0	0
T14	1220	10	0	0
T18	1058	9	0	0
T21	1118	9	0	0
T23	1114	7	0	0
T24	1107	10	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	116706	0	0
T1	1092	1018	0	0
T2	1085	1024	0	0
T3	1099	1003	0	0
T7	1084	1012	0	0
T9	1127	1070	0	0
T14	1220	1077	0	0
T18	1058	984	0	0
T21	1118	1033	0	0
T23	1114	1031	0	0
T24	1107	1037	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	16056	0	0
T1	1092	180	0	0
T2	1085	147	0	0
T3	1099	149	0	0
T7	1084	201	0	0
T9	1127	231	0	0
T14	1220	226	0	0
T18	1058	171	0	0
T21	1118	179	0	0
T23	1114	145	0	0
T24	1107	202	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	15750	0	0
T1	1092	177	0	0
T2	1085	125	0	0
T3	1099	149	0	0
T7	1084	198	0	0
T9	1127	217	0	0
T14	1220	225	0	0
T18	1058	167	0	0
T21	1118	176	0	0
T23	1114	145	0	0
T24	1107	198	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151891	115799	0	0
T1	1078	1004	0	0
T2	1067	1006	0	0
T3	1082	986	0	0
T7	1067	995	0	0
T9	1109	1052	0	0
T14	1205	1062	0	0
T18	1042	968	0	0
T21	1104	1019	0	0
T23	1100	1017	0	0
T24	1092	1022	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	63	0	40
T2	1085	1	0	0
T3	1099	0	0	0
T7	1084	2	0	0
T8	1156	1	0	0
T9	1127	1	0	0
T10	0	1	0	0
T12	0	0	0	1
T14	1220	1	0	0
T15	0	2	0	0
T18	1058	2	0	0
T21	1118	1	0	0
T23	1114	0	0	0
T24	1107	0	0	0
T25	0	1	0	0
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1
T34	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	116706	0	0
T1	1092	1018	0	0
T2	1085	1024	0	0
T3	1099	1003	0	0
T7	1084	1012	0	0
T9	1127	1070	0	0
T14	1220	1077	0	0
T18	1058	984	0	0
T21	1118	1033	0	0
T23	1114	1031	0	0
T24	1107	1037	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	116706	0	0
T1	1092	1018	0	0
T2	1085	1024	0	0
T3	1099	1003	0	0
T7	1084	1012	0	0
T9	1127	1070	0	0
T14	1220	1077	0	0
T18	1058	984	0	0
T21	1118	1033	0	0
T23	1114	1031	0	0
T24	1107	1037	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	828	0	119
T1	1092	11	0	1
T2	1085	11	0	1
T3	1099	11	0	1
T7	1084	11	0	1
T9	1127	11	0	1
T14	1220	11	0	1
T18	1058	11	0	1
T21	1118	11	0	1
T23	1114	11	0	1
T24	1107	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152798	768	0	0
T1	1092	9	0	0
T2	1085	10	0	0
T3	1099	10	0	0
T7	1084	9	0	0
T9	1127	10	0	0
T14	1220	10	0	0
T18	1058	10	0	0
T21	1118	10	0	0
T23	1114	10	0	0
T24	1107	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79419	1300	0	0
T1	1092	9	0	0
T2	1085	8	0	0
T3	1099	8	0	0
T7	1084	9	0	0
T9	1127	6	0	0
T14	1220	6	0	0
T18	1058	9	0	0
T21	1118	7	0	0
T23	1114	9	0	0
T24	1107	5	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79419	323	0	0
T1	1092	8	0	0
T2	1085	9	0	0
T3	1099	10	0	0
T7	1084	7	0	0
T9	1127	8	0	0
T14	1220	9	0	0
T18	1058	7	0	0
T21	1118	8	0	0
T23	1114	10	0	0
T24	1107	8	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79419	240	0	99
T1	1092	5	0	3
T2	1085	7	0	3
T3	1099	5	0	3
T7	1084	7	0	2
T9	1127	7	0	3
T14	1220	7	0	3
T18	1058	5	0	2
T21	1118	8	0	3
T23	1114	7	0	3
T24	1107	8	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73379	3168	0	0
T11	882	9	0	0
T17	1003	8	0	0
T26	956	9	0	0
T27	1033	8	0	0
T28	930	10	0	0
T29	951	9	0	0
T30	986	9	0	0
T31	913	11	0	0
T35	814	11	0	0
T36	899	10	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73379	348	0	0
T11	882	6	0	0
T17	1003	8	0	0
T26	956	8	0	0
T27	1033	9	0	0
T28	930	8	0	0
T29	951	9	0	0
T30	986	9	0	0
T31	913	9	0	0
T35	814	9	0	0
T36	899	10	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73379	40	0	0
T11	882	1	0	0
T17	1003	1	0	0
T26	956	1	0	0
T27	1033	1	0	0
T28	930	1	0	0
T29	951	1	0	0
T30	986	1	0	0
T31	913	1	0	0
T35	814	1	0	0
T36	899	1	0	0