Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5
1	0	1	Covered	T2,T6,T7
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T9

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T10,T11,T12	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T12,T13,T14
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T6,T15,T16
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T10,T17,T18

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	153964	116326	0	158
AlertKnownO_A	154669	118007	0	0
InBandInitRequest_A	154669	4276	0	0
InBandInitSequence_A	154669	423	0	0
InitReq_A	154669	788	0	0
IntegFailKnownO_A	154669	118007	0	0
NoSpuriousAlertsDuringInit_A	154669	16585	0	0
NoSpuriousPingOksDuringInit_A	154669	16156	0	0
PingDiffOk_A	153787	117125	0	0
PingOkBypassDuringInit_A	154669	45	0	40
PingOkKnownO_A	154669	118007	0	0
PingPKnownO_A	154669	118007	0	0
PingPending_A	154669	826	0	119
PingRequest0_A	154669	0	0	0
PingResponse0_A	154669	768	0	0
gen_async_assert.Alert_A	80877	1320	0	0
gen_async_assert.PingResponse1_A	80877	319	0	0
gen_async_assert.SigInt_A	80877	250	0	85
gen_sync_assert.Alert_A	73792	3166	0	0
gen_sync_assert.PingResponse1_A	73792	356	0	0
gen_sync_assert.SigInt_A	73792	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153964	116326	0	158
T1	1102	1023	0	2
T2	1160	1098	0	2
T3	1073	1003	0	2
T6	1064	984	0	2
T7	1180	1083	0	2
T8	1145	1078	0	2
T10	1270	1092	0	2
T17	1066	971	0	2
T19	1146	1051	0	2
T20	1045	977	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	118007	0	0
T1	1116	1039	0	0
T2	1175	1115	0	0
T3	1088	1020	0	0
T6	1079	1001	0	0
T7	1194	1099	0	0
T8	1160	1095	0	0
T10	1286	1112	0	0
T17	1081	988	0	0
T19	1162	1069	0	0
T20	1059	993	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	4276	0	0
T1	1116	47	0	0
T2	1175	81	0	0
T3	1088	51	0	0
T6	1079	53	0	0
T7	1194	77	0	0
T8	1160	50	0	0
T10	1286	74	0	0
T17	1081	62	0	0
T19	1162	69	0	0
T20	1059	43	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	423	0	0
T1	1116	1	0	0
T2	1175	5	0	0
T3	1088	2	0	0
T6	1079	2	0	0
T7	1194	4	0	0
T8	1160	1	0	0
T10	1286	2	0	0
T17	1081	4	0	0
T19	1162	4	0	0
T20	1059	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	788	0	0
T1	1116	9	0	0
T2	1175	13	0	0
T3	1088	10	0	0
T6	1079	8	0	0
T7	1194	14	0	0
T8	1160	11	0	0
T10	1286	13	0	0
T17	1081	9	0	0
T19	1162	11	0	0
T20	1059	9	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	118007	0	0
T1	1116	1039	0	0
T2	1175	1115	0	0
T3	1088	1020	0	0
T6	1079	1001	0	0
T7	1194	1099	0	0
T8	1160	1095	0	0
T10	1286	1112	0	0
T17	1081	988	0	0
T19	1162	1069	0	0
T20	1059	993	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	16585	0	0
T1	1116	180	0	0
T2	1175	255	0	0
T3	1088	196	0	0
T6	1079	161	0	0
T7	1194	272	0	0
T8	1160	219	0	0
T10	1286	270	0	0
T17	1081	182	0	0
T19	1162	212	0	0
T20	1059	172	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	16156	0	0
T1	1116	167	0	0
T2	1175	252	0	0
T3	1088	179	0	0
T6	1079	160	0	0
T7	1194	268	0	0
T8	1160	205	0	0
T10	1286	262	0	0
T17	1081	178	0	0
T19	1162	206	0	0
T20	1059	168	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153787	117125	0	0
T1	1098	1021	0	0
T2	1163	1103	0	0
T3	1070	1002	0	0
T6	1062	984	0	0
T7	1177	1082	0	0
T8	1147	1082	0	0
T10	1268	1094	0	0
T17	1066	973	0	0
T19	1147	1054	0	0
T20	1042	976	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	45	0	40
T1	1116	1	0	0
T2	1175	0	0	0
T3	1088	2	0	0
T6	1079	0	0	0
T7	1194	2	0	0
T8	1160	1	0	0
T9	0	0	0	1
T10	1286	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	0	1	0	0
T17	1081	2	0	0
T18	0	2	0	0
T19	1162	0	0	0
T20	1059	2	0	0
T21	0	0	0	1
T22	0	0	0	1
T23	0	0	0	1
T24	0	0	0	1
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	118007	0	0
T1	1116	1039	0	0
T2	1175	1115	0	0
T3	1088	1020	0	0
T6	1079	1001	0	0
T7	1194	1099	0	0
T8	1160	1095	0	0
T10	1286	1112	0	0
T17	1081	988	0	0
T19	1162	1069	0	0
T20	1059	993	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	118007	0	0
T1	1116	1039	0	0
T2	1175	1115	0	0
T3	1088	1020	0	0
T6	1079	1001	0	0
T7	1194	1099	0	0
T8	1160	1095	0	0
T10	1286	1112	0	0
T17	1081	988	0	0
T19	1162	1069	0	0
T20	1059	993	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	826	0	119
T1	1116	11	0	1
T2	1175	11	0	1
T3	1088	11	0	1
T6	1079	11	0	1
T7	1194	11	0	1
T8	1160	11	0	1
T10	1286	11	0	1
T17	1081	11	0	1
T19	1162	11	0	1
T20	1059	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154669	768	0	0
T1	1116	10	0	0
T2	1175	9	0	0
T3	1088	10	0	0
T6	1079	9	0	0
T7	1194	9	0	0
T8	1160	10	0	0
T10	1286	9	0	0
T17	1081	10	0	0
T19	1162	10	0	0
T20	1059	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80877	1320	0	0
T1	1116	9	0	0
T2	1175	5	0	0
T3	1088	7	0	0
T6	1079	6	0	0
T7	1194	3	0	0
T8	1160	9	0	0
T10	1286	6	0	0
T17	1081	8	0	0
T19	1162	7	0	0
T20	1059	8	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80877	319	0	0
T1	1116	9	0	0
T2	1175	8	0	0
T3	1088	8	0	0
T6	1079	9	0	0
T7	1194	7	0	0
T8	1160	8	0	0
T10	1286	6	0	0
T17	1081	7	0	0
T19	1162	7	0	0
T20	1059	7	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80877	250	0	85
T1	1116	5	0	3
T2	1175	6	0	2
T3	1088	5	0	3
T6	1079	7	0	2
T7	1194	5	0	2
T8	1160	8	0	3
T10	1286	8	0	3
T17	1081	8	0	2
T19	1162	7	0	3
T20	1059	7	0	2

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73792	3166	0	0
T21	915	9	0	0
T22	1011	10	0	0
T23	964	8	0	0
T30	886	10	0	0
T31	1040	9	0	0
T32	862	11	0	0
T33	938	8	0	0
T34	983	11	0	0
T35	1033	7	0	0
T36	951	9	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73792	356	0	0
T21	915	7	0	0
T22	1011	8	0	0
T23	964	7	0	0
T30	886	10	0	0
T31	1040	10	0	0
T32	862	9	0	0
T33	938	10	0	0
T34	983	10	0	0
T35	1033	8	0	0
T36	951	9	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73792	40	0	0
T21	915	1	0	0
T22	1011	1	0	0
T23	964	1	0	0
T30	886	1	0	0
T31	1040	1	0	0
T32	862	1	0	0
T33	938	1	0	0
T34	983	1	0	0
T35	1033	1	0	0
T36	951	1	0	0