Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_receiver	95.18	100.00	100.00	100.00	80.00	95.83	95.24

---

Module Instance : prim_alert_tb.i_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	100.00	100.00	80.00	95.83	95.24

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
TOTAL		60	60	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
ALWAYS	159	43	43	100.00
ALWAYS	253	7	7	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
107	1	1
111	1	1
112	1	1
144	1	1
147	1	1
148	1	1
150	1	1
151	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
184	1	1
185	1	1
187	1	1
191	1	1
192	1	1
197	1	1
199	1	1
204	1	1
205	1	1
208	1	1
209	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
223	1	1
			MISSING_ELSE
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
			MISSING_ELSE
			MISSING_ELSE
253	1	1
256	1	1
257	1	1
258	1	1
260	1	1
261	1	1
262	1	1

---

Cond Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       106
 EXPRESSION (ping_req_d && ((!ping_req_q)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (send_init ? 1'b0 : (send_ping ? ((~ping_tog_pq)) : ping_tog_pq))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION (send_ping ? ((~ping_tog_pq)) : ping_tog_pq)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 EXPRESSION (send_init ? ack_pd : ((~ack_pd)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (ping_rise | (((~ping_ok_o)) & ping_req_i & ping_pending_q))
             ----1----   -----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (((~ping_ok_o)) & ping_req_i & ping_pending_q)
                 -------1------   -----2----   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (ping_rise || ping_pending_q)
             ----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T11

---

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T12,T13,T14	Yes	T1,T2,T3	INPUT
init_trig_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_i.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_alert_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	12	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
HsAckWait	172	Covered	T1,T2,T3
Idle	192	Covered	T1,T2,T3
InitAckWait	209	Covered	T1,T2,T3
InitReq	234	Covered	T1,T2,T3
Pause0	185	Covered	T1,T2,T3
Pause1	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
HsAckWait->Idle	243	Covered	T1,T2,T3
HsAckWait->InitReq	234	Covered	T1,T2,T3
HsAckWait->Pause0	185	Covered	T1,T2,T3
Idle->HsAckWait	172	Covered	T1,T2,T3
Idle->InitReq	234	Covered	T1,T2,T3
InitAckWait->Idle	243	Not Covered
InitAckWait->InitReq	234	Covered	T12,T15
InitAckWait->Pause0	219	Covered	T1,T2,T3
InitReq->Idle	243	Not Covered
InitReq->InitAckWait	209	Covered	T1,T2,T3
Pause0->Idle	243	Not Covered
Pause0->InitReq	234	Covered	T16,T17,T15
Pause0->Pause1	191	Covered	T1,T2,T3
Pause1->Idle	192	Covered	T1,T2,T3
Pause1->InitReq	234	Covered	T1,T13,T14

---

Branch Coverage for Module : prim_alert_receiver

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	107	3	3	100.00
TERNARY	111	2	2	100.00
CASE	168	13	12	92.31
IF	231	4	4	100.00
IF	253	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	107	(send_init) ? 
-2-:	107	(send_ping) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	(send_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (alert_level)
-3-:	175	if (ping_pending_q)
-4-:	184	if ((!alert_level))
-5-:	204	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-6-:	208	if (alert_sigint)
-7-:	218	if ((!alert_sigint))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	1	-	-	-	Covered	T1,T2,T3
HsAckWait	-	-	0	-	-	-	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
InitReq	-	-	-	1	-	-	Covered	T1,T2,T3
InitReq	-	-	-	0	1	-	Covered	T1,T2,T3
InitReq	-	-	-	0	0	-	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	1	Covered	T1,T2,T3
InitAckWait	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	231	if ((!(state_q inside {InitReq, InitAckWait})))
-2-:	233	if (prim_mubi_pkg::mubi4_test_true_strict(init_trig_i))
-3-:	242	if (alert_sigint)

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	20	95.24
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	20	95.24

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckDiffOk_A	155519	117423	0	160
AlertKnownO_A	156225	119126	0	0
InBandInitRequest_A	156225	4434	0	0
InBandInitSequence_A	156225	444	0	0
InitReq_A	156225	785	0	0
IntegFailKnownO_A	156225	119126	0	0
NoSpuriousAlertsDuringInit_A	156225	16892	0	0
NoSpuriousPingOksDuringInit_A	156225	16525	0	0
PingDiffOk_A	155296	118197	0	0
PingOkBypassDuringInit_A	156225	51	0	40
PingOkKnownO_A	156225	119126	0	0
PingPKnownO_A	156225	119126	0	0
PingPending_A	156225	840	0	120
PingRequest0_A	156225	0	0	0
PingResponse0_A	156225	777	0	0
gen_async_assert.Alert_A	82141	1349	0	0
gen_async_assert.PingResponse1_A	82141	319	0	0
gen_async_assert.SigInt_A	82141	260	0	104
gen_sync_assert.Alert_A	74084	3202	0	0
gen_sync_assert.PingResponse1_A	74084	352	0	0
gen_sync_assert.SigInt_A	74084	40	0	0

AckDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155519	117423	0	160
T1	1055	968	0	2
T2	1033	972	0	2
T3	1094	1028	0	2
T7	1115	1056	0	2
T12	1189	997	0	2
T13	1221	1080	0	2
T18	1097	1015	0	2
T19	1129	1053	0	2
T20	1114	1041	0	2
T21	1026	945	0	2

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	119126	0	0
T1	1070	985	0	0
T2	1047	988	0	0
T3	1109	1045	0	0
T7	1130	1073	0	0
T12	1204	1016	0	0
T13	1235	1098	0	0
T18	1110	1030	0	0
T19	1144	1070	0	0
T20	1129	1058	0	0
T21	1042	963	0	0

InBandInitRequest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	4434	0	0
T1	1070	36	0	0
T2	1047	50	0	0
T3	1109	32	0	0
T7	1130	39	0	0
T12	1204	31	0	0
T13	1235	98	0	0
T18	1110	61	0	0
T19	1144	60	0	0
T20	1129	72	0	0
T21	1042	42	0	0

InBandInitSequence_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	444	0	0
T1	1070	2	0	0
T2	1047	1	0	0
T3	1109	2	0	0
T7	1130	2	0	0
T12	1204	1	0	0
T13	1235	6	0	0
T18	1110	3	0	0
T19	1144	3	0	0
T20	1129	4	0	0
T21	1042	3	0	0

InitReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	785	0	0
T1	1070	7	0	0
T2	1047	9	0	0
T3	1109	10	0	0
T7	1130	8	0	0
T12	1204	8	0	0
T13	1235	16	0	0
T18	1110	10	0	0
T19	1144	9	0	0
T20	1129	12	0	0
T21	1042	6	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	119126	0	0
T1	1070	985	0	0
T2	1047	988	0	0
T3	1109	1045	0	0
T7	1130	1073	0	0
T12	1204	1016	0	0
T13	1235	1098	0	0
T18	1110	1030	0	0
T19	1144	1070	0	0
T20	1129	1058	0	0
T21	1042	963	0	0

NoSpuriousAlertsDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	16892	0	0
T1	1070	148	0	0
T2	1047	182	0	0
T3	1109	201	0	0
T7	1130	167	0	0
T12	1204	181	0	0
T13	1235	324	0	0
T18	1110	198	0	0
T19	1144	182	0	0
T20	1129	231	0	0
T21	1042	123	0	0

NoSpuriousPingOksDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	16525	0	0
T1	1070	137	0	0
T2	1047	166	0	0
T3	1109	185	0	0
T7	1130	166	0	0
T12	1204	168	0	0
T13	1235	314	0	0
T18	1110	192	0	0
T19	1144	182	0	0
T20	1129	222	0	0
T21	1042	122	0	0

PingDiffOk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155296	118197	0	0
T1	1052	967	0	0
T2	1031	972	0	0
T3	1093	1029	0	0
T7	1115	1058	0	0
T12	1188	1000	0	0
T13	1221	1084	0	0
T18	1093	1013	0	0
T19	1128	1054	0	0
T20	1113	1042	0	0
T21	1028	949	0	0

PingOkBypassDuringInit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	51	0	40
T1	1070	1	0	0
T2	1047	0	0	0
T3	1109	0	0	0
T7	1130	0	0	0
T8	0	2	0	0
T11	0	0	0	1
T12	1204	0	0	0
T13	1235	4	0	0
T14	0	1	0	0
T16	0	1	0	0
T18	1110	0	0	0
T19	1144	0	0	0
T20	1129	1	0	0
T21	1042	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	2	0	0
T25	0	0	0	1
T26	0	0	0	1
T27	0	0	0	1
T28	0	0	0	1
T29	0	0	0	1
T30	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T33	0	0	0	1

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	119126	0	0
T1	1070	985	0	0
T2	1047	988	0	0
T3	1109	1045	0	0
T7	1130	1073	0	0
T12	1204	1016	0	0
T13	1235	1098	0	0
T18	1110	1030	0	0
T19	1144	1070	0	0
T20	1129	1058	0	0
T21	1042	963	0	0

PingPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	119126	0	0
T1	1070	985	0	0
T2	1047	988	0	0
T3	1109	1045	0	0
T7	1130	1073	0	0
T12	1204	1016	0	0
T13	1235	1098	0	0
T18	1110	1030	0	0
T19	1144	1070	0	0
T20	1129	1058	0	0
T21	1042	963	0	0

PingPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	840	0	120
T1	1070	11	0	1
T2	1047	11	0	1
T3	1109	11	0	1
T7	1130	11	0	1
T12	1204	11	0	1
T13	1235	11	0	1
T18	1110	11	0	1
T19	1144	11	0	1
T20	1129	11	0	1
T21	1042	11	0	1

PingRequest0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	0	0	0

PingResponse0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	777	0	0
T1	1070	10	0	0
T2	1047	7	0	0
T3	1109	10	0	0
T7	1130	9	0	0
T12	1204	10	0	0
T13	1235	10	0	0
T18	1110	10	0	0
T19	1144	10	0	0
T20	1129	10	0	0
T21	1042	10	0	0

gen_async_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	1349	0	0
T1	1070	9	0	0
T2	1047	9	0	0
T3	1109	6	0	0
T7	1130	6	0	0
T12	1204	9	0	0
T13	1235	5	0	0
T18	1110	6	0	0
T19	1144	6	0	0
T20	1129	6	0	0
T21	1042	9	0	0

gen_async_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	319	0	0
T1	1070	9	0	0
T2	1047	6	0	0
T3	1109	10	0	0
T7	1130	9	0	0
T12	1204	9	0	0
T13	1235	3	0	0
T18	1110	7	0	0
T19	1144	10	0	0
T20	1129	9	0	0
T21	1042	9	0	0

gen_async_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	260	0	104
T1	1070	8	0	2
T2	1047	7	0	3
T3	1109	8	0	3
T7	1130	6	0	2
T12	1204	6	0	2
T13	1235	5	0	2
T18	1110	5	0	2
T19	1144	7	0	3
T20	1129	5	0	3
T21	1042	6	0	3

gen_sync_assert.Alert_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	3202	0	0
T25	840	12	0	0
T26	887	11	0	0
T27	804	10	0	0
T28	1030	6	0	0
T29	871	8	0	0
T34	885	12	0	0
T35	941	12	0	0
T36	936	11	0	0
T37	952	10	0	0
T38	823	12	0	0

gen_sync_assert.PingResponse1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	352	0	0
T25	840	9	0	0
T26	887	8	0	0
T27	804	9	0	0
T28	1030	8	0	0
T29	871	9	0	0
T34	885	9	0	0
T35	941	9	0	0
T36	936	10	0	0
T37	952	10	0	0
T38	823	7	0	0

gen_sync_assert.SigInt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	40	0	0
T25	840	1	0	0
T26	887	1	0	0
T27	804	1	0	0
T28	1030	1	0	0
T29	871	1	0	0
T34	885	1	0	0
T35	941	1	0	0
T36	936	1	0	0
T37	952	1	0	0
T38	823	1	0	0