Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_sender	95.52	100.00	100.00	100.00	100.00	95.83	77.27

---

Module Instance : prim_alert_tb.i_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	193	32	32	100.00
ALWAYS	276	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	1	1
145	1	1
146	1	1
163	1	1
167	1	1
171	1	1
172	1	1
175	1	1
177	1	1
178	1	1
182	1	1
183	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
202	1	1
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
214	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE
226	1	1
227	1	1
229	1	1
230	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
242	1	1
246	1	1
255	1	1
256	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
282	1	1
283	1	1
284	1	1
285	1	1

---

Cond Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (ack_sigint | ping_sigint)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (alert_req | alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (alert_clr ? 1'b0 : alert_req_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (alert_test_i | alert_test_set_q)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (alert_clr ? 1'b0 : alert_test_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (alert_req_trigger | alert_test_trigger)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       177
 EXPRESSION (ping_set_q | ping_event)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (ping_clr ? 1'b0 : ping_trigger)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       182
 EXPRESSION (alert_clr & alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       202
 EXPRESSION (alert_trigger || ping_trigger)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (alert_trigger ? AlertHsPhase1 : PingHsPhase1)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T12,T13,T14	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_ack_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_alert_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertHsPhase1	203	Covered	T1,T2,T3
AlertHsPhase2	211	Covered	T1,T2,T3
Idle	246	Covered	T1,T2,T3
Pause0	220	Covered	T1,T2,T3
Pause1	242	Covered	T1,T2,T3
PingHsPhase1	203	Covered	T1,T2,T3
PingHsPhase2	227	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertHsPhase1->AlertHsPhase2	211	Covered	T1,T2,T3
AlertHsPhase1->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Pause0	220	Covered	T1,T2,T3
Idle->AlertHsPhase1	203	Covered	T1,T2,T3
Idle->PingHsPhase1	203	Covered	T1,T2,T3
Pause0->Idle	256	Covered	T39,T34,T36
Pause0->Pause1	242	Covered	T1,T2,T3
Pause1->Idle	246	Covered	T1,T2,T3
PingHsPhase1->Idle	256	Covered	T2,T3,T18
PingHsPhase1->PingHsPhase2	227	Covered	T1,T2,T3
PingHsPhase2->Idle	256	Covered	T1,T2,T12
PingHsPhase2->Pause0	237	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	172	2	2	100.00
TERNARY	178	2	2	100.00
TERNARY	167	2	2	100.00
CASE	199	14	13	92.86
IF	255	2	2	100.00
IF	276	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv' or '../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	172	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	(ping_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(alert_clr) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	199	case (state_q)
-2-:	202	if ((alert_trigger || ping_trigger))
-3-:	203	(alert_trigger) ? 
-4-:	210	if (ack_level)
-5-:	219	if ((!ack_level))
-6-:	226	if (ack_level)
-7-:	235	if ((!ack_level))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	1	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	0	-	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	1	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	0	-	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	1	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	0	-	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	1	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	0	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	255	if (sigint_detected)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	276	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	17	77.27
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	17	77.27

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertHs_A	156225	1115	0	0
AlertPKnownO_A	156225	119126	0	0
AlertState0_A	156225	119126	0	0
AlertTest1_A	156225	80	0	0
AlertTestHs_A	156225	80	0	0
gen_async_assert.DiffEncoding_A	82141	56152	0	0
gen_async_assert.InBandInitFsm_A	82141	126	0	160
gen_async_assert.InBandInitPing_A	82141	126	0	160
gen_async_assert.PingHs_A	82141	365	0	0
gen_async_assert.SigIntAck_A	82141	126	0	200
gen_async_assert.SigIntPing_A	82141	126	0	200
gen_fatal_assert.AlertState1_A	115429	6626	0	0
gen_fatal_assert.AlertState2_A	115429	46651	0	0
gen_fatal_assert.AlertState3_A	115429	4293	0	0
gen_recov_assert.AlertState1_A	40796	6556	0	0
gen_recov_assert.AlertState2_A	40796	0	0	0
gen_sync_assert.DiffEncoding_A	74084	51646	0	0
gen_sync_assert.InBandInitFsm_A	74084	0	0	0
gen_sync_assert.InBandInitPing_A	74084	0	0	0
gen_sync_assert.PingHs_A	74084	372	0	0
gen_sync_assert.SigIntAck_A	74084	0	0	0
gen_sync_assert.SigIntPing_A	74084	0	0	0

AlertHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	1115	0	0
T1	1070	14	0	0
T2	1047	14	0	0
T3	1109	17	0	0
T7	1130	17	0	0
T12	1204	14	0	0
T13	1235	18	0	0
T18	1110	16	0	0
T19	1144	17	0	0
T20	1129	17	0	0
T21	1042	14	0	0

AlertPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	119126	0	0
T1	1070	985	0	0
T2	1047	988	0	0
T3	1109	1045	0	0
T7	1130	1073	0	0
T12	1204	1016	0	0
T13	1235	1098	0	0
T18	1110	1030	0	0
T19	1144	1070	0	0
T20	1129	1058	0	0
T21	1042	963	0	0

AlertState0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	119126	0	0
T1	1070	985	0	0
T2	1047	988	0	0
T3	1109	1045	0	0
T7	1130	1073	0	0
T12	1204	1016	0	0
T13	1235	1098	0	0
T18	1110	1030	0	0
T19	1144	1070	0	0
T20	1129	1058	0	0
T21	1042	963	0	0

AlertTest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	80	0	0
T1	1070	1	0	0
T2	1047	1	0	0
T3	1109	1	0	0
T7	1130	1	0	0
T12	1204	1	0	0
T13	1235	1	0	0
T18	1110	1	0	0
T19	1144	1	0	0
T20	1129	1	0	0
T21	1042	1	0	0

AlertTestHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156225	80	0	0
T1	1070	1	0	0
T2	1047	1	0	0
T3	1109	1	0	0
T7	1130	1	0	0
T12	1204	1	0	0
T13	1235	1	0	0
T18	1110	1	0	0
T19	1144	1	0	0
T20	1129	1	0	0
T21	1042	1	0	0

gen_async_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	56152	0	0
T1	1070	887	0	0
T2	1047	872	0	0
T3	1109	919	0	0
T7	1130	964	0	0
T12	1204	900	0	0
T13	1235	901	0	0
T18	1110	907	0	0
T19	1144	953	0	0
T20	1129	914	0	0
T21	1042	876	0	0

gen_async_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	126	0	160
T1	1070	3	0	4
T2	1047	3	0	4
T3	1109	4	0	4
T7	1130	3	0	4
T12	1204	3	0	4
T13	1235	2	0	4
T18	1110	3	0	4
T19	1144	4	0	4
T20	1129	4	0	4
T21	1042	4	0	4

gen_async_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	126	0	160
T1	1070	3	0	4
T2	1047	3	0	4
T3	1109	4	0	4
T7	1130	3	0	4
T12	1204	3	0	4
T13	1235	2	0	4
T18	1110	3	0	4
T19	1144	4	0	4
T20	1129	4	0	4
T21	1042	4	0	4

gen_async_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	365	0	0
T1	1070	9	0	0
T2	1047	9	0	0
T3	1109	11	0	0
T7	1130	10	0	0
T12	1204	10	0	0
T13	1235	6	0	0
T18	1110	10	0	0
T19	1144	11	0	0
T20	1129	9	0	0
T21	1042	9	0	0

gen_async_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	126	0	200
T1	1070	3	0	5
T2	1047	3	0	5
T3	1109	4	0	5
T7	1130	3	0	5
T12	1204	3	0	5
T13	1235	2	0	5
T18	1110	3	0	5
T19	1144	4	0	5
T20	1129	4	0	5
T21	1042	4	0	5

gen_async_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82141	126	0	200
T1	1070	3	0	5
T2	1047	3	0	5
T3	1109	4	0	5
T7	1130	3	0	5
T12	1204	3	0	5
T13	1235	2	0	5
T18	1110	3	0	5
T19	1144	4	0	5
T20	1129	4	0	5
T21	1042	4	0	5

gen_fatal_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115429	6626	0	0
T4	2860	243	0	0
T5	3049	195	0	0
T15	3055	303	0	0
T17	3053	266	0	0
T40	2842	276	0	0
T41	2805	228	0	0
T42	2977	225	0	0
T43	2852	265	0	0
T44	3036	227	0	0
T45	2955	279	0	0

gen_fatal_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115429	46651	0	0
T4	2860	1254	0	0
T5	3049	1423	0	0
T15	3055	1268	0	0
T17	3053	1284	0	0
T40	2842	1202	0	0
T41	2805	1185	0	0
T42	2977	1210	0	0
T43	2852	1166	0	0
T44	3036	1278	0	0
T45	2955	1112	0	0

gen_fatal_assert.AlertState3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115429	4293	0	0
T4	2860	64	0	0
T5	3049	77	0	0
T15	3055	61	0	0
T17	3053	64	0	0
T40	2842	59	0	0
T41	2805	61	0	0
T42	2977	62	0	0
T43	2852	58	0	0
T44	3036	66	0	0
T45	2955	54	0	0

gen_recov_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40796	6556	0	0
T1	1070	205	0	0
T2	1047	217	0	0
T3	1109	271	0	0
T7	1130	276	0	0
T12	1204	209	0	0
T13	1235	276	0	0
T18	1110	263	0	0
T19	1144	266	0	0
T20	1129	268	0	0
T21	1042	215	0	0

gen_recov_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40796	0	0	0

gen_sync_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	51646	0	0
T25	840	736	0	0
T26	887	742	0	0
T27	804	705	0	0
T28	1030	821	0	0
T29	871	740	0	0
T34	885	763	0	0
T35	941	737	0	0
T36	936	764	0	0
T37	952	800	0	0
T38	823	697	0	0

gen_sync_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	0	0	0

gen_sync_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	0	0	0

gen_sync_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	372	0	0
T25	840	9	0	0
T26	887	8	0	0
T27	804	9	0	0
T28	1030	9	0	0
T29	871	9	0	0
T34	885	10	0	0
T35	941	10	0	0
T36	936	10	0	0
T37	952	10	0	0
T38	823	9	0	0

gen_sync_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	0	0	0

gen_sync_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74084	0	0	0