Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/prim_alert-sim-vcs/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_alert_tb.i_alert_sender	95.52	100.00	100.00	100.00	100.00	95.83	77.27

---

Module Instance : prim_alert_tb.i_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.52	100.00	100.00	100.00	100.00	95.83	77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_alert_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
TOTAL		53	53	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	193	32	32	100.00
ALWAYS	276	9	9	100.00

140                     
141        1/1            assign sigint_detected = ack_sigint | ping_sigint;
           Tests:       T1 T2 T3 
142                     
143                     
144                       // diff pair output
145        1/1            assign alert_tx_o.alert_p = alert_pq;
           Tests:       T1 T2 T3 
146        1/1            assign alert_tx_o.alert_n = alert_nq;
           Tests:       T1 T2 T3 
147                     
148                       // alert and ping set regs
149                       logic alert_set_d, alert_set_q, alert_clr;
150                       logic alert_test_set_d, alert_test_set_q;
151                       logic ping_set_d, ping_set_q, ping_clr;
152                       logic alert_req_trigger, alert_test_trigger, ping_trigger;
153                     
154                       // if handshake is ongoing, capture additional alert requests.
155                       logic alert_req;
156                       prim_sec_anchor_buf #(
157                         .Width(1)
158                       ) u_prim_buf_in_req (
159                         .in_i(alert_req_i),
160                         .out_o(alert_req)
161                       );
162                     
163        1/1            assign alert_req_trigger = alert_req | alert_set_q;
           Tests:       T1 T2 T3 
164                       if (IsFatal) begin : gen_fatal
165                         assign alert_set_d = alert_req_trigger;
166                       end else begin : gen_recov
167        1/1              assign alert_set_d = (alert_clr) ? 1'b0 : alert_req_trigger;
           Tests:       T1 T2 T3 
168                       end
169                     
170                       // the alert test request is always cleared.
171        1/1            assign alert_test_trigger = alert_test_i | alert_test_set_q;
           Tests:       T1 T2 T3 
172        1/1            assign alert_test_set_d = (alert_clr) ? 1'b0 : alert_test_trigger;
           Tests:       T1 T2 T3 
173                     
174                       logic alert_trigger;
175        1/1            assign alert_trigger = alert_req_trigger | alert_test_trigger;
           Tests:       T1 T2 T3 
176                     
177        1/1            assign ping_trigger = ping_set_q | ping_event;
           Tests:       T1 T2 T3 
178        1/1            assign ping_set_d  = (ping_clr) ? 1'b0 : ping_trigger;
           Tests:       T1 T2 T3 
179                     
180                     
181                       // alert event acknowledge and state (not affected by alert_test_i)
182        1/1            assign alert_ack_o = alert_clr & alert_set_q;
           Tests:       T1 T2 T3 
183        1/1            assign alert_state_o = alert_set_q;
           Tests:       T1 T2 T3 
184                     
185                       // this FSM performs a full four phase handshake upon a ping or alert trigger.
186                       // note that the latency of the alert_p/n diff pair is at least one cycle
187                       // until it enters the receiver FSM. the same holds for the ack_* diff pair
188                       // input. in case a signal integrity issue is detected, the FSM bails out,
189                       // sets the alert_p/n diff pair to the same value and toggles it in order to
190                       // signal that condition over to the receiver.
191                       always_comb begin : p_fsm
192                         // default
193        1/1              state_d   = state_q;
           Tests:       T1 T2 T3 
194        1/1              alert_pd  = 1'b0;
           Tests:       T1 T2 T3 
195        1/1              alert_nd  = 1'b1;
           Tests:       T1 T2 T3 
196        1/1              ping_clr  = 1'b0;
           Tests:       T1 T2 T3 
197        1/1              alert_clr = 1'b0;
           Tests:       T1 T2 T3 
198                     
199        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
200                           Idle: begin
201                             // alert always takes precedence
202        1/1                  if (alert_trigger || ping_trigger) begin
           Tests:       T1 T2 T3 
203        1/1                    state_d = (alert_trigger) ? AlertHsPhase1 : PingHsPhase1;
           Tests:       T1 T2 T3 
204        1/1                    alert_pd = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                    alert_nd = 1'b0;
           Tests:       T1 T2 T3 
206                             end
                        MISSING_ELSE
207                           end
208                           // waiting for ack from receiver
209                           AlertHsPhase1: begin
210        1/1                  if (ack_level) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d  = AlertHsPhase2;
           Tests:       T1 T2 T3 
212                             end else begin
213        1/1                    alert_pd = 1'b1;
           Tests:       T1 T2 T3 
214        1/1                    alert_nd = 1'b0;
           Tests:       T1 T2 T3 
215                             end
216                           end
217                           // wait for deassertion of ack
218                           AlertHsPhase2: begin
219        1/1                  if (!ack_level) begin
           Tests:       T1 T2 T3 
220        1/1                    state_d = Pause0;
           Tests:       T1 T2 T3 
221        1/1                    alert_clr = 1'b1;
           Tests:       T1 T2 T3 
222                             end
                        MISSING_ELSE
223                           end
224                           // waiting for ack from receiver
225                           PingHsPhase1: begin
226        1/1                  if (ack_level) begin
           Tests:       T1 T2 T3 
227        1/1                    state_d  = PingHsPhase2;
           Tests:       T1 T2 T3 
228                             end else begin
229        1/1                    alert_pd = 1'b1;
           Tests:       T1 T2 T3 
230        1/1                    alert_nd = 1'b0;
           Tests:       T1 T2 T3 
231                             end
232                           end
233                           // wait for deassertion of ack
234                           PingHsPhase2: begin
235        1/1                  if (!ack_level) begin
           Tests:       T1 T2 T3 
236        1/1                    ping_clr = 1'b1;
           Tests:       T1 T2 T3 
237        1/1                    state_d = Pause0;
           Tests:       T1 T2 T3 
238                             end
                        MISSING_ELSE
239                           end
240                           // pause cycles between back-to-back handshakes
241                           Pause0: begin
242        1/1                  state_d = Pause1;
           Tests:       T1 T2 T3 
243                           end
244                           // clear and ack alert request if it was set
245                           Pause1: begin
246        1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
247                           end
248                           // catch parasitic states
249                           default : state_d = Idle;
250                         endcase
251                     
252                         // we have a signal integrity issue at one of the incoming diff pairs. this condition is
253                         // signalled by setting the output diffpair to zero. If the sigint has disappeared, we clear
254                         // the ping request state of this sender and go back to idle.
255        1/1              if (sigint_detected) begin
           Tests:       T1 T2 T3 
256        1/1                state_d   = Idle;
           Tests:       T1 T2 T3 
257        1/1                alert_pd  = 1'b0;
           Tests:       T1 T2 T3 
258        1/1                alert_nd  = 1'b0;
           Tests:       T1 T2 T3 
259        1/1                ping_clr  = 1'b1;
           Tests:       T1 T2 T3 
260        1/1                alert_clr = 1'b0;
           Tests:       T1 T2 T3 
261                         end
                        MISSING_ELSE
262                       end
263                     
264                       // This prevents further tool optimizations of the differential signal.
265                       prim_sec_anchor_flop #(
266                         .Width     (2),
267                         .ResetValue(2'b10)
268                       ) u_prim_flop_alert (
269                         .clk_i,
270                         .rst_ni,
271                         .d_i({alert_nd, alert_pd}),
272                         .q_o({alert_nq, alert_pq})
273                       );
274                     
275                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg
276        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
277        1/1                state_q          <= Idle;
           Tests:       T1 T2 T3 
278        1/1                alert_set_q      <= 1'b0;
           Tests:       T1 T2 T3 
279        1/1                alert_test_set_q <= 1'b0;
           Tests:       T1 T2 T3 
280        1/1                ping_set_q       <= 1'b0;
           Tests:       T1 T2 T3 
281                         end else begin
282        1/1                state_q          <= state_d;
           Tests:       T1 T2 T3 
283        1/1                alert_set_q      <= alert_set_d;
           Tests:       T1 T2 T3 
284        1/1                alert_test_set_q <= alert_test_set_d;
           Tests:       T1 T2 T3 
285        1/1                ping_set_q       <= ping_set_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (ack_sigint | ping_sigint)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       163
 EXPRESSION (alert_req | alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (alert_clr ? 1'b0 : alert_req_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (alert_test_i | alert_test_set_q)
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (alert_clr ? 1'b0 : alert_test_trigger)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (alert_req_trigger | alert_test_trigger)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       177
 EXPRESSION (ping_set_q | ping_event)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       178
 EXPRESSION (ping_clr ? 1'b0 : ping_trigger)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       182
 EXPRESSION (alert_clr & alert_set_q)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       202
 EXPRESSION (alert_trigger || ping_trigger)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (alert_trigger ? AlertHsPhase1 : PingHsPhase1)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T9	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_ack_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ping_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_alert_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertHsPhase1	203	Covered	T1,T2,T3
AlertHsPhase2	211	Covered	T1,T2,T3
Idle	246	Covered	T1,T2,T3
Pause0	220	Covered	T1,T2,T3
Pause1	242	Covered	T1,T2,T3
PingHsPhase1	203	Covered	T1,T2,T3
PingHsPhase2	227	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertHsPhase1->AlertHsPhase2	211	Covered	T1,T2,T3
AlertHsPhase1->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Idle	256	Covered	T1,T2,T3
AlertHsPhase2->Pause0	220	Covered	T1,T2,T3
Idle->AlertHsPhase1	203	Covered	T1,T2,T3
Idle->PingHsPhase1	203	Covered	T1,T2,T3
Pause0->Idle	256	Covered	T28,T37,T32
Pause0->Pause1	242	Covered	T1,T2,T3
Pause1->Idle	246	Covered	T1,T2,T3
PingHsPhase1->Idle	256	Covered	T1,T2,T3
PingHsPhase1->PingHsPhase2	227	Covered	T1,T2,T3
PingHsPhase2->Idle	256	Covered	T1,T3,T7
PingHsPhase2->Pause0	237	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_alert_sender

	Line No.	Total	Covered	Percent
Branches		24	23	95.83
TERNARY	172	2	2	100.00
TERNARY	178	2	2	100.00
TERNARY	167	2	2	100.00
CASE	199	14	13	92.86
IF	255	2	2	100.00
IF	276	2	2	100.00

172          assign alert_test_set_d = (alert_clr) ? 1'b0 : alert_test_trigger;
                                                   -1-  
                                                   ==>  
                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

178          assign ping_set_d  = (ping_clr) ? 1'b0 : ping_trigger;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

167            assign alert_set_d = (alert_clr) ? 1'b0 : alert_req_trigger;
                                                -1-  
                                                ==>  
                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

199            unique case (state_q)
                      -1-  
200              Idle: begin
201                // alert always takes precedence
202                if (alert_trigger || ping_trigger) begin
                   -2-  
203                  state_d = (alert_trigger) ? AlertHsPhase1 : PingHsPhase1;
                                               -3-  
                                               ==>  
                                               ==>  
204                  alert_pd = 1'b1;
205                  alert_nd = 1'b0;
206                end
                   MISSING_ELSE
                   ==>
207              end
208              // waiting for ack from receiver
209              AlertHsPhase1: begin
210                if (ack_level) begin
                   -4-  
211                  state_d  = AlertHsPhase2;
                     ==>
212                end else begin
213                  alert_pd = 1'b1;
                     ==>
214                  alert_nd = 1'b0;
215                end
216              end
217              // wait for deassertion of ack
218              AlertHsPhase2: begin
219                if (!ack_level) begin
                   -5-  
220                  state_d = Pause0;
                     ==>
221                  alert_clr = 1'b1;
222                end
                   MISSING_ELSE
                   ==>
223              end
224              // waiting for ack from receiver
225              PingHsPhase1: begin
226                if (ack_level) begin
                   -6-  
227                  state_d  = PingHsPhase2;
                     ==>
228                end else begin
229                  alert_pd = 1'b1;
                     ==>
230                  alert_nd = 1'b0;
231                end
232              end
233              // wait for deassertion of ack
234              PingHsPhase2: begin
235                if (!ack_level) begin
                   -7-  
236                  ping_clr = 1'b1;
                     ==>
237                  state_d = Pause0;
238                end
                   MISSING_ELSE
                   ==>
239              end
240              // pause cycles between back-to-back handshakes
241              Pause0: begin
242                state_d = Pause1;
                   ==>
243              end
244              // clear and ack alert request if it was set
245              Pause1: begin
246                state_d = Idle;
                   ==>
247              end
248              // catch parasitic states
249              default : state_d = Idle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	1	-	-	-	-	Covered	T1,T2,T3
Idle	1	0	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	1	-	-	-	Covered	T1,T2,T3
AlertHsPhase1	-	-	0	-	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	1	-	-	Covered	T1,T2,T3
AlertHsPhase2	-	-	-	0	-	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	1	-	Covered	T1,T2,T3
PingHsPhase1	-	-	-	-	0	-	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	1	Covered	T1,T2,T3
PingHsPhase2	-	-	-	-	-	0	Covered	T1,T2,T3
Pause0	-	-	-	-	-	-	Covered	T1,T2,T3
Pause1	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

255            if (sigint_detected) begin
               -1-  
256              state_d   = Idle;
                 ==>
257              alert_pd  = 1'b0;
258              alert_nd  = 1'b0;
259              ping_clr  = 1'b1;
260              alert_clr = 1'b0;
261            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

276            if (!rst_ni) begin
               -1-  
277              state_q          <= Idle;
                 ==>
278              alert_set_q      <= 1'b0;
279              alert_test_set_q <= 1'b0;
280              ping_set_q       <= 1'b0;
281            end else begin
282              state_q          <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_alert_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	17	77.27
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	17	77.27

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertHs_A	152694	1085	0	0
AlertPKnownO_A	152694	116533	0	0
AlertState0_A	152694	116533	0	0
AlertTest1_A	152694	79	0	0
AlertTestHs_A	152694	79	0	0
gen_async_assert.DiffEncoding_A	79229	54518	0	3
gen_async_assert.InBandInitFsm_A	79229	107	0	152
gen_async_assert.InBandInitPing_A	79229	107	0	152
gen_async_assert.PingHs_A	79229	368	0	1
gen_async_assert.SigIntAck_A	79229	107	0	191
gen_async_assert.SigIntPing_A	79229	107	0	191
gen_fatal_assert.AlertState1_A	111400	6156	0	0
gen_fatal_assert.AlertState2_A	111400	45440	0	0
gen_fatal_assert.AlertState3_A	111400	4241	0	0
gen_recov_assert.AlertState1_A	41294	6388	0	0
gen_recov_assert.AlertState2_A	41294	0	0	0
gen_sync_assert.DiffEncoding_A	73465	51279	0	0
gen_sync_assert.InBandInitFsm_A	73465	0	0	0
gen_sync_assert.InBandInitPing_A	73465	0	0	0
gen_sync_assert.PingHs_A	73465	361	0	0
gen_sync_assert.SigIntAck_A	73465	0	0	0
gen_sync_assert.SigIntPing_A	73465	0	0	0

AlertHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152694	1085	0	0
T1	1265	14	0	0
T2	1046	13	0	0
T3	1168	15	0	0
T7	1067	14	0	0
T8	1075	14	0	0
T9	1193	17	0	0
T16	1177	17	0	0
T17	1149	15	0	0
T18	1104	16	0	0
T19	1127	16	0	0

AlertPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152694	116533	0	0
T1	1265	1099	0	0
T2	1046	978	0	0
T3	1168	1047	0	0
T7	1067	978	0	0
T8	1075	993	0	0
T9	1193	1039	0	0
T16	1177	1114	0	0
T17	1149	1071	0	0
T18	1104	1021	0	0
T19	1127	1031	0	0

AlertState0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152694	116533	0	0
T1	1265	1099	0	0
T2	1046	978	0	0
T3	1168	1047	0	0
T7	1067	978	0	0
T8	1075	993	0	0
T9	1193	1039	0	0
T16	1177	1114	0	0
T17	1149	1071	0	0
T18	1104	1021	0	0
T19	1127	1031	0	0

AlertTest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152694	79	0	0
T1	1265	1	0	0
T2	1046	1	0	0
T3	1168	1	0	0
T7	1067	1	0	0
T8	1075	1	0	0
T9	1193	1	0	0
T16	1177	1	0	0
T17	1149	1	0	0
T18	1104	1	0	0
T19	1127	1	0	0

AlertTestHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152694	79	0	0
T1	1265	1	0	0
T2	1046	1	0	0
T3	1168	1	0	0
T7	1067	1	0	0
T8	1075	1	0	0
T9	1193	1	0	0
T16	1177	1	0	0
T17	1149	1	0	0
T18	1104	1	0	0
T19	1127	1	0	0

gen_async_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79229	54518	0	3
T1	1265	950	0	0
T2	1046	897	0	0
T3	1168	904	0	0
T7	1067	875	0	0
T8	1075	866	0	0
T9	1193	905	0	0
T16	1177	957	0	0
T17	1149	933	0	0
T18	1104	919	0	0
T19	1127	917	0	0
T41	0	0	0	3

gen_async_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79229	107	0	152
T1	1265	3	0	4
T2	1046	3	0	4
T3	1168	4	0	4
T7	1067	3	0	4
T8	1075	3	0	4
T9	1193	3	0	4
T16	1177	3	0	4
T17	1149	3	0	4
T18	1104	3	0	4
T19	1127	3	0	4

gen_async_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79229	107	0	152
T1	1265	3	0	4
T2	1046	3	0	4
T3	1168	4	0	4
T7	1067	3	0	4
T8	1075	3	0	4
T9	1193	3	0	4
T16	1177	3	0	4
T17	1149	3	0	4
T18	1104	3	0	4
T19	1127	3	0	4

gen_async_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79229	368	0	1
T1	1265	9	0	0
T2	1046	10	0	0
T3	1168	9	0	0
T7	1067	9	0	0
T8	1075	7	0	0
T9	1193	9	0	0
T16	1177	9	0	0
T17	1149	10	0	0
T18	1104	10	0	0
T19	1127	10	0	0
T41	0	0	0	1

gen_async_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79229	107	0	191
T1	1265	3	0	5
T2	1046	3	0	5
T3	1168	4	0	5
T7	1067	3	0	5
T8	1075	3	0	5
T9	1193	3	0	5
T16	1177	3	0	5
T17	1149	3	0	5
T18	1104	3	0	5
T19	1127	3	0	5

gen_async_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79229	107	0	191
T1	1265	3	0	5
T2	1046	3	0	5
T3	1168	4	0	5
T7	1067	3	0	5
T8	1075	3	0	5
T9	1193	3	0	5
T16	1177	3	0	5
T17	1149	3	0	5
T18	1104	3	0	5
T19	1127	3	0	5

gen_fatal_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111400	6156	0	0
T11	3061	198	0	0
T15	2956	199	0	0
T21	3011	282	0	0
T22	2812	198	0	0
T23	2794	254	0	0
T24	3139	284	0	0
T42	2898	199	0	0
T43	3080	272	0	0
T44	2870	258	0	0
T45	2818	172	0	0

gen_fatal_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111400	45440	0	0
T11	3061	1302	0	0
T15	2956	1266	0	0
T21	3011	1271	0	0
T22	2812	1152	0	0
T23	2794	1077	0	0
T24	3139	1389	0	0
T42	2898	1189	0	0
T43	3080	1351	0	0
T44	2870	1160	0	0
T45	2818	1211	0	0

gen_fatal_assert.AlertState3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111400	4241	0	0
T11	3061	69	0	0
T15	2956	66	0	0
T21	3011	63	0	0
T22	2812	61	0	0
T23	2794	53	0	0
T24	3139	69	0	0
T42	2898	62	0	0
T43	3080	67	0	0
T44	2870	58	0	0
T45	2818	66	0	0

gen_recov_assert.AlertState1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41294	6388	0	0
T1	1265	226	0	0
T2	1046	210	0	0
T3	1168	244	0	0
T7	1067	206	0	0
T8	1075	216	0	0
T9	1193	243	0	0
T16	1177	278	0	0
T17	1149	274	0	0
T18	1104	245	0	0
T19	1127	237	0	0

gen_recov_assert.AlertState2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41294	0	0	0

gen_sync_assert.DiffEncoding_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73465	51279	0	0
T27	933	764	0	0
T28	940	746	0	0
T29	974	736	0	0
T30	880	744	0	0
T31	1021	794	0	0
T32	937	780	0	0
T37	998	822	0	0
T38	1015	799	0	0
T39	921	783	0	0
T40	989	741	0	0

gen_sync_assert.InBandInitFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73465	0	0	0

gen_sync_assert.InBandInitPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73465	0	0	0

gen_sync_assert.PingHs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73465	361	0	0
T27	933	9	0	0
T28	940	8	0	0
T29	974	8	0	0
T30	880	8	0	0
T31	1021	9	0	0
T32	937	9	0	0
T37	998	10	0	0
T38	1015	10	0	0
T39	921	9	0	0
T40	989	10	0	0

gen_sync_assert.SigIntAck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73465	0	0	0

gen_sync_assert.SigIntPing_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73465	0	0	0