Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.12	100.00	86.67	100.00	90.91	93.33	81.82

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_esc_tb.i_esc_receiver	92.12	100.00	86.67	100.00	90.91	93.33	81.82

---

Module Instance : prim_esc_tb.i_esc_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.12	100.00	86.67	100.00	90.91	93.33	81.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.12	100.00	86.67	100.00	90.91	93.33	81.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_esc_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	158	39	39	100.00
ALWAYS	238	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
99	1	1
100	1	1
153	1	1
154	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
164	1	1
167	1	1
168	1	1
169	1	1
170	1	1
			MISSING_ELSE
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
			MISSING_ELSE
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
			MISSING_ELSE
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
225	1	1
226	1	1
227	1	1
228	1	1
			MISSING_ELSE
238	1	1
239	1	1
241	1	1

---

Cond Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (ping_en && ((!(&timeout_cnt))))
             ---1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION ((timeout_cnt > '0) && ((!(&timeout_cnt))))
             ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION (esc_req || ((&timeout_cnt)) || timeout_cnt_error)
             ---1---    --------2-------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       225
 EXPRESSION (sigint_detected && (state_q != SigInt))
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       225
 SUB-EXPRESSION (state_q != SigInt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_esc_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Check	168	Covered	T1,T2,T3
EscResp	180	Covered	T1,T2,T3
Idle	187	Covered	T1,T2,T3
PingResp	176	Covered	T1,T2,T3
SigInt	216	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Check->EscResp	180	Covered	T1,T2,T3
Check->PingResp	176	Covered	T1,T2,T3
Check->SigInt	226	Covered	T1,T4,T16
EscResp->Idle	199	Covered	T1,T2,T3
EscResp->SigInt	226	Covered	T2,T3,T5
Idle->Check	168	Covered	T1,T2,T3
Idle->SigInt	226	Covered	T1,T2,T3
PingResp->EscResp	192	Covered	T10,T11,T12
PingResp->Idle	187	Covered	T1,T2,T3
PingResp->SigInt	226	Not Covered
SigInt->Idle	213	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
Branches		15	14	93.33
CASE	164	11	10	90.91
IF	225	2	2	100.00
IF	238	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	164	case (state_q)
-2-:	167	if (esc_level)
-3-:	179	if (esc_level)
-4-:	191	if (esc_level)
-5-:	200	if (esc_level)
-6-:	215	if (sigint_detected)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
Idle	1	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	Covered	T1,T2,T3
Check	-	1	-	-	-	Covered	T1,T2,T3
Check	-	0	-	-	-	Covered	T1,T2,T3
PingResp	-	-	1	-	-	Covered	T10,T11,T12
PingResp	-	-	0	-	-	Covered	T1,T2,T3
EscResp	-	-	-	1	-	Covered	T1,T2,T3
EscResp	-	-	-	0	-	Covered	T1,T2,T3
SigInt	-	-	-	-	1	Covered	T1,T2,T3
SigInt	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	225	if ((sigint_detected && (state_q != SigInt)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	238	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_esc_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	9	81.82
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	9	81.82

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DiffEncCheck_A	9801	5135	0	0
EscCntEsc_A	9801	0	0	0
EscCntWrap_A	9801	0	0	0
EscEnCheck_A	9801	304	0	0
EscEnKnownO_A	9801	5235	0	0
EscRespCheck_A	9801	304	0	20
PingRespCheck_A	9801	53	0	20
RespPKnownO_A	9801	5235	0	0
SigIntCheck0_A	9801	40	0	0
SigIntCheck1_A	9801	40	0	0
SigIntCheck2_A	9801	40	0	0

DiffEncCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	5135	0	0
T1	499	244	0	0
T2	503	251	0	0
T3	535	283	0	0
T4	495	291	0	0
T5	483	256	0	0
T6	460	271	0	0
T7	475	218	0	0
T10	466	256	0	0
T13	467	246	0	0
T16	505	232	0	0

EscCntEsc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	0	0	0

EscCntWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	0	0	0

EscEnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	304	0	0
T1	499	7	0	0
T2	503	4	0	0
T3	535	25	0	0
T4	495	15	0	0
T5	483	14	0	0
T6	460	10	0	0
T7	475	9	0	0
T10	466	19	0	0
T13	467	21	0	0
T16	505	13	0	0

EscEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	5235	0	0
T1	499	249	0	0
T2	503	256	0	0
T3	535	288	0	0
T4	495	296	0	0
T5	483	261	0	0
T6	460	276	0	0
T7	475	223	0	0
T10	466	261	0	0
T13	467	251	0	0
T16	505	237	0	0

EscRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	304	0	20
T1	499	7	0	1
T2	503	4	0	1
T3	535	25	0	1
T4	495	15	0	1
T5	483	14	0	1
T6	460	10	0	1
T7	475	9	0	1
T10	466	19	0	1
T13	467	21	0	1
T16	505	13	0	1

PingRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	53	0	20
T1	499	3	0	1
T2	503	2	0	1
T3	535	3	0	1
T4	495	3	0	1
T5	483	2	0	1
T6	460	3	0	1
T7	475	2	0	1
T10	466	3	0	1
T13	467	2	0	1
T16	505	3	0	1

RespPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	5235	0	0
T1	499	249	0	0
T2	503	256	0	0
T3	535	288	0	0
T4	495	296	0	0
T5	483	261	0	0
T6	460	276	0	0
T7	475	223	0	0
T10	466	261	0	0
T13	467	251	0	0
T16	505	237	0	0

SigIntCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	40	0	0
T1	499	2	0	0
T2	503	2	0	0
T3	535	2	0	0
T4	495	2	0	0
T5	483	2	0	0
T6	460	2	0	0
T7	475	2	0	0
T10	466	2	0	0
T13	467	2	0	0
T16	505	2	0	0

SigIntCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	40	0	0
T1	499	2	0	0
T2	503	2	0	0
T3	535	2	0	0
T4	495	2	0	0
T5	483	2	0	0
T6	460	2	0	0
T7	475	2	0	0
T10	466	2	0	0
T13	467	2	0	0
T16	505	2	0	0

SigIntCheck2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9801	40	0	0
T1	499	2	0	0
T2	503	2	0	0
T3	535	2	0	0
T4	495	2	0	0
T5	483	2	0	0
T6	460	2	0	0
T7	475	2	0	0
T10	466	2	0	0
T13	467	2	0	0
T16	505	2	0	0