| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.70 | 86.70 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/5.prim_esc_test.209037104 |
| 88.44 | 1.74 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/18.prim_esc_test.1270212196 |
| 89.58 | 1.14 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.956930904 |
| 90.72 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.2546336198 |
| 91.31 | 0.60 | 95.24 | 0.00 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2573967032 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.3113631723 |
| /workspace/coverage/default/10.prim_esc_test.2030340809 |
| /workspace/coverage/default/11.prim_esc_test.780719599 |
| /workspace/coverage/default/14.prim_esc_test.946286539 |
| /workspace/coverage/default/15.prim_esc_test.850127804 |
| /workspace/coverage/default/16.prim_esc_test.3980242334 |
| /workspace/coverage/default/17.prim_esc_test.2236087025 |
| /workspace/coverage/default/19.prim_esc_test.2545551078 |
| /workspace/coverage/default/2.prim_esc_test.3124333763 |
| /workspace/coverage/default/3.prim_esc_test.2908426052 |
| /workspace/coverage/default/4.prim_esc_test.4134023826 |
| /workspace/coverage/default/6.prim_esc_test.1977035388 |
| /workspace/coverage/default/7.prim_esc_test.2315111287 |
| /workspace/coverage/default/8.prim_esc_test.1287337650 |
| /workspace/coverage/default/9.prim_esc_test.45716109 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/16.prim_esc_test.3980242334 | Feb 07 12:21:19 PM PST 24 | Feb 07 12:21:20 PM PST 24 | 4733674 ps | ||
| T2 | /workspace/coverage/default/5.prim_esc_test.209037104 | Feb 07 12:24:03 PM PST 24 | Feb 07 12:24:05 PM PST 24 | 5562482 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.2030340809 | Feb 07 12:25:27 PM PST 24 | Feb 07 12:25:29 PM PST 24 | 5064626 ps | ||
| T4 | /workspace/coverage/default/0.prim_esc_test.2573967032 | Feb 07 12:24:00 PM PST 24 | Feb 07 12:24:02 PM PST 24 | 4819254 ps | ||
| T5 | /workspace/coverage/default/2.prim_esc_test.3124333763 | Feb 07 12:24:22 PM PST 24 | Feb 07 12:24:23 PM PST 24 | 4899976 ps | ||
| T12 | /workspace/coverage/default/13.prim_esc_test.2546336198 | Feb 07 12:21:13 PM PST 24 | Feb 07 12:21:14 PM PST 24 | 5048317 ps | ||
| T6 | /workspace/coverage/default/14.prim_esc_test.946286539 | Feb 07 12:24:03 PM PST 24 | Feb 07 12:24:05 PM PST 24 | 4258628 ps | ||
| T14 | /workspace/coverage/default/9.prim_esc_test.45716109 | Feb 07 12:20:24 PM PST 24 | Feb 07 12:20:25 PM PST 24 | 4486465 ps | ||
| T13 | /workspace/coverage/default/3.prim_esc_test.2908426052 | Feb 07 12:20:23 PM PST 24 | Feb 07 12:20:24 PM PST 24 | 4460237 ps | ||
| T11 | /workspace/coverage/default/12.prim_esc_test.956930904 | Feb 07 12:20:37 PM PST 24 | Feb 07 12:20:39 PM PST 24 | 4697681 ps | ||
| T7 | /workspace/coverage/default/6.prim_esc_test.1977035388 | Feb 07 12:21:40 PM PST 24 | Feb 07 12:21:41 PM PST 24 | 4980802 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.850127804 | Feb 07 12:20:37 PM PST 24 | Feb 07 12:20:39 PM PST 24 | 5008493 ps | ||
| T16 | /workspace/coverage/default/8.prim_esc_test.1287337650 | Feb 07 12:23:22 PM PST 24 | Feb 07 12:23:23 PM PST 24 | 5148146 ps | ||
| T8 | /workspace/coverage/default/18.prim_esc_test.1270212196 | Feb 07 12:24:03 PM PST 24 | Feb 07 12:24:05 PM PST 24 | 4980435 ps | ||
| T9 | /workspace/coverage/default/19.prim_esc_test.2545551078 | Feb 07 12:21:50 PM PST 24 | Feb 07 12:21:51 PM PST 24 | 4708953 ps | ||
| T10 | /workspace/coverage/default/4.prim_esc_test.4134023826 | Feb 07 12:21:38 PM PST 24 | Feb 07 12:21:39 PM PST 24 | 4534428 ps | ||
| T17 | /workspace/coverage/default/11.prim_esc_test.780719599 | Feb 07 12:24:17 PM PST 24 | Feb 07 12:24:17 PM PST 24 | 5564938 ps | ||
| T18 | /workspace/coverage/default/7.prim_esc_test.2315111287 | Feb 07 12:25:21 PM PST 24 | Feb 07 12:25:25 PM PST 24 | 5116930 ps | ||
| T19 | /workspace/coverage/default/1.prim_esc_test.3113631723 | Feb 07 12:25:41 PM PST 24 | Feb 07 12:25:42 PM PST 24 | 4666709 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.2236087025 | Feb 07 12:24:22 PM PST 24 | Feb 07 12:24:23 PM PST 24 | 5219722 ps |
| Test location | /workspace/coverage/default/5.prim_esc_test.209037104 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5562482 ps |
| CPU time | 0.4 seconds |
| Started | Feb 07 12:24:03 PM PST 24 |
| Finished | Feb 07 12:24:05 PM PST 24 |
| Peak memory | 145516 kb |
| Host | smart-a709a5e6-d94c-48a9-89db-e3c12972ee5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209037104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.209037104 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1270212196 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4980435 ps |
| CPU time | 0.39 seconds |
| Started | Feb 07 12:24:03 PM PST 24 |
| Finished | Feb 07 12:24:05 PM PST 24 |
| Peak memory | 145372 kb |
| Host | smart-b435326a-9fd4-4de8-bbcc-9aafdffce573 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1270212196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1270212196 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.956930904 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4697681 ps |
| CPU time | 0.43 seconds |
| Started | Feb 07 12:20:37 PM PST 24 |
| Finished | Feb 07 12:20:39 PM PST 24 |
| Peak memory | 146032 kb |
| Host | smart-46d2cf06-e1cd-4dc4-8b71-ebcb271006af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956930904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.956930904 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2546336198 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5048317 ps |
| CPU time | 0.39 seconds |
| Started | Feb 07 12:21:13 PM PST 24 |
| Finished | Feb 07 12:21:14 PM PST 24 |
| Peak memory | 146196 kb |
| Host | smart-f2dd4b58-0a3e-44ff-bf46-651190a52c4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546336198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2546336198 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2573967032 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4819254 ps |
| CPU time | 0.4 seconds |
| Started | Feb 07 12:24:00 PM PST 24 |
| Finished | Feb 07 12:24:02 PM PST 24 |
| Peak memory | 145860 kb |
| Host | smart-d8c95b1b-d7ad-46f1-a3ef-c9c098e16a9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573967032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2573967032 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3113631723 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4666709 ps |
| CPU time | 0.37 seconds |
| Started | Feb 07 12:25:41 PM PST 24 |
| Finished | Feb 07 12:25:42 PM PST 24 |
| Peak memory | 146116 kb |
| Host | smart-518926a1-13e8-4af9-90b8-12f7e5559cb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113631723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3113631723 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2030340809 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5064626 ps |
| CPU time | 0.38 seconds |
| Started | Feb 07 12:25:27 PM PST 24 |
| Finished | Feb 07 12:25:29 PM PST 24 |
| Peak memory | 145948 kb |
| Host | smart-0813794b-8689-40bb-8e27-345821122a54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030340809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2030340809 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.780719599 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5564938 ps |
| CPU time | 0.36 seconds |
| Started | Feb 07 12:24:17 PM PST 24 |
| Finished | Feb 07 12:24:17 PM PST 24 |
| Peak memory | 146068 kb |
| Host | smart-71bf79f8-d97a-478e-8424-f942258fe1e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780719599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.780719599 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.946286539 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4258628 ps |
| CPU time | 0.41 seconds |
| Started | Feb 07 12:24:03 PM PST 24 |
| Finished | Feb 07 12:24:05 PM PST 24 |
| Peak memory | 145380 kb |
| Host | smart-0f78efc6-8802-4c11-8ba4-ca67864650fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946286539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.946286539 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.850127804 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5008493 ps |
| CPU time | 0.43 seconds |
| Started | Feb 07 12:20:37 PM PST 24 |
| Finished | Feb 07 12:20:39 PM PST 24 |
| Peak memory | 145996 kb |
| Host | smart-62c72777-254d-4c61-a564-4dbc78666071 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850127804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.850127804 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3980242334 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4733674 ps |
| CPU time | 0.42 seconds |
| Started | Feb 07 12:21:19 PM PST 24 |
| Finished | Feb 07 12:21:20 PM PST 24 |
| Peak memory | 146292 kb |
| Host | smart-26c3f24a-aa68-4846-b31b-5aabaf0ee1e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980242334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3980242334 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2236087025 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5219722 ps |
| CPU time | 0.4 seconds |
| Started | Feb 07 12:24:22 PM PST 24 |
| Finished | Feb 07 12:24:23 PM PST 24 |
| Peak memory | 146060 kb |
| Host | smart-c659fec0-484f-4894-a9aa-19a2aaed4050 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236087025 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2236087025 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2545551078 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4708953 ps |
| CPU time | 0.39 seconds |
| Started | Feb 07 12:21:50 PM PST 24 |
| Finished | Feb 07 12:21:51 PM PST 24 |
| Peak memory | 146024 kb |
| Host | smart-c3e39f2e-af14-43ef-93b2-f31638d21e96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545551078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2545551078 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3124333763 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4899976 ps |
| CPU time | 0.37 seconds |
| Started | Feb 07 12:24:22 PM PST 24 |
| Finished | Feb 07 12:24:23 PM PST 24 |
| Peak memory | 146060 kb |
| Host | smart-67eec596-a6c6-4ecc-9dc9-f17cbf92fa5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124333763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3124333763 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2908426052 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4460237 ps |
| CPU time | 0.44 seconds |
| Started | Feb 07 12:20:23 PM PST 24 |
| Finished | Feb 07 12:20:24 PM PST 24 |
| Peak memory | 145616 kb |
| Host | smart-1941296f-f725-48a4-be45-4c2bd3ae3c8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908426052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2908426052 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.4134023826 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4534428 ps |
| CPU time | 0.4 seconds |
| Started | Feb 07 12:21:38 PM PST 24 |
| Finished | Feb 07 12:21:39 PM PST 24 |
| Peak memory | 146292 kb |
| Host | smart-d697b7fb-64ee-495e-a105-7bf44abe2bb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134023826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.4134023826 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1977035388 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4980802 ps |
| CPU time | 0.4 seconds |
| Started | Feb 07 12:21:40 PM PST 24 |
| Finished | Feb 07 12:21:41 PM PST 24 |
| Peak memory | 146276 kb |
| Host | smart-1a96d2a7-77e1-4f67-9144-23c4bace361b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1977035388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1977035388 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2315111287 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5116930 ps |
| CPU time | 0.42 seconds |
| Started | Feb 07 12:25:21 PM PST 24 |
| Finished | Feb 07 12:25:25 PM PST 24 |
| Peak memory | 145644 kb |
| Host | smart-7e80dd06-eb2c-439d-818f-aceb15e059a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315111287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2315111287 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1287337650 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5148146 ps |
| CPU time | 0.38 seconds |
| Started | Feb 07 12:23:22 PM PST 24 |
| Finished | Feb 07 12:23:23 PM PST 24 |
| Peak memory | 145992 kb |
| Host | smart-87bccafa-e3bd-44ef-b825-eb20760da7d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287337650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1287337650 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.45716109 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4486465 ps |
| CPU time | 0.38 seconds |
| Started | Feb 07 12:20:24 PM PST 24 |
| Finished | Feb 07 12:20:25 PM PST 24 |
| Peak memory | 145908 kb |
| Host | smart-5e84041b-f9cc-4200-bb49-a25841be620a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45716109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.45716109 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |