| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.31 | 95.24 | 86.36 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.10 | 86.10 | 92.38 | 92.38 | 86.36 | 86.36 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/14.prim_esc_test.963515403 |
| 88.44 | 2.33 | 93.33 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/5.prim_esc_test.3817924614 |
| 90.17 | 1.74 | 94.29 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.2860264698 |
| 91.31 | 1.14 | 95.24 | 0.95 | 86.36 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3703682342 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2328089039 |
| /workspace/coverage/default/1.prim_esc_test.2153843459 |
| /workspace/coverage/default/11.prim_esc_test.2370396648 |
| /workspace/coverage/default/12.prim_esc_test.1841138122 |
| /workspace/coverage/default/13.prim_esc_test.4190942842 |
| /workspace/coverage/default/16.prim_esc_test.800684289 |
| /workspace/coverage/default/17.prim_esc_test.3696544865 |
| /workspace/coverage/default/18.prim_esc_test.1118719762 |
| /workspace/coverage/default/19.prim_esc_test.1896554334 |
| /workspace/coverage/default/2.prim_esc_test.4228318694 |
| /workspace/coverage/default/3.prim_esc_test.4070421674 |
| /workspace/coverage/default/4.prim_esc_test.1355305014 |
| /workspace/coverage/default/6.prim_esc_test.2522235878 |
| /workspace/coverage/default/7.prim_esc_test.1366022633 |
| /workspace/coverage/default/8.prim_esc_test.2355473809 |
| /workspace/coverage/default/9.prim_esc_test.3294558367 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_esc_test.2522235878 | Apr 28 12:28:27 PM PDT 24 | Apr 28 12:28:29 PM PDT 24 | 4711267 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.2153843459 | Apr 28 12:28:22 PM PDT 24 | Apr 28 12:28:28 PM PDT 24 | 4328677 ps | ||
| T3 | /workspace/coverage/default/2.prim_esc_test.4228318694 | Apr 28 12:28:28 PM PDT 24 | Apr 28 12:28:30 PM PDT 24 | 4659944 ps | ||
| T8 | /workspace/coverage/default/4.prim_esc_test.1355305014 | Apr 28 12:28:23 PM PDT 24 | Apr 28 12:28:24 PM PDT 24 | 4866269 ps | ||
| T4 | /workspace/coverage/default/14.prim_esc_test.963515403 | Apr 28 12:28:52 PM PDT 24 | Apr 28 12:28:55 PM PDT 24 | 4486227 ps | ||
| T5 | /workspace/coverage/default/0.prim_esc_test.2328089039 | Apr 28 12:28:27 PM PDT 24 | Apr 28 12:28:28 PM PDT 24 | 4674534 ps | ||
| T6 | /workspace/coverage/default/13.prim_esc_test.4190942842 | Apr 28 12:28:28 PM PDT 24 | Apr 28 12:28:35 PM PDT 24 | 5063574 ps | ||
| T9 | /workspace/coverage/default/11.prim_esc_test.2370396648 | Apr 28 12:28:30 PM PDT 24 | Apr 28 12:28:32 PM PDT 24 | 4848049 ps | ||
| T16 | /workspace/coverage/default/12.prim_esc_test.1841138122 | Apr 28 12:28:25 PM PDT 24 | Apr 28 12:28:27 PM PDT 24 | 4876757 ps | ||
| T7 | /workspace/coverage/default/19.prim_esc_test.1896554334 | Apr 28 12:28:28 PM PDT 24 | Apr 28 12:28:30 PM PDT 24 | 4961665 ps | ||
| T13 | /workspace/coverage/default/9.prim_esc_test.3294558367 | Apr 28 12:28:31 PM PDT 24 | Apr 28 12:28:33 PM PDT 24 | 5071928 ps | ||
| T15 | /workspace/coverage/default/17.prim_esc_test.3696544865 | Apr 28 12:28:29 PM PDT 24 | Apr 28 12:28:31 PM PDT 24 | 4371598 ps | ||
| T17 | /workspace/coverage/default/7.prim_esc_test.1366022633 | Apr 28 12:28:10 PM PDT 24 | Apr 28 12:28:12 PM PDT 24 | 4903183 ps | ||
| T18 | /workspace/coverage/default/8.prim_esc_test.2355473809 | Apr 28 12:28:23 PM PDT 24 | Apr 28 12:28:24 PM PDT 24 | 5201561 ps | ||
| T11 | /workspace/coverage/default/15.prim_esc_test.3703682342 | Apr 28 12:28:44 PM PDT 24 | Apr 28 12:28:44 PM PDT 24 | 4315305 ps | ||
| T14 | /workspace/coverage/default/5.prim_esc_test.3817924614 | Apr 28 12:28:25 PM PDT 24 | Apr 28 12:28:26 PM PDT 24 | 4828136 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.2860264698 | Apr 28 12:28:28 PM PDT 24 | Apr 28 12:28:29 PM PDT 24 | 4718959 ps | ||
| T19 | /workspace/coverage/default/18.prim_esc_test.1118719762 | Apr 28 12:28:15 PM PDT 24 | Apr 28 12:28:17 PM PDT 24 | 4965724 ps | ||
| T20 | /workspace/coverage/default/3.prim_esc_test.4070421674 | Apr 28 12:28:37 PM PDT 24 | Apr 28 12:28:38 PM PDT 24 | 4860529 ps | ||
| T12 | /workspace/coverage/default/16.prim_esc_test.800684289 | Apr 28 12:28:26 PM PDT 24 | Apr 28 12:28:28 PM PDT 24 | 5033529 ps |
| Test location | /workspace/coverage/default/14.prim_esc_test.963515403 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4486227 ps |
| CPU time | 0.38 seconds |
| Started | Apr 28 12:28:52 PM PDT 24 |
| Finished | Apr 28 12:28:55 PM PDT 24 |
| Peak memory | 146356 kb |
| Host | smart-db2d4396-4b22-40f7-ac38-ec4352f6d686 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963515403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.963515403 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3817924614 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4828136 ps |
| CPU time | 0.41 seconds |
| Started | Apr 28 12:28:25 PM PDT 24 |
| Finished | Apr 28 12:28:26 PM PDT 24 |
| Peak memory | 146264 kb |
| Host | smart-4dcf4161-6d62-43de-8c89-4c3eea43fa24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817924614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3817924614 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2860264698 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4718959 ps |
| CPU time | 0.36 seconds |
| Started | Apr 28 12:28:28 PM PDT 24 |
| Finished | Apr 28 12:28:29 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-bba87ca2-f916-48cf-8fae-e56dd2becd6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860264698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2860264698 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3703682342 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4315305 ps |
| CPU time | 0.38 seconds |
| Started | Apr 28 12:28:44 PM PDT 24 |
| Finished | Apr 28 12:28:44 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-7f8abf03-7c5e-4a3f-a51a-a762095341c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703682342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3703682342 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2328089039 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4674534 ps |
| CPU time | 0.37 seconds |
| Started | Apr 28 12:28:27 PM PDT 24 |
| Finished | Apr 28 12:28:28 PM PDT 24 |
| Peak memory | 146264 kb |
| Host | smart-7690d3c6-5293-4990-80ce-43be81b5fd2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328089039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2328089039 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2153843459 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4328677 ps |
| CPU time | 0.43 seconds |
| Started | Apr 28 12:28:22 PM PDT 24 |
| Finished | Apr 28 12:28:28 PM PDT 24 |
| Peak memory | 146256 kb |
| Host | smart-fc798655-d15d-4b33-b374-aed178173238 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153843459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2153843459 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2370396648 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4848049 ps |
| CPU time | 0.38 seconds |
| Started | Apr 28 12:28:30 PM PDT 24 |
| Finished | Apr 28 12:28:32 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-cbc507e5-c544-4895-94c3-a495014f1114 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370396648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2370396648 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1841138122 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4876757 ps |
| CPU time | 0.37 seconds |
| Started | Apr 28 12:28:25 PM PDT 24 |
| Finished | Apr 28 12:28:27 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-d38aa52e-75b9-4879-84e2-02a2489c143d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841138122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1841138122 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.4190942842 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5063574 ps |
| CPU time | 0.36 seconds |
| Started | Apr 28 12:28:28 PM PDT 24 |
| Finished | Apr 28 12:28:35 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-c2cc8e14-2e8c-4004-b218-dc49f1fc407f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190942842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4190942842 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.800684289 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5033529 ps |
| CPU time | 0.38 seconds |
| Started | Apr 28 12:28:26 PM PDT 24 |
| Finished | Apr 28 12:28:28 PM PDT 24 |
| Peak memory | 146292 kb |
| Host | smart-b9decda5-012e-47f4-b2bf-011956cb24a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800684289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.800684289 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3696544865 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4371598 ps |
| CPU time | 0.38 seconds |
| Started | Apr 28 12:28:29 PM PDT 24 |
| Finished | Apr 28 12:28:31 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-9b7f4b6d-0e89-4392-8d00-807b71c8ee42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696544865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3696544865 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1118719762 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4965724 ps |
| CPU time | 0.37 seconds |
| Started | Apr 28 12:28:15 PM PDT 24 |
| Finished | Apr 28 12:28:17 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-cbeaac03-13f5-4c36-9369-1b271f914d1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118719762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1118719762 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1896554334 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4961665 ps |
| CPU time | 0.37 seconds |
| Started | Apr 28 12:28:28 PM PDT 24 |
| Finished | Apr 28 12:28:30 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-7725a9cb-8e26-47e4-bace-0de873219352 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896554334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1896554334 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.4228318694 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4659944 ps |
| CPU time | 0.37 seconds |
| Started | Apr 28 12:28:28 PM PDT 24 |
| Finished | Apr 28 12:28:30 PM PDT 24 |
| Peak memory | 146288 kb |
| Host | smart-cc6ec2d2-30b0-4a8c-9d09-e99f17b597b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228318694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.4228318694 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.4070421674 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4860529 ps |
| CPU time | 0.37 seconds |
| Started | Apr 28 12:28:37 PM PDT 24 |
| Finished | Apr 28 12:28:38 PM PDT 24 |
| Peak memory | 146324 kb |
| Host | smart-d78d0aaf-56aa-4726-8bda-6d1fec22e97f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070421674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.4070421674 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1355305014 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4866269 ps |
| CPU time | 0.4 seconds |
| Started | Apr 28 12:28:23 PM PDT 24 |
| Finished | Apr 28 12:28:24 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-cba3a7b8-17b4-43ed-80ba-67b32ec17d79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355305014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1355305014 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2522235878 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4711267 ps |
| CPU time | 0.37 seconds |
| Started | Apr 28 12:28:27 PM PDT 24 |
| Finished | Apr 28 12:28:29 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-0cc22bb6-cdc5-4edf-8c00-2b5fd3b1dd39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522235878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2522235878 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1366022633 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4903183 ps |
| CPU time | 0.38 seconds |
| Started | Apr 28 12:28:10 PM PDT 24 |
| Finished | Apr 28 12:28:12 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-1a7d7909-c16d-41c1-b5d2-4abf757e09ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366022633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1366022633 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2355473809 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5201561 ps |
| CPU time | 0.37 seconds |
| Started | Apr 28 12:28:23 PM PDT 24 |
| Finished | Apr 28 12:28:24 PM PDT 24 |
| Peak memory | 146292 kb |
| Host | smart-ed4f2ce0-1f1b-4153-a834-1a505f65f973 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355473809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2355473809 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3294558367 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5071928 ps |
| CPU time | 0.4 seconds |
| Started | Apr 28 12:28:31 PM PDT 24 |
| Finished | Apr 28 12:28:33 PM PDT 24 |
| Peak memory | 146260 kb |
| Host | smart-78f1d037-7dc5-44e0-b3a6-ea6af8ae01a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294558367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3294558367 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |