Assertions
dashboard | hierarchy | modlist | groups | tests | asserts

Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total2700
Category 02700


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total2700
Severity 02700


Summary for Assertions
NUMBERPERCENT
Total Number27100.00
Uncovered518.52
Success2281.48
Failure00.00
Incomplete518.52
Without Attempts00.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
prim_esc_tb.i_esc_receiver.EscCntEsc_A 009555000
prim_esc_tb.i_esc_receiver.EscCntWrap_A 009555000
prim_esc_tb.i_esc_sender.PingCheck_A 0095550020
prim_esc_tb.i_esc_sender.SigIntCheck1_A 0095550020
prim_esc_tb.i_esc_sender.SigIntCheck2_A 0095550020

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
prim_esc_tb.i_esc_receiver.DiffEncCheck_A 009555509500
prim_esc_tb.i_esc_receiver.EscEnCheck_A 00955531400
prim_esc_tb.i_esc_receiver.EscEnKnownO_A 009555519500
prim_esc_tb.i_esc_receiver.EscRespCheck_A 009555315020
prim_esc_tb.i_esc_receiver.PingRespCheck_A 00955550020
prim_esc_tb.i_esc_receiver.RespPKnownO_A 009555519500
prim_esc_tb.i_esc_receiver.SigIntCheck0_A 0095554000
prim_esc_tb.i_esc_receiver.SigIntCheck1_A 0095554000
prim_esc_tb.i_esc_receiver.SigIntCheck2_A 0095554000
prim_esc_tb.i_esc_sender.DiffEncCheck_A 009555519500
prim_esc_tb.i_esc_sender.EscCheck_A 00955534600
prim_esc_tb.i_esc_sender.EscPKnownO_A 009555519500
prim_esc_tb.i_esc_sender.EscPingCheck_A 0095552000
prim_esc_tb.i_esc_sender.IntegFailKnownO_A 009555519500
prim_esc_tb.i_esc_sender.PingOkKnownO_A 009555519500
prim_esc_tb.i_esc_sender.SigIntBackCheck_A 0095556000
prim_esc_tb.i_esc_sender.SigIntCheck0_A 0095554000
prim_esc_tb.i_esc_sender.SigIntCheck3_A 0095552000
prim_esc_tb.i_esc_sender.StateEscRespHiBackCheck_A 00955521600
prim_esc_tb.i_esc_sender.StateEscRespHiCheck_A 00955514300
prim_esc_tb.i_esc_sender.StateEscRespLoBackCheck_A 00955519200
prim_esc_tb.i_esc_sender.StateEscRespLoCheck_A 00955518500

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
prim_esc_tb.i_esc_receiver.EscRespCheck_A 009555315020
prim_esc_tb.i_esc_receiver.PingRespCheck_A 00955550020
prim_esc_tb.i_esc_sender.PingCheck_A 0095550020
prim_esc_tb.i_esc_sender.SigIntCheck1_A 0095550020
prim_esc_tb.i_esc_sender.SigIntCheck2_A 0095550020

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%