Module Definition
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Module : prim_esc_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.57 100.00 83.33 100.00 90.91 93.33 81.82

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_esc_tb.i_esc_receiver 91.57 100.00 83.33 100.00 90.91 93.33 81.82



Module Instance : prim_esc_tb.i_esc_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.57 100.00 83.33 100.00 90.91 93.33 81.82


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.57 100.00 83.33 100.00 90.91 93.33 81.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_esc_tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_esc_receiver
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15811100.00
ALWAYS1623939100.00
ALWAYS24233100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
99 1 1
100 1 1
157 1 1
158 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
168 1 1
171 1 1
172 1 1
173 1 1
174 1 1
MISSING_ELSE
180 1 1
181 1 1
182 1 1
183 1 1
184 1 1
185 1 1
MISSING_ELSE
191 1 1
192 1 1
193 1 1
194 1 1
195 1 1
196 1 1
197 1 1
MISSING_ELSE
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
MISSING_ELSE
242 1 1
243 1 1
245 1 1


Cond Coverage for Module : prim_esc_receiver
TotalCoveredPercent
Conditions121083.33
Logical121083.33
Non-Logical00
Event00

 LINE       99
 EXPRESSION (ping_en && ((!(&timeout_cnt))))
             ---1---    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       132
 EXPRESSION (esc_req || ((&timeout_cnt)) || timeout_cnt_error)
             ---1---    --------2-------    --------3--------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       229
 EXPRESSION (sigint_detected && (state_q != SigInt))
             -------1-------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       229
 SUB-EXPRESSION (state_q != SigInt)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Toggle Coverage for Module : prim_esc_receiver
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 14 14 100.00
Total Bits 0->1 7 7 100.00
Total Bits 1->0 7 7 100.00

Ports 7 7 100.00
Port Bits 14 14 100.00
Port Bits 0->1 7 7 100.00
Port Bits 1->0 7 7 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_req_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
esc_rx_o.resp_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
esc_rx_o.resp_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
esc_tx_i.esc_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_tx_i.esc_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT


FSM Coverage for Module : prim_esc_receiver
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 11 10 90.91
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Check 172 Covered T1,T2,T3
EscResp 184 Covered T1,T2,T3
Idle 191 Covered T1,T2,T3
PingResp 180 Covered T1,T2,T3
SigInt 220 Covered T1,T2,T3


transitionsLine No.CoveredTests
Check->EscResp 184 Covered T1,T2,T3
Check->PingResp 180 Covered T1,T2,T3
Check->SigInt 230 Covered T5,T8
EscResp->Idle 203 Covered T1,T2,T3
EscResp->SigInt 230 Covered T2,T3,T4
Idle->Check 172 Covered T1,T2,T3
Idle->SigInt 230 Covered T1,T2,T3
PingResp->EscResp 196 Covered T3,T8,T9
PingResp->Idle 191 Covered T1,T2,T3
PingResp->SigInt 230 Not Covered
SigInt->Idle 217 Covered T1,T2,T3



Branch Coverage for Module : prim_esc_receiver
Line No.TotalCoveredPercent
Branches 15 14 93.33
CASE 168 11 10 90.91
IF 229 2 2 100.00
IF 242 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 168 case (state_q) -2-: 171 if (esc_level) -3-: 183 if (esc_level) -4-: 195 if (esc_level) -5-: 204 if (esc_level) -6-: 219 if (sigint_detected)

Branches:
-1--2--3--4--5--6-StatusTests
Idle 1 - - - - Covered T1,T2,T3
Idle 0 - - - - Covered T1,T2,T3
Check - 1 - - - Covered T1,T2,T3
Check - 0 - - - Covered T1,T2,T3
PingResp - - 1 - - Covered T3,T8,T9
PingResp - - 0 - - Covered T1,T2,T3
EscResp - - - 1 - Covered T1,T2,T3
EscResp - - - 0 - Covered T1,T2,T3
SigInt - - - - 1 Covered T1,T2,T3
SigInt - - - - 0 Covered T1,T2,T3
default - - - - - Not Covered


LineNo. Expression -1-: 229 if ((sigint_detected && (state_q != SigInt)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 242 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_esc_receiver
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 9 81.82
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 9 81.82




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DiffEncCheck_A 9858 5195 0 0
EscCntEsc_A 9858 0 0 0
EscCntWrap_A 9858 0 0 0
EscEnCheck_A 9858 283 0 0
EscEnKnownO_A 9858 5295 0 0
EscRespCheck_A 9858 284 0 20
PingRespCheck_A 9858 54 0 20
RespPKnownO_A 9858 5295 0 0
SigIntCheck0_A 9858 40 0 0
SigIntCheck1_A 9858 40 0 0
SigIntCheck2_A 9858 40 0 0


DiffEncCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 5195 0 0
T1 500 277 0 0
T2 504 254 0 0
T3 528 287 0 0
T4 513 275 0 0
T5 494 230 0 0
T8 470 255 0 0
T10 494 281 0 0
T15 520 265 0 0
T16 491 274 0 0
T17 507 266 0 0

EscCntEsc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 0 0 0

EscCntWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 0 0 0

EscEnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 283 0 0
T1 500 6 0 0
T2 504 16 0 0
T3 528 18 0 0
T4 513 16 0 0
T5 494 4 0 0
T8 470 8 0 0
T10 494 20 0 0
T15 520 23 0 0
T16 491 21 0 0
T17 507 6 0 0

EscEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 5295 0 0
T1 500 282 0 0
T2 504 259 0 0
T3 528 292 0 0
T4 513 280 0 0
T5 494 235 0 0
T8 470 260 0 0
T10 494 286 0 0
T15 520 270 0 0
T16 491 279 0 0
T17 507 271 0 0

EscRespCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 284 0 20
T1 500 6 0 1
T2 504 16 0 1
T3 528 18 0 1
T4 513 16 0 1
T5 494 4 0 1
T8 470 8 0 1
T10 494 20 0 1
T15 520 23 0 1
T16 491 21 0 1
T17 507 6 0 1

PingRespCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 54 0 20
T1 500 3 0 1
T2 504 3 0 1
T3 528 3 0 1
T4 513 2 0 1
T5 494 2 0 1
T8 470 3 0 1
T10 494 3 0 1
T15 520 3 0 1
T16 491 3 0 1
T17 507 2 0 1

RespPKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 5295 0 0
T1 500 282 0 0
T2 504 259 0 0
T3 528 292 0 0
T4 513 280 0 0
T5 494 235 0 0
T8 470 260 0 0
T10 494 286 0 0
T15 520 270 0 0
T16 491 279 0 0
T17 507 271 0 0

SigIntCheck0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 40 0 0
T1 500 2 0 0
T2 504 2 0 0
T3 528 2 0 0
T4 513 2 0 0
T5 494 2 0 0
T8 470 2 0 0
T10 494 2 0 0
T15 520 2 0 0
T16 491 2 0 0
T17 507 2 0 0

SigIntCheck1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 40 0 0
T1 500 2 0 0
T2 504 2 0 0
T3 528 2 0 0
T4 513 2 0 0
T5 494 2 0 0
T8 470 2 0 0
T10 494 2 0 0
T15 520 2 0 0
T16 491 2 0 0
T17 507 2 0 0

SigIntCheck2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9858 40 0 0
T1 500 2 0 0
T2 504 2 0 0
T3 528 2 0 0
T4 513 2 0 0
T5 494 2 0 0
T8 470 2 0 0
T10 494 2 0 0
T15 520 2 0 0
T16 491 2 0 0
T17 507 2 0 0

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