ASSERT | PROPERTIES | SEQUENCES | |
Total | 27 | 0 | 0 |
Category 0 | 27 | 0 | 0 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 27 | 0 | 0 |
Severity 0 | 27 | 0 | 0 |
NUMBER | PERCENT | |
Total Number | 27 | 100.00 |
Uncovered | 5 | 18.52 |
Success | 22 | 81.48 |
Failure | 0 | 0.00 |
Incomplete | 5 | 18.52 |
Without Attempts | 0 | 0.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
prim_esc_tb.i_esc_receiver.EscCntEsc_A | 0 | 0 | 9577 | 0 | 0 | 0 | |
prim_esc_tb.i_esc_receiver.EscCntWrap_A | 0 | 0 | 9577 | 0 | 0 | 0 | |
prim_esc_tb.i_esc_sender.PingCheck_A | 0 | 0 | 9577 | 0 | 0 | 20 | |
prim_esc_tb.i_esc_sender.SigIntCheck1_A | 0 | 0 | 9577 | 0 | 0 | 20 | |
prim_esc_tb.i_esc_sender.SigIntCheck2_A | 0 | 0 | 9577 | 0 | 0 | 20 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
prim_esc_tb.i_esc_receiver.EscRespCheck_A | 0 | 0 | 9577 | 270 | 0 | 20 | |
prim_esc_tb.i_esc_receiver.PingRespCheck_A | 0 | 0 | 9577 | 52 | 0 | 20 | |
prim_esc_tb.i_esc_sender.PingCheck_A | 0 | 0 | 9577 | 0 | 0 | 20 | |
prim_esc_tb.i_esc_sender.SigIntCheck1_A | 0 | 0 | 9577 | 0 | 0 | 20 | |
prim_esc_tb.i_esc_sender.SigIntCheck2_A | 0 | 0 | 9577 | 0 | 0 | 20 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |