| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.23 | 84.23 | 90.48 | 90.48 | 82.93 | 82.93 | 100.00 | 100.00 | 71.43 | 71.43 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/5.prim_esc_test.3011962952 |
| 87.27 | 3.04 | 93.33 | 2.86 | 82.93 | 0.00 | 100.00 | 0.00 | 82.14 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.2405847242 |
| 89.41 | 2.14 | 94.29 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.1618891986 |
| 91.15 | 1.74 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 7.14 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/8.prim_esc_test.2142671063 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.276269525 |
| /workspace/coverage/default/1.prim_esc_test.4087909799 |
| /workspace/coverage/default/10.prim_esc_test.554596561 |
| /workspace/coverage/default/12.prim_esc_test.1111236118 |
| /workspace/coverage/default/13.prim_esc_test.1944951231 |
| /workspace/coverage/default/14.prim_esc_test.2378532022 |
| /workspace/coverage/default/15.prim_esc_test.676318912 |
| /workspace/coverage/default/16.prim_esc_test.1089567109 |
| /workspace/coverage/default/17.prim_esc_test.3829940302 |
| /workspace/coverage/default/18.prim_esc_test.4140631882 |
| /workspace/coverage/default/19.prim_esc_test.2880425367 |
| /workspace/coverage/default/2.prim_esc_test.3357133722 |
| /workspace/coverage/default/3.prim_esc_test.1318604599 |
| /workspace/coverage/default/6.prim_esc_test.1952059566 |
| /workspace/coverage/default/7.prim_esc_test.1899471029 |
| /workspace/coverage/default/9.prim_esc_test.237625370 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_esc_test.3829940302 | Jun 25 04:45:53 PM PDT 24 | Jun 25 04:45:54 PM PDT 24 | 4636278 ps | ||
| T2 | /workspace/coverage/default/13.prim_esc_test.1944951231 | Jun 25 04:46:07 PM PDT 24 | Jun 25 04:46:11 PM PDT 24 | 4572935 ps | ||
| T3 | /workspace/coverage/default/15.prim_esc_test.676318912 | Jun 25 04:45:55 PM PDT 24 | Jun 25 04:45:57 PM PDT 24 | 5229775 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.1318604599 | Jun 25 04:45:46 PM PDT 24 | Jun 25 04:45:47 PM PDT 24 | 4864815 ps | ||
| T6 | /workspace/coverage/default/5.prim_esc_test.3011962952 | Jun 25 04:45:52 PM PDT 24 | Jun 25 04:45:52 PM PDT 24 | 4774110 ps | ||
| T17 | /workspace/coverage/default/6.prim_esc_test.1952059566 | Jun 25 04:46:01 PM PDT 24 | Jun 25 04:46:09 PM PDT 24 | 4924156 ps | ||
| T4 | /workspace/coverage/default/4.prim_esc_test.1618891986 | Jun 25 04:45:59 PM PDT 24 | Jun 25 04:46:07 PM PDT 24 | 5015374 ps | ||
| T7 | /workspace/coverage/default/8.prim_esc_test.2142671063 | Jun 25 04:45:57 PM PDT 24 | Jun 25 04:45:59 PM PDT 24 | 5184035 ps | ||
| T9 | /workspace/coverage/default/9.prim_esc_test.237625370 | Jun 25 04:46:00 PM PDT 24 | Jun 25 04:46:02 PM PDT 24 | 5229928 ps | ||
| T5 | /workspace/coverage/default/1.prim_esc_test.4087909799 | Jun 25 04:45:53 PM PDT 24 | Jun 25 04:45:55 PM PDT 24 | 4724347 ps | ||
| T11 | /workspace/coverage/default/11.prim_esc_test.2405847242 | Jun 25 04:46:05 PM PDT 24 | Jun 25 04:46:09 PM PDT 24 | 4517401 ps | ||
| T13 | /workspace/coverage/default/18.prim_esc_test.4140631882 | Jun 25 04:46:03 PM PDT 24 | Jun 25 04:46:05 PM PDT 24 | 4984708 ps | ||
| T12 | /workspace/coverage/default/16.prim_esc_test.1089567109 | Jun 25 04:46:12 PM PDT 24 | Jun 25 04:46:24 PM PDT 24 | 4611564 ps | ||
| T10 | /workspace/coverage/default/19.prim_esc_test.2880425367 | Jun 25 04:46:01 PM PDT 24 | Jun 25 04:46:02 PM PDT 24 | 4776224 ps | ||
| T15 | /workspace/coverage/default/12.prim_esc_test.1111236118 | Jun 25 04:46:35 PM PDT 24 | Jun 25 04:46:37 PM PDT 24 | 4688085 ps | ||
| T18 | /workspace/coverage/default/7.prim_esc_test.1899471029 | Jun 25 04:46:00 PM PDT 24 | Jun 25 04:46:02 PM PDT 24 | 5015067 ps | ||
| T14 | /workspace/coverage/default/14.prim_esc_test.2378532022 | Jun 25 04:45:53 PM PDT 24 | Jun 25 04:45:54 PM PDT 24 | 4770037 ps | ||
| T19 | /workspace/coverage/default/2.prim_esc_test.3357133722 | Jun 25 04:45:55 PM PDT 24 | Jun 25 04:45:57 PM PDT 24 | 4818966 ps | ||
| T16 | /workspace/coverage/default/0.prim_esc_test.276269525 | Jun 25 04:46:05 PM PDT 24 | Jun 25 04:46:08 PM PDT 24 | 4582184 ps | ||
| T20 | /workspace/coverage/default/10.prim_esc_test.554596561 | Jun 25 04:45:54 PM PDT 24 | Jun 25 04:45:56 PM PDT 24 | 4059092 ps |
| Test location | /workspace/coverage/default/5.prim_esc_test.3011962952 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4774110 ps |
| CPU time | 0.41 seconds |
| Started | Jun 25 04:45:52 PM PDT 24 |
| Finished | Jun 25 04:45:52 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-9f88646a-c327-479e-a593-0e74b2a691a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011962952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3011962952 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2405847242 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4517401 ps |
| CPU time | 0.39 seconds |
| Started | Jun 25 04:46:05 PM PDT 24 |
| Finished | Jun 25 04:46:09 PM PDT 24 |
| Peak memory | 146000 kb |
| Host | smart-5559a150-7e67-4259-8015-43a2efb0d795 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405847242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2405847242 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1618891986 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5015374 ps |
| CPU time | 0.38 seconds |
| Started | Jun 25 04:45:59 PM PDT 24 |
| Finished | Jun 25 04:46:07 PM PDT 24 |
| Peak memory | 145888 kb |
| Host | smart-8ff76831-d7e8-412f-a413-752c449439c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618891986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1618891986 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2142671063 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5184035 ps |
| CPU time | 0.37 seconds |
| Started | Jun 25 04:45:57 PM PDT 24 |
| Finished | Jun 25 04:45:59 PM PDT 24 |
| Peak memory | 145896 kb |
| Host | smart-0445c40a-18ca-4263-b961-218ea15be5d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142671063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2142671063 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.276269525 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4582184 ps |
| CPU time | 0.38 seconds |
| Started | Jun 25 04:46:05 PM PDT 24 |
| Finished | Jun 25 04:46:08 PM PDT 24 |
| Peak memory | 145784 kb |
| Host | smart-28e2cbfb-3ed0-4038-aeee-a24fbc7b9364 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276269525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.276269525 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.4087909799 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4724347 ps |
| CPU time | 0.4 seconds |
| Started | Jun 25 04:45:53 PM PDT 24 |
| Finished | Jun 25 04:45:55 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-6a9d3723-ba38-4604-b394-40fe635ec835 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087909799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4087909799 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.554596561 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4059092 ps |
| CPU time | 0.37 seconds |
| Started | Jun 25 04:45:54 PM PDT 24 |
| Finished | Jun 25 04:45:56 PM PDT 24 |
| Peak memory | 145748 kb |
| Host | smart-6d450644-bd21-4302-bda1-9f7b82b14f12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=554596561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.554596561 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1111236118 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4688085 ps |
| CPU time | 0.38 seconds |
| Started | Jun 25 04:46:35 PM PDT 24 |
| Finished | Jun 25 04:46:37 PM PDT 24 |
| Peak memory | 145728 kb |
| Host | smart-a7ef5814-3db7-416c-b840-ef459d249466 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111236118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1111236118 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1944951231 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4572935 ps |
| CPU time | 0.39 seconds |
| Started | Jun 25 04:46:07 PM PDT 24 |
| Finished | Jun 25 04:46:11 PM PDT 24 |
| Peak memory | 145872 kb |
| Host | smart-756cc67d-c987-43e0-8de9-eff62cccec9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944951231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1944951231 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2378532022 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4770037 ps |
| CPU time | 0.4 seconds |
| Started | Jun 25 04:45:53 PM PDT 24 |
| Finished | Jun 25 04:45:54 PM PDT 24 |
| Peak memory | 145860 kb |
| Host | smart-80e1a73a-e1f6-41db-9a38-b32fdf23bd06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2378532022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2378532022 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.676318912 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5229775 ps |
| CPU time | 0.45 seconds |
| Started | Jun 25 04:45:55 PM PDT 24 |
| Finished | Jun 25 04:45:57 PM PDT 24 |
| Peak memory | 145956 kb |
| Host | smart-485246f2-1920-4267-956c-fe9bdef99e0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=676318912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.676318912 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1089567109 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4611564 ps |
| CPU time | 0.38 seconds |
| Started | Jun 25 04:46:12 PM PDT 24 |
| Finished | Jun 25 04:46:24 PM PDT 24 |
| Peak memory | 145992 kb |
| Host | smart-2cce6acc-6c3e-44ec-bf21-dd10d636500f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089567109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1089567109 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3829940302 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4636278 ps |
| CPU time | 0.42 seconds |
| Started | Jun 25 04:45:53 PM PDT 24 |
| Finished | Jun 25 04:45:54 PM PDT 24 |
| Peak memory | 145804 kb |
| Host | smart-f8580658-29ce-44bd-97ae-be3cebb53542 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829940302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3829940302 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.4140631882 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4984708 ps |
| CPU time | 0.38 seconds |
| Started | Jun 25 04:46:03 PM PDT 24 |
| Finished | Jun 25 04:46:05 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-6e066298-a29f-49c8-8502-5fadb82af9dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4140631882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.4140631882 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2880425367 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4776224 ps |
| CPU time | 0.38 seconds |
| Started | Jun 25 04:46:01 PM PDT 24 |
| Finished | Jun 25 04:46:02 PM PDT 24 |
| Peak memory | 145912 kb |
| Host | smart-b38d8ac4-aba5-41d1-ad8c-338728f7047b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880425367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2880425367 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3357133722 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4818966 ps |
| CPU time | 0.38 seconds |
| Started | Jun 25 04:45:55 PM PDT 24 |
| Finished | Jun 25 04:45:57 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-7443c5e2-1ba3-48ba-a895-11e965cded26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357133722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3357133722 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1318604599 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4864815 ps |
| CPU time | 0.4 seconds |
| Started | Jun 25 04:45:46 PM PDT 24 |
| Finished | Jun 25 04:45:47 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-5847617a-310f-498f-9388-bc2ee68e618b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1318604599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1318604599 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1952059566 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4924156 ps |
| CPU time | 0.39 seconds |
| Started | Jun 25 04:46:01 PM PDT 24 |
| Finished | Jun 25 04:46:09 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-abc8fc9d-882a-462c-8412-4d10e90a8b9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1952059566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1952059566 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1899471029 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5015067 ps |
| CPU time | 0.39 seconds |
| Started | Jun 25 04:46:00 PM PDT 24 |
| Finished | Jun 25 04:46:02 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-e30ff771-81f4-45a5-b495-181723fc3c70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899471029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1899471029 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.237625370 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5229928 ps |
| CPU time | 0.37 seconds |
| Started | Jun 25 04:46:00 PM PDT 24 |
| Finished | Jun 25 04:46:02 PM PDT 24 |
| Peak memory | 145836 kb |
| Host | smart-27676fb1-ed27-45bb-94ba-858e3c89b98e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=237625370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.237625370 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |