Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_esc_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.78 91.53 86.21 100.00 100.00 85.71 81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_esc_tb.i_esc_sender 90.78 91.53 86.21 100.00 100.00 85.71 81.25



Module Instance : prim_esc_tb.i_esc_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.78 91.53 86.21 100.00 100.00 85.71 81.25


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.78 91.53 86.21 100.00 100.00 85.71 81.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_esc_tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_esc_sender
Line No.TotalCoveredPercent
TOTAL595491.53
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8511100.00
ALWAYS108474289.36
ALWAYS21699100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
79 1 1
80 1 1
85 1 1
108 1 1
109 1 1
110 1 1
112 1 1
115 1 1
116 1 1
117 1 1
118 1 1
MISSING_ELSE
122 1 1
123 1 1
MISSING_ELSE
128 1 1
129 1 1
130 1 1
131 1 1
MISSING_ELSE
136 1 1
137 1 1
138 1 1
139 1 1
MISSING_ELSE
145 1 1
148 1 1
149 1 1
151 1 1
152 1 1
153 1 1
MISSING_ELSE
157 1 1
160 1 1
161 1 1
163 1 1
164 0 1
165 0 1
MISSING_ELSE
169 1 1
172 1 1
173 1 1
175 1 1
176 0 1
177 0 1
MISSING_ELSE
181 1 1
184 1 1
185 1 1
187 1 1
188 0 1
190 1 1
199 1 1
200 1 1
201 1 1
MISSING_ELSE
206 1 1
207 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
222 1 1
223 1 1
224 1 1
225 1 1


Cond Coverage for Module : prim_esc_sender
TotalCoveredPercent
Conditions292586.21
Logical292586.21
Non-Logical00
Event00

 LINE       85
 EXPRESSION (esc_req_i | esc_req_q | (ping_req_d & ((~ping_req_q))))
             ----1----   ----2----   ---------------3--------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       85
 SUB-EXPRESSION (ping_req_d & ((~ping_req_q)))
                 -----1----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       117
 EXPRESSION (ping_req_d & ((~ping_req_q)))
             -----1----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       129
 EXPRESSION (((!esc_tx_o.esc_p)) || resp)
             ---------1---------    --2-
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10CoveredT1,T2,T3

 LINE       131
 EXPRESSION (sigint_detected | resp)
             -------1-------   --2-
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       137
 EXPRESSION (((!esc_tx_o.esc_p)) || ((!resp)))
             ---------1---------    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T6,T5

 LINE       139
 EXPRESSION (sigint_detected | ((~resp)))
             -------1-------   ----2----
-1--2-StatusTests
00CoveredT2,T6,T5
01Not Covered
10Not Covered

 LINE       206
 EXPRESSION ((esc_req_i || esc_req_q || esc_req_q1) && ping_req_i)
             -------------------1------------------    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       206
 SUB-EXPRESSION (esc_req_i || esc_req_q || esc_req_q1)
                 ----1----    ----2----    -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Toggle Coverage for Module : prim_esc_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ping_req_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ping_ok_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
integ_fail_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
esc_req_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_rx_i.resp_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_rx_i.resp_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
esc_tx_o.esc_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
esc_tx_o.esc_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT


FSM Coverage for Module : prim_esc_sender
Summary for FSM :: state_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 17 17 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
CheckEscRespHi 116 Covered T1,T2,T3
CheckEscRespLo 136 Covered T1,T2,T3
CheckPingResp0 118 Covered T1,T2,T3
CheckPingResp1 145 Covered T1,T2,T3
CheckPingResp2 157 Covered T1,T2,T3
CheckPingResp3 169 Covered T1,T2,T3
Idle 130 Covered T1,T2,T3


transitionsLine No.CoveredTests
CheckEscRespHi->CheckEscRespLo 136 Covered T1,T2,T3
CheckEscRespHi->Idle 138 Covered T1,T2,T7
CheckEscRespLo->CheckEscRespHi 128 Covered T1,T2,T3
CheckEscRespLo->Idle 130 Covered T1,T2,T3
CheckPingResp0->CheckEscRespLo 149 Covered T5,T8,T9
CheckPingResp0->CheckPingResp1 145 Covered T1,T2,T3
CheckPingResp0->Idle 152 Covered T1,T2,T3
CheckPingResp1->CheckEscRespHi 161 Covered T1,T7,T10
CheckPingResp1->CheckPingResp2 157 Covered T1,T2,T3
CheckPingResp1->Idle 164 Covered T1,T4,T11
CheckPingResp2->CheckEscRespLo 173 Covered T12
CheckPingResp2->CheckPingResp3 169 Covered T1,T2,T3
CheckPingResp2->Idle 176 Covered T13,T5,T12
CheckPingResp3->CheckEscRespHi 185 Covered T3,T4
CheckPingResp3->Idle 181 Covered T1,T2,T3
Idle->CheckEscRespHi 116 Covered T1,T2,T3
Idle->CheckPingResp0 118 Covered T1,T2,T3



Branch Coverage for Module : prim_esc_sender
Line No.TotalCoveredPercent
Branches 28 24 85.71
CASE 112 22 18 81.82
IF 199 2 2 100.00
IF 206 2 2 100.00
IF 216 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 112 case (state_q) -2-: 115 if (esc_req_i) -3-: 117 if ((ping_req_d & (~ping_req_q))) -4-: 122 if (resp) -5-: 129 if (((!esc_tx_o.esc_p) || resp)) -6-: 137 if (((!esc_tx_o.esc_p) || (!resp))) -7-: 148 if (esc_req_i) -8-: 151 if ((!resp)) -9-: 160 if (esc_req_i) -10-: 163 if (resp) -11-: 172 if (esc_req_i) -12-: 175 if ((!resp)) -13-: 184 if (esc_req_i) -14-: 187 if (resp)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
Idle 1 - - - - - - - - - - - - Covered T1,T2,T3
Idle 0 1 - - - - - - - - - - - Covered T1,T2,T3
Idle 0 0 - - - - - - - - - - - Covered T1,T2,T3
Idle - - 1 - - - - - - - - - - Covered T1,T2,T3
Idle - - 0 - - - - - - - - - - Covered T1,T2,T3
CheckEscRespLo - - - 1 - - - - - - - - - Covered T1,T2,T3
CheckEscRespLo - - - 0 - - - - - - - - - Covered T1,T2,T3
CheckEscRespHi - - - - 1 - - - - - - - - Covered T1,T2,T3
CheckEscRespHi - - - - 0 - - - - - - - - Covered T1,T2,T3
CheckPingResp0 - - - - - 1 - - - - - - - Covered T5,T8,T9
CheckPingResp0 - - - - - 0 1 - - - - - - Covered T1,T2,T3
CheckPingResp0 - - - - - 0 0 - - - - - - Covered T1,T2,T3
CheckPingResp1 - - - - - - - 1 - - - - - Covered T1,T7,T10
CheckPingResp1 - - - - - - - 0 1 - - - - Not Covered
CheckPingResp1 - - - - - - - 0 0 - - - - Covered T1,T2,T3
CheckPingResp2 - - - - - - - - - 1 - - - Covered T12
CheckPingResp2 - - - - - - - - - 0 1 - - Not Covered
CheckPingResp2 - - - - - - - - - 0 0 - - Covered T1,T2,T3
CheckPingResp3 - - - - - - - - - - - 1 - Covered T3,T4
CheckPingResp3 - - - - - - - - - - - 0 1 Not Covered
CheckPingResp3 - - - - - - - - - - - 0 0 Covered T1,T2,T3
default - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 199 if (sigint_detected)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 206 if ((((esc_req_i || esc_req_q) || esc_req_q1) && ping_req_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 216 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_esc_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 13 81.25
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 13 81.25




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DiffEncCheck_A 9541 5046 0 0
EscCheck_A 9541 295 0 0
EscPKnownO_A 9541 5046 0 0
EscPingCheck_A 9541 20 0 0
IntegFailKnownO_A 9541 5046 0 0
PingCheck_A 9541 0 0 20
PingOkKnownO_A 9541 5046 0 0
SigIntBackCheck_A 9541 60 0 0
SigIntCheck0_A 9541 40 0 0
SigIntCheck1_A 9541 0 0 20
SigIntCheck2_A 9541 0 0 20
SigIntCheck3_A 9541 20 0 0
StateEscRespHiBackCheck_A 9541 189 0 0
StateEscRespHiCheck_A 9541 114 0 0
StateEscRespLoBackCheck_A 9541 167 0 0
StateEscRespLoCheck_A 9541 162 0 0


DiffEncCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 5046 0 0
T1 446 248 0 0
T2 508 249 0 0
T3 491 256 0 0
T4 471 253 0 0
T6 492 265 0 0
T7 463 217 0 0
T10 486 254 0 0
T14 515 280 0 0
T15 504 281 0 0
T16 532 280 0 0

EscCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 295 0 0
T1 446 12 0 0
T2 508 23 0 0
T3 491 15 0 0
T4 471 5 0 0
T6 492 13 0 0
T7 463 16 0 0
T10 486 20 0 0
T14 515 22 0 0
T15 504 22 0 0
T16 532 20 0 0

EscPKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 5046 0 0
T1 446 248 0 0
T2 508 249 0 0
T3 491 256 0 0
T4 471 253 0 0
T6 492 265 0 0
T7 463 217 0 0
T10 486 254 0 0
T14 515 280 0 0
T15 504 281 0 0
T16 532 280 0 0

EscPingCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 20 0 0
T1 446 1 0 0
T2 508 1 0 0
T3 491 1 0 0
T4 471 1 0 0
T6 492 1 0 0
T7 463 1 0 0
T10 486 1 0 0
T14 515 1 0 0
T15 504 1 0 0
T16 532 1 0 0

IntegFailKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 5046 0 0
T1 446 248 0 0
T2 508 249 0 0
T3 491 256 0 0
T4 471 253 0 0
T6 492 265 0 0
T7 463 217 0 0
T10 486 254 0 0
T14 515 280 0 0
T15 504 281 0 0
T16 532 280 0 0

PingCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 0 0 20

PingOkKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 5046 0 0
T1 446 248 0 0
T2 508 249 0 0
T3 491 256 0 0
T4 471 253 0 0
T6 492 265 0 0
T7 463 217 0 0
T10 486 254 0 0
T14 515 280 0 0
T15 504 281 0 0
T16 532 280 0 0

SigIntBackCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 60 0 0
T1 446 3 0 0
T2 508 3 0 0
T3 491 3 0 0
T4 471 3 0 0
T6 492 3 0 0
T7 463 3 0 0
T10 486 3 0 0
T14 515 3 0 0
T15 504 3 0 0
T16 532 3 0 0

SigIntCheck0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 40 0 0
T1 446 2 0 0
T2 508 2 0 0
T3 491 2 0 0
T4 471 2 0 0
T6 492 2 0 0
T7 463 2 0 0
T10 486 2 0 0
T14 515 2 0 0
T15 504 2 0 0
T16 532 2 0 0

SigIntCheck1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 0 0 20

SigIntCheck2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 0 0 20

SigIntCheck3_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 20 0 0
T1 446 1 0 0
T2 508 1 0 0
T3 491 1 0 0
T4 471 1 0 0
T6 492 1 0 0
T7 463 1 0 0
T10 486 1 0 0
T14 515 1 0 0
T15 504 1 0 0
T16 532 1 0 0

StateEscRespHiBackCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 189 0 0
T1 446 8 0 0
T2 508 14 0 0
T3 491 9 0 0
T4 471 4 0 0
T6 492 9 0 0
T7 463 10 0 0
T10 486 13 0 0
T14 515 13 0 0
T15 504 13 0 0
T16 532 12 0 0

StateEscRespHiCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 114 0 0
T1 446 4 0 0
T2 508 10 0 0
T3 491 5 0 0
T4 471 0 0 0
T5 0 3 0 0
T6 492 5 0 0
T7 463 6 0 0
T10 486 9 0 0
T14 515 9 0 0
T15 504 9 0 0
T16 532 8 0 0

StateEscRespLoBackCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 167 0 0
T1 446 7 0 0
T2 508 12 0 0
T3 491 9 0 0
T4 471 4 0 0
T6 492 7 0 0
T7 463 9 0 0
T10 486 11 0 0
T14 515 12 0 0
T15 504 12 0 0
T16 532 11 0 0

StateEscRespLoCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9541 162 0 0
T1 446 7 0 0
T2 508 12 0 0
T3 491 9 0 0
T4 471 4 0 0
T6 492 7 0 0
T7 463 9 0 0
T10 486 11 0 0
T14 515 12 0 0
T15 504 12 0 0
T16 532 11 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%