Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	100.00	83.33	100.00	90.91	93.33	81.82

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_esc_tb.i_esc_receiver	91.57	100.00	83.33	100.00	90.91	93.33	81.82

---

Module Instance : prim_esc_tb.i_esc_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	100.00	83.33	100.00	90.91	93.33	81.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	100.00	83.33	100.00	90.91	93.33	81.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_esc_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
ALWAYS	162	39	39	100.00
ALWAYS	242	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
99	1	1
100	1	1
157	1	1
158	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
168	1	1
171	1	1
172	1	1
173	1	1
174	1	1
			MISSING_ELSE
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
242	1	1
243	1	1
245	1	1

---

Cond Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Conditions	12	10	83.33
Logical	12	10	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (ping_en && ((!(&timeout_cnt))))
             ---1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (esc_req || ((&timeout_cnt)) || timeout_cnt_error)
             ---1---    --------2-------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       229
 EXPRESSION (sigint_detected && (state_q != SigInt))
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       229
 SUB-EXPRESSION (state_q != SigInt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_esc_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Check	172	Covered	T1,T2,T3
EscResp	184	Covered	T1,T2,T3
Idle	191	Covered	T1,T2,T3
PingResp	180	Covered	T1,T2,T3
SigInt	220	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Check->EscResp	184	Covered	T1,T2,T3
Check->PingResp	180	Covered	T1,T2,T3
Check->SigInt	230	Covered	T4,T5,T8
EscResp->Idle	203	Covered	T1,T2,T3
EscResp->SigInt	230	Covered	T1,T2,T3
Idle->Check	172	Covered	T1,T2,T3
Idle->SigInt	230	Covered	T1,T2,T3
PingResp->EscResp	196	Covered	T1,T10,T11
PingResp->Idle	191	Covered	T1,T2,T3
PingResp->SigInt	230	Not Covered
SigInt->Idle	217	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
Branches		15	14	93.33
CASE	168	11	10	90.91
IF	229	2	2	100.00
IF	242	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	168	case (state_q)
-2-:	171	if (esc_level)
-3-:	183	if (esc_level)
-4-:	195	if (esc_level)
-5-:	204	if (esc_level)
-6-:	219	if (sigint_detected)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
Idle	1	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	Covered	T1,T2,T3
Check	-	1	-	-	-	Covered	T1,T2,T3
Check	-	0	-	-	-	Covered	T1,T2,T3
PingResp	-	-	1	-	-	Covered	T1,T10,T11
PingResp	-	-	0	-	-	Covered	T1,T2,T3
EscResp	-	-	-	1	-	Covered	T1,T2,T3
EscResp	-	-	-	0	-	Covered	T1,T2,T3
SigInt	-	-	-	-	1	Covered	T1,T2,T3
SigInt	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	229	if ((sigint_detected && (state_q != SigInt)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_esc_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	9	81.82
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	9	81.82

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DiffEncCheck_A	9458	4920	0	0
EscCntEsc_A	9458	0	0	0
EscCntWrap_A	9458	0	0	0
EscEnCheck_A	9458	273	0	0
EscEnKnownO_A	9458	5020	0	0
EscRespCheck_A	9458	273	0	20
PingRespCheck_A	9458	53	0	20
RespPKnownO_A	9458	5020	0	0
SigIntCheck0_A	9458	40	0	0
SigIntCheck1_A	9458	40	0	0
SigIntCheck2_A	9458	40	0	0

DiffEncCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	4920	0	0
T1	480	248	0	0
T2	463	239	0	0
T3	498	263	0	0
T4	463	245	0	0
T5	526	252	0	0
T6	439	217	0	0
T7	430	240	0	0
T10	451	228	0	0
T11	501	265	0	0
T14	530	257	0	0

EscCntEsc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	0	0	0

EscCntWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	0	0	0

EscEnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	273	0	0
T1	480	10	0	0
T2	463	14	0	0
T3	498	21	0	0
T4	463	6	0	0
T5	526	9	0	0
T6	439	12	0	0
T7	430	7	0	0
T10	451	9	0	0
T11	501	19	0	0
T14	530	18	0	0

EscEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	5020	0	0
T1	480	253	0	0
T2	463	244	0	0
T3	498	268	0	0
T4	463	250	0	0
T5	526	257	0	0
T6	439	222	0	0
T7	430	245	0	0
T10	451	233	0	0
T11	501	270	0	0
T14	530	262	0	0

EscRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	273	0	20
T1	480	10	0	1
T2	463	14	0	1
T3	498	21	0	1
T4	463	6	0	1
T5	526	9	0	1
T6	439	12	0	1
T7	430	7	0	1
T10	451	9	0	1
T11	501	19	0	1
T14	530	18	0	1

PingRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	53	0	20
T1	480	2	0	1
T2	463	1	0	1
T3	498	3	0	1
T4	463	3	0	1
T5	526	3	0	1
T6	439	2	0	1
T7	430	3	0	1
T10	451	3	0	1
T11	501	3	0	1
T14	530	3	0	1

RespPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	5020	0	0
T1	480	253	0	0
T2	463	244	0	0
T3	498	268	0	0
T4	463	250	0	0
T5	526	257	0	0
T6	439	222	0	0
T7	430	245	0	0
T10	451	233	0	0
T11	501	270	0	0
T14	530	262	0	0

SigIntCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	40	0	0
T1	480	2	0	0
T2	463	2	0	0
T3	498	2	0	0
T4	463	2	0	0
T5	526	2	0	0
T6	439	2	0	0
T7	430	2	0	0
T10	451	2	0	0
T11	501	2	0	0
T14	530	2	0	0

SigIntCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	40	0	0
T1	480	2	0	0
T2	463	2	0	0
T3	498	2	0	0
T4	463	2	0	0
T5	526	2	0	0
T6	439	2	0	0
T7	430	2	0	0
T10	451	2	0	0
T11	501	2	0	0
T14	530	2	0	0

SigIntCheck2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9458	40	0	0
T1	480	2	0	0
T2	463	2	0	0
T3	498	2	0	0
T4	463	2	0	0
T5	526	2	0	0
T6	439	2	0	0
T7	430	2	0	0
T10	451	2	0	0
T11	501	2	0	0
T14	530	2	0	0