Assertions
dashboard | hierarchy | modlist | groups | tests | asserts

Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total2700
Category 02700


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total2700
Severity 02700


Summary for Assertions
NUMBERPERCENT
Total Number27100.00
Uncovered518.52
Success2281.48
Failure00.00
Incomplete518.52
Without Attempts00.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
prim_esc_tb.i_esc_receiver.EscCntEsc_A 009791000
prim_esc_tb.i_esc_receiver.EscCntWrap_A 009791000
prim_esc_tb.i_esc_sender.PingCheck_A 0097910020
prim_esc_tb.i_esc_sender.SigIntCheck1_A 0097910020
prim_esc_tb.i_esc_sender.SigIntCheck2_A 0097910020

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
prim_esc_tb.i_esc_receiver.DiffEncCheck_A 009791512600
prim_esc_tb.i_esc_receiver.EscEnCheck_A 00979127700
prim_esc_tb.i_esc_receiver.EscEnKnownO_A 009791522600
prim_esc_tb.i_esc_receiver.EscRespCheck_A 009791277020
prim_esc_tb.i_esc_receiver.PingRespCheck_A 00979146020
prim_esc_tb.i_esc_receiver.RespPKnownO_A 009791522600
prim_esc_tb.i_esc_receiver.SigIntCheck0_A 0097914000
prim_esc_tb.i_esc_receiver.SigIntCheck1_A 0097914000
prim_esc_tb.i_esc_receiver.SigIntCheck2_A 0097914000
prim_esc_tb.i_esc_sender.DiffEncCheck_A 009791522600
prim_esc_tb.i_esc_sender.EscCheck_A 00979130800
prim_esc_tb.i_esc_sender.EscPKnownO_A 009791522600
prim_esc_tb.i_esc_sender.EscPingCheck_A 0097912000
prim_esc_tb.i_esc_sender.IntegFailKnownO_A 009791522600
prim_esc_tb.i_esc_sender.PingOkKnownO_A 009791522600
prim_esc_tb.i_esc_sender.SigIntBackCheck_A 0097916000
prim_esc_tb.i_esc_sender.SigIntCheck0_A 0097914000
prim_esc_tb.i_esc_sender.SigIntCheck3_A 0097912000
prim_esc_tb.i_esc_sender.StateEscRespHiBackCheck_A 00979119500
prim_esc_tb.i_esc_sender.StateEscRespHiCheck_A 00979112100
prim_esc_tb.i_esc_sender.StateEscRespLoBackCheck_A 00979117300
prim_esc_tb.i_esc_sender.StateEscRespLoCheck_A 00979116800

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
prim_esc_tb.i_esc_receiver.EscRespCheck_A 009791277020
prim_esc_tb.i_esc_receiver.PingRespCheck_A 00979146020
prim_esc_tb.i_esc_sender.PingCheck_A 0097910020
prim_esc_tb.i_esc_sender.SigIntCheck1_A 0097910020
prim_esc_tb.i_esc_sender.SigIntCheck2_A 0097910020

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%