| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 89.41 | 94.29 | 85.37 | 100.00 | 89.29 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.64 | 84.64 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 71.43 | 71.43 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/7.prim_esc_test.3124820009 |
| 87.08 | 2.44 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 78.57 | 7.14 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.2365382933 |
| 88.27 | 1.19 | 93.33 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.868870916 |
| 89.41 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.1504525907 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3748567078 |
| /workspace/coverage/default/1.prim_esc_test.3228713438 |
| /workspace/coverage/default/11.prim_esc_test.4251478376 |
| /workspace/coverage/default/13.prim_esc_test.1674239749 |
| /workspace/coverage/default/14.prim_esc_test.3211094625 |
| /workspace/coverage/default/15.prim_esc_test.421492891 |
| /workspace/coverage/default/17.prim_esc_test.3108567500 |
| /workspace/coverage/default/18.prim_esc_test.2594781923 |
| /workspace/coverage/default/19.prim_esc_test.2623158900 |
| /workspace/coverage/default/2.prim_esc_test.4036014417 |
| /workspace/coverage/default/3.prim_esc_test.3433932457 |
| /workspace/coverage/default/4.prim_esc_test.1016124849 |
| /workspace/coverage/default/5.prim_esc_test.2575536980 |
| /workspace/coverage/default/6.prim_esc_test.3975286894 |
| /workspace/coverage/default/8.prim_esc_test.3147657955 |
| /workspace/coverage/default/9.prim_esc_test.2174045761 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_esc_test.1674239749 | Jul 23 04:21:21 PM PDT 24 | Jul 23 04:21:22 PM PDT 24 | 5044527 ps | ||
| T2 | /workspace/coverage/default/2.prim_esc_test.4036014417 | Jul 23 04:21:27 PM PDT 24 | Jul 23 04:21:28 PM PDT 24 | 4811307 ps | ||
| T3 | /workspace/coverage/default/7.prim_esc_test.3124820009 | Jul 23 04:21:23 PM PDT 24 | Jul 23 04:21:24 PM PDT 24 | 4979596 ps | ||
| T11 | /workspace/coverage/default/12.prim_esc_test.1504525907 | Jul 23 04:21:25 PM PDT 24 | Jul 23 04:21:26 PM PDT 24 | 4999868 ps | ||
| T4 | /workspace/coverage/default/1.prim_esc_test.3228713438 | Jul 23 04:26:35 PM PDT 24 | Jul 23 04:26:37 PM PDT 24 | 5593743 ps | ||
| T13 | /workspace/coverage/default/8.prim_esc_test.3147657955 | Jul 23 04:21:36 PM PDT 24 | Jul 23 04:21:37 PM PDT 24 | 5088672 ps | ||
| T14 | /workspace/coverage/default/3.prim_esc_test.3433932457 | Jul 23 04:21:36 PM PDT 24 | Jul 23 04:21:38 PM PDT 24 | 4125689 ps | ||
| T8 | /workspace/coverage/default/4.prim_esc_test.1016124849 | Jul 23 04:21:27 PM PDT 24 | Jul 23 04:21:28 PM PDT 24 | 4559623 ps | ||
| T9 | /workspace/coverage/default/6.prim_esc_test.3975286894 | Jul 23 04:26:34 PM PDT 24 | Jul 23 04:26:36 PM PDT 24 | 4569241 ps | ||
| T5 | /workspace/coverage/default/18.prim_esc_test.2594781923 | Jul 23 04:21:36 PM PDT 24 | Jul 23 04:21:37 PM PDT 24 | 4731249 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.868870916 | Jul 23 04:21:25 PM PDT 24 | Jul 23 04:21:26 PM PDT 24 | 4171121 ps | ||
| T12 | /workspace/coverage/default/14.prim_esc_test.3211094625 | Jul 23 04:21:36 PM PDT 24 | Jul 23 04:21:37 PM PDT 24 | 4879287 ps | ||
| T6 | /workspace/coverage/default/19.prim_esc_test.2623158900 | Jul 23 04:21:27 PM PDT 24 | Jul 23 04:21:28 PM PDT 24 | 4696334 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.421492891 | Jul 23 04:26:35 PM PDT 24 | Jul 23 04:26:38 PM PDT 24 | 5115052 ps | ||
| T16 | /workspace/coverage/default/17.prim_esc_test.3108567500 | Jul 23 04:21:37 PM PDT 24 | Jul 23 04:21:38 PM PDT 24 | 4917752 ps | ||
| T7 | /workspace/coverage/default/16.prim_esc_test.2365382933 | Jul 23 04:26:34 PM PDT 24 | Jul 23 04:26:36 PM PDT 24 | 5089455 ps | ||
| T17 | /workspace/coverage/default/9.prim_esc_test.2174045761 | Jul 23 04:21:36 PM PDT 24 | Jul 23 04:21:38 PM PDT 24 | 5128878 ps | ||
| T18 | /workspace/coverage/default/5.prim_esc_test.2575536980 | Jul 23 04:21:36 PM PDT 24 | Jul 23 04:21:37 PM PDT 24 | 5016366 ps | ||
| T19 | /workspace/coverage/default/11.prim_esc_test.4251478376 | Jul 23 04:21:37 PM PDT 24 | Jul 23 04:21:39 PM PDT 24 | 5026183 ps | ||
| T20 | /workspace/coverage/default/0.prim_esc_test.3748567078 | Jul 23 04:21:28 PM PDT 24 | Jul 23 04:21:29 PM PDT 24 | 5552103 ps |
| Test location | /workspace/coverage/default/7.prim_esc_test.3124820009 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4979596 ps |
| CPU time | 0.37 seconds |
| Started | Jul 23 04:21:23 PM PDT 24 |
| Finished | Jul 23 04:21:24 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-12949d1e-e4b6-4c64-bbfe-f21dfafa19d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124820009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3124820009 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2365382933 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5089455 ps |
| CPU time | 0.36 seconds |
| Started | Jul 23 04:26:34 PM PDT 24 |
| Finished | Jul 23 04:26:36 PM PDT 24 |
| Peak memory | 145408 kb |
| Host | smart-e1c596a9-beb8-4ac1-8e09-0643be53eaec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365382933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2365382933 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.868870916 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4171121 ps |
| CPU time | 0.48 seconds |
| Started | Jul 23 04:21:25 PM PDT 24 |
| Finished | Jul 23 04:21:26 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-69eb87ae-a83e-4301-8d79-8bf05c901a97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868870916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.868870916 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1504525907 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4999868 ps |
| CPU time | 0.45 seconds |
| Started | Jul 23 04:21:25 PM PDT 24 |
| Finished | Jul 23 04:21:26 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-56bdea73-8fd5-438b-bad3-639b71ed05e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504525907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1504525907 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3748567078 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5552103 ps |
| CPU time | 0.39 seconds |
| Started | Jul 23 04:21:28 PM PDT 24 |
| Finished | Jul 23 04:21:29 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-215650c2-53bd-4e3d-8b9e-ab38230f3695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748567078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3748567078 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3228713438 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5593743 ps |
| CPU time | 0.36 seconds |
| Started | Jul 23 04:26:35 PM PDT 24 |
| Finished | Jul 23 04:26:37 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-bbd7cf56-f217-48ed-b072-62a1a49724ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228713438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3228713438 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.4251478376 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5026183 ps |
| CPU time | 0.44 seconds |
| Started | Jul 23 04:21:37 PM PDT 24 |
| Finished | Jul 23 04:21:39 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-c841e5b9-d043-455f-809e-c7f32f7d3e92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251478376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4251478376 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1674239749 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5044527 ps |
| CPU time | 0.37 seconds |
| Started | Jul 23 04:21:21 PM PDT 24 |
| Finished | Jul 23 04:21:22 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-fcd6dc50-1825-4a2d-9a2e-3ba6775da4ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674239749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1674239749 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3211094625 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4879287 ps |
| CPU time | 0.43 seconds |
| Started | Jul 23 04:21:36 PM PDT 24 |
| Finished | Jul 23 04:21:37 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-a46c0366-c908-49bc-bda0-8a79f739cba9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211094625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3211094625 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.421492891 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5115052 ps |
| CPU time | 0.36 seconds |
| Started | Jul 23 04:26:35 PM PDT 24 |
| Finished | Jul 23 04:26:38 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-1de485ab-8c2e-41cf-8440-317921d5b2e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421492891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.421492891 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3108567500 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4917752 ps |
| CPU time | 0.37 seconds |
| Started | Jul 23 04:21:37 PM PDT 24 |
| Finished | Jul 23 04:21:38 PM PDT 24 |
| Peak memory | 145552 kb |
| Host | smart-1f0cbdab-6ea1-42f3-9afb-be5ee3ad74ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3108567500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3108567500 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2594781923 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4731249 ps |
| CPU time | 0.38 seconds |
| Started | Jul 23 04:21:36 PM PDT 24 |
| Finished | Jul 23 04:21:37 PM PDT 24 |
| Peak memory | 145548 kb |
| Host | smart-fce1ff41-2861-4950-9456-ec696889c4e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594781923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2594781923 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2623158900 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4696334 ps |
| CPU time | 0.4 seconds |
| Started | Jul 23 04:21:27 PM PDT 24 |
| Finished | Jul 23 04:21:28 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-ec3ac1ec-7d32-4131-93c6-19be090a228a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623158900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2623158900 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.4036014417 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4811307 ps |
| CPU time | 0.42 seconds |
| Started | Jul 23 04:21:27 PM PDT 24 |
| Finished | Jul 23 04:21:28 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-e319b07b-fb36-49df-a776-ae84ee9f0398 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036014417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.4036014417 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3433932457 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4125689 ps |
| CPU time | 0.5 seconds |
| Started | Jul 23 04:21:36 PM PDT 24 |
| Finished | Jul 23 04:21:38 PM PDT 24 |
| Peak memory | 145416 kb |
| Host | smart-32d34df3-2528-4c20-9cdb-0ef4a6ef4151 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433932457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3433932457 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1016124849 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4559623 ps |
| CPU time | 0.41 seconds |
| Started | Jul 23 04:21:27 PM PDT 24 |
| Finished | Jul 23 04:21:28 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-02a127a4-ee73-4281-891e-07bfcfb8dead |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1016124849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1016124849 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2575536980 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5016366 ps |
| CPU time | 0.43 seconds |
| Started | Jul 23 04:21:36 PM PDT 24 |
| Finished | Jul 23 04:21:37 PM PDT 24 |
| Peak memory | 145612 kb |
| Host | smart-c6405ad6-3d27-4d8b-9014-0a39bace8174 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575536980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2575536980 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3975286894 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4569241 ps |
| CPU time | 0.41 seconds |
| Started | Jul 23 04:26:34 PM PDT 24 |
| Finished | Jul 23 04:26:36 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-5b028e21-d5f0-4cc4-875f-598bca7f998c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975286894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3975286894 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3147657955 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5088672 ps |
| CPU time | 0.37 seconds |
| Started | Jul 23 04:21:36 PM PDT 24 |
| Finished | Jul 23 04:21:37 PM PDT 24 |
| Peak memory | 145848 kb |
| Host | smart-a221978b-1019-4dcf-b06f-af595d2b47e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147657955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3147657955 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2174045761 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5128878 ps |
| CPU time | 0.47 seconds |
| Started | Jul 23 04:21:36 PM PDT 24 |
| Finished | Jul 23 04:21:38 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-10926701-e944-4806-a912-f00ca801f0bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174045761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2174045761 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |