Unified Coverage Report :: Module :: prim_esc_sender

Module : prim_esc_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.92	89.83	86.21	100.00	94.12	82.14	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_esc_tb.i_esc_sender	88.92	89.83	86.21	100.00	94.12	82.14	81.25

---

Module Instance : prim_esc_tb.i_esc_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.92	89.83	86.21	100.00	94.12	82.14	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.92	89.83	86.21	100.00	94.12	82.14	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_esc_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_esc_sender

	Line No.	Total	Covered	Percent
TOTAL		59	53	89.83
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	108	47	41	87.23
ALWAYS	216	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
79	1	1
80	1	1
85	1	1
108	1	1
109	1	1
110	1	1
112	1	1
115	1	1
116	1	1
117	1	1
118	1	1
			MISSING_ELSE
122	1	1
123	1	1
			MISSING_ELSE
128	1	1
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
136	1	1
137	1	1
138	1	1
139	1	1
			MISSING_ELSE
145	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
157	1	1
160	1	1
161	1	1
163	1	1
164	0	1
165	0	1
			MISSING_ELSE
169	1	1
172	1	1
173	0	1
175	1	1
176	0	1
177	0	1
			MISSING_ELSE
181	1	1
184	1	1
185	1	1
187	1	1
188	0	1
190	1	1
199	1	1
200	1	1
201	1	1
			MISSING_ELSE
206	1	1
207	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
222	1	1
223	1	1
224	1	1
225	1	1

---

Cond Coverage for Module : prim_esc_sender

	Total	Covered	Percent
Conditions	29	25	86.21
Logical	29	25	86.21
Non-Logical	0	0
Event	0	0

 LINE       85
 EXPRESSION (esc_req_i | esc_req_q | (ping_req_d & ((~ping_req_q))))
             ----1----   ----2----   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       85
 SUB-EXPRESSION (ping_req_d & ((~ping_req_q)))
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION (ping_req_d & ((~ping_req_q)))
             -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (((!esc_tx_o.esc_p)) || resp)
             ---------1---------    --2-

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T5,T6

 LINE       131
 EXPRESSION (sigint_detected | resp)
             -------1-------   --2-

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Not Covered
1	0	Not Covered

 LINE       137
 EXPRESSION (((!esc_tx_o.esc_p)) || ((!resp)))
             ---------1---------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (sigint_detected | ((~resp)))
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       206
 EXPRESSION ((esc_req_i || esc_req_q || esc_req_q1) && ping_req_i)
             -------------------1------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       206
 SUB-EXPRESSION (esc_req_i || esc_req_q || esc_req_q1)
                 ----1----    ----2----    -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T6,T7,T8
1	0	0	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_esc_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_rx_i.resp_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_rx_i.resp_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_o.esc_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_tx_o.esc_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_esc_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	17	16	94.12
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CheckEscRespHi	116	Covered	T1,T2,T3
CheckEscRespLo	136	Covered	T1,T2,T3
CheckPingResp0	118	Covered	T1,T2,T3
CheckPingResp1	145	Covered	T1,T2,T3
CheckPingResp2	157	Covered	T1,T2,T3
CheckPingResp3	169	Covered	T1,T2,T3
Idle	130	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
CheckEscRespHi->CheckEscRespLo	136	Covered	T1,T2,T3
CheckEscRespHi->Idle	138	Covered	T1,T2,T3
CheckEscRespLo->CheckEscRespHi	128	Covered	T1,T2,T3
CheckEscRespLo->Idle	130	Covered	T1,T3,T4
CheckPingResp0->CheckEscRespLo	149	Covered	T7,T9
CheckPingResp0->CheckPingResp1	145	Covered	T1,T2,T3
CheckPingResp0->Idle	152	Covered	T1,T2,T3
CheckPingResp1->CheckEscRespHi	161	Covered	T6,T8
CheckPingResp1->CheckPingResp2	157	Covered	T1,T2,T3
CheckPingResp1->Idle	164	Covered	T10,T7,T11
CheckPingResp2->CheckEscRespLo	173	Not Covered
CheckPingResp2->CheckPingResp3	169	Covered	T1,T2,T3
CheckPingResp2->Idle	176	Covered	T5,T12,T9
CheckPingResp3->CheckEscRespHi	185	Covered	T1,T4,T5
CheckPingResp3->Idle	181	Covered	T1,T2,T3
Idle->CheckEscRespHi	116	Covered	T1,T2,T3
Idle->CheckPingResp0	118	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_esc_sender

	Line No.	Total	Covered	Percent
Branches		28	23	82.14
CASE	112	22	17	77.27
IF	199	2	2	100.00
IF	206	2	2	100.00
IF	216	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	112	case (state_q)
-2-:	115	if (esc_req_i)
-3-:	117	if ((ping_req_d & (~ping_req_q)))
-4-:	122	if (resp)
-5-:	129	if (((!esc_tx_o.esc_p) || resp))
-6-:	137	if (((!esc_tx_o.esc_p) || (!resp)))
-7-:	148	if (esc_req_i)
-8-:	151	if ((!resp))
-9-:	160	if (esc_req_i)
-10-:	163	if (resp)
-11-:	172	if (esc_req_i)
-12-:	175	if ((!resp))
-13-:	184	if (esc_req_i)
-14-:	187	if (resp)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckEscRespLo	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
CheckEscRespLo	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckEscRespHi	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckEscRespHi	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckPingResp0	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T7,T9
CheckPingResp0	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
CheckPingResp0	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
CheckPingResp1	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T6,T8
CheckPingResp1	-	-	-	-	-	-	-	0	1	-	-	-	-	Not Covered
CheckPingResp1	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T3
CheckPingResp2	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
CheckPingResp2	-	-	-	-	-	-	-	-	-	0	1	-	-	Not Covered
CheckPingResp2	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T3
CheckPingResp3	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T4,T5
CheckPingResp3	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
CheckPingResp3	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	199	if (sigint_detected)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	if ((((esc_req_i || esc_req_q) || esc_req_q1) && ping_req_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	216	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_esc_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DiffEncCheck_A	9656	5236	0	0
EscCheck_A	9656	414	0	0
EscPKnownO_A	9656	5236	0	0
EscPingCheck_A	9656	36	0	0
IntegFailKnownO_A	9656	5236	0	0
PingCheck_A	9656	0	0	20
PingOkKnownO_A	9656	5236	0	0
SigIntBackCheck_A	9656	96	0	0
SigIntCheck0_A	9656	43	0	0
SigIntCheck1_A	9656	0	0	20
SigIntCheck2_A	9656	0	0	20
SigIntCheck3_A	9656	53	0	0
StateEscRespHiBackCheck_A	9656	254	0	0
StateEscRespHiCheck_A	9656	178	0	0
StateEscRespLoBackCheck_A	9656	198	0	0
StateEscRespLoCheck_A	9656	196	0	0

DiffEncCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	5236	0	0
T1	464	267	0	0
T2	471	264	0	0
T3	521	260	0	0
T4	481	274	0	0
T5	525	274	0	0
T6	506	242	0	0
T10	507	253	0	0
T12	460	271	0	0
T13	453	256	0	0
T14	479	264	0	0

EscCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	414	0	0
T1	464	31	0	0
T2	471	18	0	0
T3	521	26	0	0
T4	481	18	0	0
T5	525	30	0	0
T6	506	17	0	0
T10	507	21	0	0
T12	460	26	0	0
T13	453	12	0	0
T14	479	11	0	0

EscPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	5236	0	0
T1	464	267	0	0
T2	471	264	0	0
T3	521	260	0	0
T4	481	274	0	0
T5	525	274	0	0
T6	506	242	0	0
T10	507	253	0	0
T12	460	271	0	0
T13	453	256	0	0
T14	479	264	0	0

EscPingCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	36	0	0
T1	464	2	0	0
T2	471	2	0	0
T3	521	2	0	0
T4	481	2	0	0
T5	525	2	0	0
T6	506	1	0	0
T10	507	2	0	0
T12	460	2	0	0
T13	453	2	0	0
T14	479	2	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	5236	0	0
T1	464	267	0	0
T2	471	264	0	0
T3	521	260	0	0
T4	481	274	0	0
T5	525	274	0	0
T6	506	242	0	0
T10	507	253	0	0
T12	460	271	0	0
T13	453	256	0	0
T14	479	264	0	0

PingCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	0	0	20

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	5236	0	0
T1	464	267	0	0
T2	471	264	0	0
T3	521	260	0	0
T4	481	274	0	0
T5	525	274	0	0
T6	506	242	0	0
T10	507	253	0	0
T12	460	271	0	0
T13	453	256	0	0
T14	479	264	0	0

SigIntBackCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	96	0	0
T1	464	5	0	0
T2	471	5	0	0
T3	521	5	0	0
T4	481	5	0	0
T5	525	5	0	0
T6	506	4	0	0
T10	507	5	0	0
T12	460	5	0	0
T13	453	5	0	0
T14	479	4	0	0

SigIntCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	43	0	0
T1	464	2	0	0
T2	471	2	0	0
T3	521	2	0	0
T4	481	2	0	0
T5	525	2	0	0
T6	506	2	0	0
T10	507	2	0	0
T12	460	2	0	0
T13	453	2	0	0
T14	479	2	0	0

SigIntCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	0	0	20

SigIntCheck2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	0	0	20

SigIntCheck3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	53	0	0
T1	464	3	0	0
T2	471	3	0	0
T3	521	3	0	0
T4	481	3	0	0
T5	525	3	0	0
T6	506	2	0	0
T10	507	3	0	0
T12	460	3	0	0
T13	453	3	0	0
T14	479	2	0	0

StateEscRespHiBackCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	254	0	0
T1	464	18	0	0
T2	471	12	0	0
T3	521	15	0	0
T4	481	11	0	0
T5	525	17	0	0
T6	506	11	0	0
T10	507	13	0	0
T12	460	15	0	0
T13	453	9	0	0
T14	479	8	0	0

StateEscRespHiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	178	0	0
T1	464	14	0	0
T2	471	8	0	0
T3	521	11	0	0
T4	481	8	0	0
T5	525	13	0	0
T6	506	8	0	0
T10	507	9	0	0
T12	460	11	0	0
T13	453	5	0	0
T14	479	4	0	0

StateEscRespLoBackCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	198	0	0
T1	464	15	0	0
T2	471	8	0	0
T3	521	13	0	0
T4	481	9	0	0
T5	525	15	0	0
T6	506	8	0	0
T10	507	10	0	0
T12	460	13	0	0
T13	453	5	0	0
T14	479	5	0	0

StateEscRespLoCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9656	196	0	0
T1	464	15	0	0
T2	471	8	0	0
T3	521	13	0	0
T4	481	9	0	0
T5	525	15	0	0
T6	506	8	0	0
T10	507	10	0	0
T12	460	13	0	0
T13	453	5	0	0
T14	479	5	0	0