| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/10.prim_esc_test.3309021254 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/0.prim_esc_test.2453143599 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/1.prim_esc_test.2169920831 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/14.prim_esc_test.1769055272 |
| Name |
|---|
| /workspace/coverage/default/11.prim_esc_test.422874720 |
| /workspace/coverage/default/12.prim_esc_test.424530351 |
| /workspace/coverage/default/13.prim_esc_test.4279830015 |
| /workspace/coverage/default/15.prim_esc_test.1646938076 |
| /workspace/coverage/default/16.prim_esc_test.775939538 |
| /workspace/coverage/default/17.prim_esc_test.1232375744 |
| /workspace/coverage/default/18.prim_esc_test.2263640993 |
| /workspace/coverage/default/19.prim_esc_test.721845816 |
| /workspace/coverage/default/2.prim_esc_test.141111457 |
| /workspace/coverage/default/3.prim_esc_test.1812445928 |
| /workspace/coverage/default/4.prim_esc_test.3597381780 |
| /workspace/coverage/default/5.prim_esc_test.3736511885 |
| /workspace/coverage/default/6.prim_esc_test.1685027561 |
| /workspace/coverage/default/7.prim_esc_test.4113498830 |
| /workspace/coverage/default/8.prim_esc_test.2323937820 |
| /workspace/coverage/default/9.prim_esc_test.806684591 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_esc_test.4113498830 | Jul 30 04:26:09 PM PDT 24 | Jul 30 04:26:10 PM PDT 24 | 4784774 ps | ||
| T2 | /workspace/coverage/default/12.prim_esc_test.424530351 | Jul 30 04:26:13 PM PDT 24 | Jul 30 04:26:13 PM PDT 24 | 5364525 ps | ||
| T3 | /workspace/coverage/default/1.prim_esc_test.2169920831 | Jul 30 04:26:03 PM PDT 24 | Jul 30 04:26:04 PM PDT 24 | 5265820 ps | ||
| T16 | /workspace/coverage/default/18.prim_esc_test.2263640993 | Jul 30 04:26:09 PM PDT 24 | Jul 30 04:26:10 PM PDT 24 | 4693722 ps | ||
| T7 | /workspace/coverage/default/2.prim_esc_test.141111457 | Jul 30 04:26:03 PM PDT 24 | Jul 30 04:26:04 PM PDT 24 | 4629616 ps | ||
| T4 | /workspace/coverage/default/10.prim_esc_test.3309021254 | Jul 30 04:26:13 PM PDT 24 | Jul 30 04:26:13 PM PDT 24 | 5047433 ps | ||
| T5 | /workspace/coverage/default/9.prim_esc_test.806684591 | Jul 30 04:26:03 PM PDT 24 | Jul 30 04:26:04 PM PDT 24 | 5249634 ps | ||
| T14 | /workspace/coverage/default/15.prim_esc_test.1646938076 | Jul 30 04:26:13 PM PDT 24 | Jul 30 04:26:13 PM PDT 24 | 5080975 ps | ||
| T10 | /workspace/coverage/default/5.prim_esc_test.3736511885 | Jul 30 04:26:09 PM PDT 24 | Jul 30 04:26:10 PM PDT 24 | 4997621 ps | ||
| T8 | /workspace/coverage/default/17.prim_esc_test.1232375744 | Jul 30 04:26:00 PM PDT 24 | Jul 30 04:26:01 PM PDT 24 | 4482251 ps | ||
| T13 | /workspace/coverage/default/14.prim_esc_test.1769055272 | Jul 30 04:26:11 PM PDT 24 | Jul 30 04:26:11 PM PDT 24 | 5211161 ps | ||
| T6 | /workspace/coverage/default/19.prim_esc_test.721845816 | Jul 30 04:26:13 PM PDT 24 | Jul 30 04:26:13 PM PDT 24 | 4637182 ps | ||
| T11 | /workspace/coverage/default/0.prim_esc_test.2453143599 | Jul 30 04:26:03 PM PDT 24 | Jul 30 04:26:04 PM PDT 24 | 4864286 ps | ||
| T15 | /workspace/coverage/default/16.prim_esc_test.775939538 | Jul 30 04:26:00 PM PDT 24 | Jul 30 04:26:01 PM PDT 24 | 4429658 ps | ||
| T12 | /workspace/coverage/default/11.prim_esc_test.422874720 | Jul 30 04:26:11 PM PDT 24 | Jul 30 04:26:12 PM PDT 24 | 4612469 ps | ||
| T17 | /workspace/coverage/default/3.prim_esc_test.1812445928 | Jul 30 04:26:11 PM PDT 24 | Jul 30 04:26:11 PM PDT 24 | 4958436 ps | ||
| T18 | /workspace/coverage/default/8.prim_esc_test.2323937820 | Jul 30 04:26:09 PM PDT 24 | Jul 30 04:26:10 PM PDT 24 | 5213574 ps | ||
| T19 | /workspace/coverage/default/6.prim_esc_test.1685027561 | Jul 30 04:25:57 PM PDT 24 | Jul 30 04:25:57 PM PDT 24 | 4748645 ps | ||
| T9 | /workspace/coverage/default/4.prim_esc_test.3597381780 | Jul 30 04:26:03 PM PDT 24 | Jul 30 04:26:04 PM PDT 24 | 4611661 ps | ||
| T20 | /workspace/coverage/default/13.prim_esc_test.4279830015 | Jul 30 04:26:09 PM PDT 24 | Jul 30 04:26:10 PM PDT 24 | 4655233 ps |
| Test location | /workspace/coverage/default/10.prim_esc_test.3309021254 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5047433 ps |
| CPU time | 0.45 seconds |
| Started | Jul 30 04:26:13 PM PDT 24 |
| Finished | Jul 30 04:26:13 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-fc8d7b69-649c-447d-9516-b08bcb4314d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309021254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3309021254 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2453143599 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4864286 ps |
| CPU time | 0.51 seconds |
| Started | Jul 30 04:26:03 PM PDT 24 |
| Finished | Jul 30 04:26:04 PM PDT 24 |
| Peak memory | 144108 kb |
| Host | smart-f951b1cd-baae-4913-aeaf-7d9e8b048d1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2453143599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2453143599 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2169920831 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5265820 ps |
| CPU time | 0.5 seconds |
| Started | Jul 30 04:26:03 PM PDT 24 |
| Finished | Jul 30 04:26:04 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-ba4568e8-899b-48ef-ac62-e3517b8bd050 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2169920831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2169920831 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1769055272 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5211161 ps |
| CPU time | 0.4 seconds |
| Started | Jul 30 04:26:11 PM PDT 24 |
| Finished | Jul 30 04:26:11 PM PDT 24 |
| Peak memory | 146008 kb |
| Host | smart-e0087c6b-1aef-492c-928e-c068d2f8ec72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769055272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1769055272 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.422874720 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4612469 ps |
| CPU time | 0.37 seconds |
| Started | Jul 30 04:26:11 PM PDT 24 |
| Finished | Jul 30 04:26:12 PM PDT 24 |
| Peak memory | 145976 kb |
| Host | smart-76eb43e0-a124-4070-aa68-f35a924da422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422874720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.422874720 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.424530351 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5364525 ps |
| CPU time | 0.48 seconds |
| Started | Jul 30 04:26:13 PM PDT 24 |
| Finished | Jul 30 04:26:13 PM PDT 24 |
| Peak memory | 144404 kb |
| Host | smart-fa9b3eb3-8658-4077-b3f3-275842a3de5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=424530351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.424530351 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.4279830015 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4655233 ps |
| CPU time | 0.38 seconds |
| Started | Jul 30 04:26:09 PM PDT 24 |
| Finished | Jul 30 04:26:10 PM PDT 24 |
| Peak memory | 145884 kb |
| Host | smart-53c641da-3894-46b3-a8f5-4d2dd3b0d89e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279830015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4279830015 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1646938076 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5080975 ps |
| CPU time | 0.47 seconds |
| Started | Jul 30 04:26:13 PM PDT 24 |
| Finished | Jul 30 04:26:13 PM PDT 24 |
| Peak memory | 145324 kb |
| Host | smart-7534ff0b-f00a-4cf9-ac96-af181b429cf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646938076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1646938076 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.775939538 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4429658 ps |
| CPU time | 0.45 seconds |
| Started | Jul 30 04:26:00 PM PDT 24 |
| Finished | Jul 30 04:26:01 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-d39fe2d5-aca1-4a15-b366-9ef3a7a254c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775939538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.775939538 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1232375744 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4482251 ps |
| CPU time | 0.45 seconds |
| Started | Jul 30 04:26:00 PM PDT 24 |
| Finished | Jul 30 04:26:01 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-b84936e5-c4a2-41ac-9d28-f89b5ca34d42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232375744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1232375744 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2263640993 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4693722 ps |
| CPU time | 0.41 seconds |
| Started | Jul 30 04:26:09 PM PDT 24 |
| Finished | Jul 30 04:26:10 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-9702c3a6-6dba-4026-b86c-cda1b8615658 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2263640993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2263640993 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.721845816 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4637182 ps |
| CPU time | 0.46 seconds |
| Started | Jul 30 04:26:13 PM PDT 24 |
| Finished | Jul 30 04:26:13 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-5cc27bb8-ac81-443b-9515-811beaa6f767 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=721845816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.721845816 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.141111457 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4629616 ps |
| CPU time | 0.52 seconds |
| Started | Jul 30 04:26:03 PM PDT 24 |
| Finished | Jul 30 04:26:04 PM PDT 24 |
| Peak memory | 144708 kb |
| Host | smart-6de522fd-aec4-479e-bb97-e1913bf7ebcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=141111457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.141111457 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1812445928 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4958436 ps |
| CPU time | 0.44 seconds |
| Started | Jul 30 04:26:11 PM PDT 24 |
| Finished | Jul 30 04:26:11 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-234d4638-6ded-4401-98a4-205950740ba5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812445928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1812445928 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3597381780 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4611661 ps |
| CPU time | 0.48 seconds |
| Started | Jul 30 04:26:03 PM PDT 24 |
| Finished | Jul 30 04:26:04 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-44c920bf-930d-4bc7-929d-f13373fa9f55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3597381780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3597381780 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3736511885 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4997621 ps |
| CPU time | 0.43 seconds |
| Started | Jul 30 04:26:09 PM PDT 24 |
| Finished | Jul 30 04:26:10 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-1604dfab-ec82-4fac-bf8f-5edfae9e3890 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736511885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3736511885 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1685027561 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4748645 ps |
| CPU time | 0.5 seconds |
| Started | Jul 30 04:25:57 PM PDT 24 |
| Finished | Jul 30 04:25:57 PM PDT 24 |
| Peak memory | 146716 kb |
| Host | smart-c6660876-da2d-42d9-9795-bbc37e6b5645 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685027561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1685027561 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4113498830 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4784774 ps |
| CPU time | 0.42 seconds |
| Started | Jul 30 04:26:09 PM PDT 24 |
| Finished | Jul 30 04:26:10 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-9631c0e4-e78e-44e4-833b-eb86f0399471 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113498830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4113498830 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2323937820 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5213574 ps |
| CPU time | 0.4 seconds |
| Started | Jul 30 04:26:09 PM PDT 24 |
| Finished | Jul 30 04:26:10 PM PDT 24 |
| Peak memory | 145688 kb |
| Host | smart-af4ba5fb-b031-4ca5-a4a6-842180902229 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323937820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2323937820 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.806684591 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5249634 ps |
| CPU time | 0.49 seconds |
| Started | Jul 30 04:26:03 PM PDT 24 |
| Finished | Jul 30 04:26:04 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-716b4f35-0418-481a-aeea-d47197002f38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806684591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.806684591 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |