| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.74 | 87.74 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/16.prim_esc_test.1801637545 |
| 90.05 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/5.prim_esc_test.3066659227 |
| 91.17 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/1.prim_esc_test.604708974 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/11.prim_esc_test.3915035741 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1130636606 |
| /workspace/coverage/default/10.prim_esc_test.3302863120 |
| /workspace/coverage/default/12.prim_esc_test.647555806 |
| /workspace/coverage/default/13.prim_esc_test.3840159553 |
| /workspace/coverage/default/14.prim_esc_test.3625254576 |
| /workspace/coverage/default/15.prim_esc_test.263777741 |
| /workspace/coverage/default/17.prim_esc_test.3154630934 |
| /workspace/coverage/default/18.prim_esc_test.3692043650 |
| /workspace/coverage/default/19.prim_esc_test.1813649984 |
| /workspace/coverage/default/2.prim_esc_test.2878754656 |
| /workspace/coverage/default/3.prim_esc_test.1815158201 |
| /workspace/coverage/default/4.prim_esc_test.2592415819 |
| /workspace/coverage/default/6.prim_esc_test.1244003232 |
| /workspace/coverage/default/7.prim_esc_test.2350465956 |
| /workspace/coverage/default/8.prim_esc_test.3392786735 |
| /workspace/coverage/default/9.prim_esc_test.1851433933 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_esc_test.2350465956 | Aug 04 04:23:58 PM PDT 24 | Aug 04 04:23:59 PM PDT 24 | 5059644 ps | ||
| T2 | /workspace/coverage/default/15.prim_esc_test.263777741 | Aug 04 04:25:31 PM PDT 24 | Aug 04 04:25:31 PM PDT 24 | 5137721 ps | ||
| T3 | /workspace/coverage/default/3.prim_esc_test.1815158201 | Aug 04 04:20:36 PM PDT 24 | Aug 04 04:20:37 PM PDT 24 | 4925689 ps | ||
| T4 | /workspace/coverage/default/5.prim_esc_test.3066659227 | Aug 04 04:20:34 PM PDT 24 | Aug 04 04:20:35 PM PDT 24 | 4657657 ps | ||
| T7 | /workspace/coverage/default/19.prim_esc_test.1813649984 | Aug 04 04:20:32 PM PDT 24 | Aug 04 04:20:33 PM PDT 24 | 4656706 ps | ||
| T6 | /workspace/coverage/default/2.prim_esc_test.2878754656 | Aug 04 04:25:31 PM PDT 24 | Aug 04 04:25:32 PM PDT 24 | 5024717 ps | ||
| T11 | /workspace/coverage/default/9.prim_esc_test.1851433933 | Aug 04 04:20:37 PM PDT 24 | Aug 04 04:20:37 PM PDT 24 | 4861167 ps | ||
| T13 | /workspace/coverage/default/17.prim_esc_test.3154630934 | Aug 04 04:20:39 PM PDT 24 | Aug 04 04:20:39 PM PDT 24 | 4441273 ps | ||
| T8 | /workspace/coverage/default/16.prim_esc_test.1801637545 | Aug 04 04:20:33 PM PDT 24 | Aug 04 04:20:33 PM PDT 24 | 5386912 ps | ||
| T14 | /workspace/coverage/default/0.prim_esc_test.1130636606 | Aug 04 04:20:36 PM PDT 24 | Aug 04 04:20:37 PM PDT 24 | 4551893 ps | ||
| T15 | /workspace/coverage/default/6.prim_esc_test.1244003232 | Aug 04 04:23:58 PM PDT 24 | Aug 04 04:23:59 PM PDT 24 | 5252394 ps | ||
| T12 | /workspace/coverage/default/11.prim_esc_test.3915035741 | Aug 04 04:23:57 PM PDT 24 | Aug 04 04:23:58 PM PDT 24 | 4798459 ps | ||
| T9 | /workspace/coverage/default/8.prim_esc_test.3392786735 | Aug 04 04:20:35 PM PDT 24 | Aug 04 04:20:35 PM PDT 24 | 5386718 ps | ||
| T10 | /workspace/coverage/default/1.prim_esc_test.604708974 | Aug 04 04:25:31 PM PDT 24 | Aug 04 04:25:32 PM PDT 24 | 5018679 ps | ||
| T16 | /workspace/coverage/default/4.prim_esc_test.2592415819 | Aug 04 04:20:36 PM PDT 24 | Aug 04 04:20:37 PM PDT 24 | 5600926 ps | ||
| T17 | /workspace/coverage/default/18.prim_esc_test.3692043650 | Aug 04 04:20:36 PM PDT 24 | Aug 04 04:20:37 PM PDT 24 | 4989380 ps | ||
| T5 | /workspace/coverage/default/10.prim_esc_test.3302863120 | Aug 04 04:25:30 PM PDT 24 | Aug 04 04:25:32 PM PDT 24 | 5435590 ps | ||
| T18 | /workspace/coverage/default/12.prim_esc_test.647555806 | Aug 04 04:20:36 PM PDT 24 | Aug 04 04:20:37 PM PDT 24 | 5049520 ps | ||
| T19 | /workspace/coverage/default/14.prim_esc_test.3625254576 | Aug 04 04:20:32 PM PDT 24 | Aug 04 04:20:32 PM PDT 24 | 5236606 ps | ||
| T20 | /workspace/coverage/default/13.prim_esc_test.3840159553 | Aug 04 04:25:34 PM PDT 24 | Aug 04 04:25:34 PM PDT 24 | 5074810 ps |
| Test location | /workspace/coverage/default/16.prim_esc_test.1801637545 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5386912 ps |
| CPU time | 0.39 seconds |
| Started | Aug 04 04:20:33 PM PDT 24 |
| Finished | Aug 04 04:20:33 PM PDT 24 |
| Peak memory | 146628 kb |
| Host | smart-b36bdaa1-1006-4d10-b7ed-989125a3d62b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1801637545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1801637545 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3066659227 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4657657 ps |
| CPU time | 0.4 seconds |
| Started | Aug 04 04:20:34 PM PDT 24 |
| Finished | Aug 04 04:20:35 PM PDT 24 |
| Peak memory | 146632 kb |
| Host | smart-2dad543b-de5b-4b1b-a4e6-30283a25dcc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3066659227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3066659227 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.604708974 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5018679 ps |
| CPU time | 0.36 seconds |
| Started | Aug 04 04:25:31 PM PDT 24 |
| Finished | Aug 04 04:25:32 PM PDT 24 |
| Peak memory | 146812 kb |
| Host | smart-9eb00b46-7eea-40fa-96ed-c06dbe84ae33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=604708974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.604708974 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3915035741 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4798459 ps |
| CPU time | 0.37 seconds |
| Started | Aug 04 04:23:57 PM PDT 24 |
| Finished | Aug 04 04:23:58 PM PDT 24 |
| Peak memory | 146372 kb |
| Host | smart-acea3dd3-2d86-4787-8b29-1c3ab1828f83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915035741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3915035741 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1130636606 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4551893 ps |
| CPU time | 0.38 seconds |
| Started | Aug 04 04:20:36 PM PDT 24 |
| Finished | Aug 04 04:20:37 PM PDT 24 |
| Peak memory | 146164 kb |
| Host | smart-f5b122a8-a59b-44c0-85e2-747317b6bd09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130636606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1130636606 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3302863120 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5435590 ps |
| CPU time | 0.41 seconds |
| Started | Aug 04 04:25:30 PM PDT 24 |
| Finished | Aug 04 04:25:32 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-cefe8173-e65b-4ab6-ad20-67ab06cfb3bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302863120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3302863120 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.647555806 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5049520 ps |
| CPU time | 0.4 seconds |
| Started | Aug 04 04:20:36 PM PDT 24 |
| Finished | Aug 04 04:20:37 PM PDT 24 |
| Peak memory | 146068 kb |
| Host | smart-e4ce342f-19c4-469b-ab39-a5ed9be1532e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647555806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.647555806 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3840159553 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5074810 ps |
| CPU time | 0.38 seconds |
| Started | Aug 04 04:25:34 PM PDT 24 |
| Finished | Aug 04 04:25:34 PM PDT 24 |
| Peak memory | 146036 kb |
| Host | smart-922bed9d-c12d-42fc-a0ab-5bce11ad44d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840159553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3840159553 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3625254576 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5236606 ps |
| CPU time | 0.41 seconds |
| Started | Aug 04 04:20:32 PM PDT 24 |
| Finished | Aug 04 04:20:32 PM PDT 24 |
| Peak memory | 146100 kb |
| Host | smart-bb6320ce-1fa5-42ba-a69a-13b27fab0058 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625254576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3625254576 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.263777741 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5137721 ps |
| CPU time | 0.36 seconds |
| Started | Aug 04 04:25:31 PM PDT 24 |
| Finished | Aug 04 04:25:31 PM PDT 24 |
| Peak memory | 145440 kb |
| Host | smart-ad863196-6c00-46d8-9562-28aae56310f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=263777741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.263777741 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3154630934 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4441273 ps |
| CPU time | 0.38 seconds |
| Started | Aug 04 04:20:39 PM PDT 24 |
| Finished | Aug 04 04:20:39 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-e4592cb9-296e-4da9-8708-98d79afd1100 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3154630934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3154630934 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3692043650 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4989380 ps |
| CPU time | 0.39 seconds |
| Started | Aug 04 04:20:36 PM PDT 24 |
| Finished | Aug 04 04:20:37 PM PDT 24 |
| Peak memory | 146136 kb |
| Host | smart-266d427a-10e4-4ba3-9373-6921a36c6d24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692043650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3692043650 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1813649984 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4656706 ps |
| CPU time | 0.39 seconds |
| Started | Aug 04 04:20:32 PM PDT 24 |
| Finished | Aug 04 04:20:33 PM PDT 24 |
| Peak memory | 146628 kb |
| Host | smart-44e7647d-4eef-4f70-bc7c-d83b4d6c7c03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1813649984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1813649984 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2878754656 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5024717 ps |
| CPU time | 0.4 seconds |
| Started | Aug 04 04:25:31 PM PDT 24 |
| Finished | Aug 04 04:25:32 PM PDT 24 |
| Peak memory | 146324 kb |
| Host | smart-460d9236-ddde-4092-a1e5-d64b277a50b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878754656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2878754656 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1815158201 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4925689 ps |
| CPU time | 0.4 seconds |
| Started | Aug 04 04:20:36 PM PDT 24 |
| Finished | Aug 04 04:20:37 PM PDT 24 |
| Peak memory | 146172 kb |
| Host | smart-a0208e3e-7bbe-49db-8702-67e6869e56a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815158201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1815158201 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2592415819 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5600926 ps |
| CPU time | 0.4 seconds |
| Started | Aug 04 04:20:36 PM PDT 24 |
| Finished | Aug 04 04:20:37 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-5fabf8e1-8bb4-4268-853a-5fb76c3f183a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2592415819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2592415819 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1244003232 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5252394 ps |
| CPU time | 0.4 seconds |
| Started | Aug 04 04:23:58 PM PDT 24 |
| Finished | Aug 04 04:23:59 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-33d6503a-713f-4dab-801e-dc508b51b6f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244003232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1244003232 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2350465956 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5059644 ps |
| CPU time | 0.39 seconds |
| Started | Aug 04 04:23:58 PM PDT 24 |
| Finished | Aug 04 04:23:59 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-ed6d828f-9cc7-404d-b418-e56c857f0e69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350465956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2350465956 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3392786735 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5386718 ps |
| CPU time | 0.41 seconds |
| Started | Aug 04 04:20:35 PM PDT 24 |
| Finished | Aug 04 04:20:35 PM PDT 24 |
| Peak memory | 146632 kb |
| Host | smart-12127483-fd6f-45e3-8fbb-38e630c311ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392786735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3392786735 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1851433933 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4861167 ps |
| CPU time | 0.41 seconds |
| Started | Aug 04 04:20:37 PM PDT 24 |
| Finished | Aug 04 04:20:37 PM PDT 24 |
| Peak memory | 146108 kb |
| Host | smart-395492c3-a752-4276-a9e3-9444dee4a02a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851433933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1851433933 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |