Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_esc_tb.i_esc_receiver	94.60	100.00	91.67	100.00	90.91	94.12	90.91

---

Module Instance : prim_esc_tb.i_esc_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_esc_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
TOTAL		50	50	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	133	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
ALWAYS	172	39	39	100.00
ALWAYS	252	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
99	1	1
100	1	1
131	1	1
133	1	1
134	1	1
136	1	1
167	1	1
168	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
178	1	1
181	1	1
182	1	1
183	1	1
184	1	1
			MISSING_ELSE
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE
252	1	1
253	1	1
255	1	1

---

Cond Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (ping_en && ((!(&timeout_cnt))))
             ---1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (esc_req || ((&timeout_cnt)) || timeout_cnt_error)
             ---1---    --------2-------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (sigint_detected && (state_q != SigInt))
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 SUB-EXPRESSION (state_q != SigInt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_esc_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Check	182	Covered	T1,T2,T3
EscResp	194	Covered	T1,T2,T3
Idle	201	Covered	T1,T2,T3
PingResp	190	Covered	T1,T2,T3
SigInt	230	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Check->EscResp	194	Covered	T1,T2,T3
Check->PingResp	190	Covered	T1,T2,T3
Check->SigInt	240	Covered	T2,T7,T12
EscResp->Idle	213	Covered	T1,T2,T3
EscResp->SigInt	240	Covered	T1,T3,T4
Idle->Check	182	Covered	T1,T2,T3
Idle->SigInt	240	Covered	T1,T2,T3
PingResp->EscResp	206	Covered	T10,T8,T13
PingResp->Idle	201	Covered	T1,T2,T3
PingResp->SigInt	240	Not Covered
SigInt->Idle	227	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
Branches		17	16	94.12
IF	133	2	2	100.00
CASE	178	11	10	90.91
IF	239	2	2	100.00
IF	252	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv' or '../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	133	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (state_q)
-2-:	181	if (esc_level)
-3-:	193	if (esc_level)
-4-:	205	if (esc_level)
-5-:	214	if (esc_level)
-6-:	229	if (sigint_detected)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
Idle	1	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	Covered	T1,T2,T3
Check	-	1	-	-	-	Covered	T1,T2,T3
Check	-	0	-	-	-	Covered	T1,T2,T3
PingResp	-	-	1	-	-	Covered	T10,T8,T13
PingResp	-	-	0	-	-	Covered	T1,T2,T3
EscResp	-	-	-	1	-	Covered	T1,T2,T3
EscResp	-	-	-	0	-	Covered	T1,T2,T3
SigInt	-	-	-	-	1	Covered	T1,T2,T3
SigInt	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	239	if ((sigint_detected && (state_q != SigInt)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	252	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_esc_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DiffEncCheck_A	9888	5174	0	0
EscCntEsc_A	9888	20	0	0
EscCntWrap_A	9888	0	0	0
EscEnCheck_A	9888	348	0	0
EscEnKnownO_A	9888	5274	0	0
EscRespCheck_A	9888	368	0	20
PingRespCheck_A	9888	54	0	20
RespPKnownO_A	9888	5274	0	0
SigIntCheck0_A	9888	40	0	0
SigIntCheck1_A	9888	40	0	0
SigIntCheck2_A	9888	40	0	0

DiffEncCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	5174	0	0
T1	457	230	0	0
T2	486	239	0	0
T3	480	260	0	0
T4	534	264	0	0
T5	524	252	0	0
T6	501	271	0	0
T10	485	250	0	0
T11	466	245	0	0
T14	548	285	0	0
T15	468	290	0	0

EscCntEsc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	20	0	0
T1	457	1	0	0
T2	486	1	0	0
T3	480	1	0	0
T4	534	1	0	0
T5	524	1	0	0
T6	501	1	0	0
T10	485	1	0	0
T11	466	1	0	0
T14	548	1	0	0
T15	468	1	0	0

EscCntWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	0	0	0

EscEnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	348	0	0
T1	457	14	0	0
T2	486	18	0	0
T3	480	15	0	0
T4	534	16	0	0
T5	524	9	0	0
T6	501	25	0	0
T10	485	12	0	0
T11	466	25	0	0
T14	548	25	0	0
T15	468	12	0	0

EscEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	5274	0	0
T1	457	235	0	0
T2	486	244	0	0
T3	480	265	0	0
T4	534	269	0	0
T5	524	257	0	0
T6	501	276	0	0
T10	485	255	0	0
T11	466	250	0	0
T14	548	290	0	0
T15	468	295	0	0

EscRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	368	0	20
T1	457	15	0	1
T2	486	19	0	1
T3	480	16	0	1
T4	534	17	0	1
T5	524	10	0	1
T6	501	26	0	1
T10	485	13	0	1
T11	466	26	0	1
T14	548	26	0	1
T15	468	13	0	1

PingRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	54	0	20
T1	457	3	0	1
T2	486	3	0	1
T3	480	2	0	1
T4	534	3	0	1
T5	524	3	0	1
T6	501	2	0	1
T10	485	2	0	1
T11	466	3	0	1
T14	548	3	0	1
T15	468	3	0	1

RespPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	5274	0	0
T1	457	235	0	0
T2	486	244	0	0
T3	480	265	0	0
T4	534	269	0	0
T5	524	257	0	0
T6	501	276	0	0
T10	485	255	0	0
T11	466	250	0	0
T14	548	290	0	0
T15	468	295	0	0

SigIntCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	40	0	0
T1	457	2	0	0
T2	486	2	0	0
T3	480	2	0	0
T4	534	2	0	0
T5	524	2	0	0
T6	501	2	0	0
T10	485	2	0	0
T11	466	2	0	0
T14	548	2	0	0
T15	468	2	0	0

SigIntCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	40	0	0
T1	457	2	0	0
T2	486	2	0	0
T3	480	2	0	0
T4	534	2	0	0
T5	524	2	0	0
T6	501	2	0	0
T10	485	2	0	0
T11	466	2	0	0
T14	548	2	0	0
T15	468	2	0	0

SigIntCheck2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9888	40	0	0
T1	457	2	0	0
T2	486	2	0	0
T3	480	2	0	0
T4	534	2	0	0
T5	524	2	0	0
T6	501	2	0	0
T10	485	2	0	0
T11	466	2	0	0
T14	548	2	0	0
T15	468	2	0	0