Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_esc_tb.i_esc_receiver	94.60	100.00	91.67	100.00	90.91	94.12	90.91

---

Module Instance : prim_esc_tb.i_esc_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.60	100.00	91.67	100.00	90.91	94.12	90.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_esc_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
TOTAL		50	50	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
ALWAYS	133	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
ALWAYS	172	39	39	100.00
ALWAYS	252	3	3	100.00

98                        logic [TimeoutCntDw-1:0] timeout_cnt;
99         1/1            assign timeout_cnt_set = (ping_en && !(&timeout_cnt));
           Tests:       T1 T2 T3 
100        1/1            assign timeout_cnt_en = (timeout_cnt > '0);
           Tests:       T1 T2 T3 
101                     
102                       prim_count #(
103                         .Width(TimeoutCntDw),
104                         // The escalation receiver behaves differently than other comportable IP. I.e., instead of
105                         // sending out an alert signal, this condition is handled internally in the alert handler.
106                         .EnableAlertTriggerSVA(0),
107                         // Pass a parameter to disable coverage for some assertions that are unreachable because
108                         // clr_i and decr_en_i are tied to zero.
109                         .PossibleActions(prim_count_pkg::Set | prim_count_pkg::Incr)
110                       ) u_prim_count (
111                         .clk_i,
112                         .rst_ni,
113                         .clr_i(1'b0),
114                         .set_i(timeout_cnt_set),
115                         .set_cnt_i(TimeoutCntDw'(1)),
116                         .incr_en_i(timeout_cnt_en),
117                         .decr_en_i(1'b0),
118                         .step_i(TimeoutCntDw'(1)),
119                         .commit_i(1'b1),
120                         .cnt_o(timeout_cnt),
121                         .cnt_after_commit_o(),
122                         .err_o(timeout_cnt_error)
123                       );
124                     
125                       // Escalation is asserted if
126                       // - requested via the escalation sender/receiver path,
127                       // - the ping monitor timeout is reached,
128                       // - the two ping monitor counters are in an inconsistent state.
129                       // Register the escalation request to avoid potential CDC issues downstream.
130                       logic esc_req, esc_req_d, esc_req_q;
131        1/1            assign esc_req_d = esc_req || (&timeout_cnt) || timeout_cnt_error;
           Tests:       T1 T2 T3 
132                       always_ff @(posedge clk_i or negedge rst_ni) begin
133        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
134        1/1                esc_req_q <= 1'b0;
           Tests:       T1 T2 T3 
135                         end else begin
136        1/1                esc_req_q <= esc_req_d;
           Tests:       T1 T2 T3 
137                         end
138                       end
139                     
140                       prim_sec_anchor_buf #(
141                         .Width(1)
142                       ) u_prim_buf_esc_req (
143                         .in_i (esc_req_q),
144                         .out_o(esc_req_o)
145                       );
146                     
147                       /////////////////
148                       // RX/TX Logic //
149                       /////////////////
150                     
151                       typedef enum logic [2:0] {Idle, Check, PingResp, EscResp, SigInt} state_e;
152                       state_e state_d, state_q;
153                       logic resp_pd, resp_pq;
154                       logic resp_nd, resp_nq;
155                     
156                       // This prevents further tool optimizations of the differential signal.
157                       prim_sec_anchor_flop #(
158                         .Width(2),
159                         .ResetValue(2'b10)
160                       ) u_prim_flop_esc (
161                         .clk_i,
162                         .rst_ni,
163                         .d_i({resp_nd, resp_pd}),
164                         .q_o({resp_nq, resp_pq})
165                       );
166                     
167        1/1            assign esc_rx_o.resp_p = resp_pq;
           Tests:       T1 T2 T3 
168        1/1            assign esc_rx_o.resp_n = resp_nq;
           Tests:       T1 T2 T3 
169                     
170                       always_comb begin : p_fsm
171                         // default
172        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
173        1/1              resp_pd = 1'b0;
           Tests:       T1 T2 T3 
174        1/1              resp_nd = 1'b1;
           Tests:       T1 T2 T3 
175        1/1              esc_req = 1'b0;
           Tests:       T1 T2 T3 
176        1/1              ping_en = 1'b0;
           Tests:       T1 T2 T3 
177                     
178        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
179                           // wait for the esc_p/n diff pair
180                           Idle: begin
181        1/1                  if (esc_level) begin
           Tests:       T1 T2 T3 
182        1/1                    state_d = Check;
           Tests:       T1 T2 T3 
183        1/1                    resp_pd = ~resp_pq;
           Tests:       T1 T2 T3 
184        1/1                    resp_nd = resp_pq;
           Tests:       T1 T2 T3 
185                             end
                        MISSING_ELSE
186                           end
187                           // we decide here whether this is only a ping request or
188                           // whether this is an escalation enable
189                           Check: begin
190        1/1                  state_d = PingResp;
           Tests:       T1 T2 T3 
191        1/1                  resp_pd = ~resp_pq;
           Tests:       T1 T2 T3 
192        1/1                  resp_nd = resp_pq;
           Tests:       T1 T2 T3 
193        1/1                  if (esc_level) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = EscResp;
           Tests:       T1 T2 T3 
195        1/1                    esc_req = 1'b1;
           Tests:       T1 T2 T3 
196                             end
                        MISSING_ELSE
197                           end
198                           // finish ping response. in case esc_level is again asserted,
199                           // we got an escalation signal (pings cannot occur back to back)
200                           PingResp: begin
201        1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
202        1/1                  resp_pd = ~resp_pq;
           Tests:       T1 T2 T3 
203        1/1                  resp_nd = resp_pq;
           Tests:       T1 T2 T3 
204        1/1                  ping_en = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  if (esc_level) begin
           Tests:       T1 T2 T3 
206        1/1                    state_d = EscResp;
           Tests:       T10 T6 T7 
207        1/1                    esc_req = 1'b1;
           Tests:       T10 T6 T7 
208                             end
                        MISSING_ELSE
209                           end
210                           // we have got an escalation enable pulse,
211                           // keep on toggling the outputs
212                           EscResp: begin
213        1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
214        1/1                  if (esc_level) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = EscResp;
           Tests:       T1 T2 T3 
216        1/1                    resp_pd = ~resp_pq;
           Tests:       T1 T2 T3 
217        1/1                    resp_nd = resp_pq;
           Tests:       T1 T2 T3 
218        1/1                    esc_req = 1'b1;
           Tests:       T1 T2 T3 
219                             end
                        MISSING_ELSE
220                           end
221                           // we have a signal integrity issue at one of
222                           // the incoming diff pairs. this condition is
223                           // signalled to the sender by setting the resp
224                           // diffpair to the same value and continuously
225                           // toggling them.
226                           SigInt: begin
227        1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
228        1/1                  esc_req = 1'b1;
           Tests:       T1 T2 T3 
229        1/1                  if (sigint_detected) begin
           Tests:       T1 T2 T3 
230        1/1                    state_d = SigInt;
           Tests:       T1 T2 T3 
231        1/1                    resp_pd = ~resp_pq;
           Tests:       T1 T2 T3 
232        1/1                    resp_nd = ~resp_pq;
           Tests:       T1 T2 T3 
233                             end
                        MISSING_ELSE
234                           end
235                           default: state_d = Idle;
236                         endcase
237                     
238                         // bail out if a signal integrity issue has been detected
239        1/1              if (sigint_detected && (state_q != SigInt)) begin
           Tests:       T1 T2 T3 
240        1/1                state_d = SigInt;
           Tests:       T1 T2 T3 
241        1/1                resp_pd = 1'b0;
           Tests:       T1 T2 T3 
242        1/1                resp_nd = 1'b0;
           Tests:       T1 T2 T3 
243                         end
                        MISSING_ELSE
244                       end
245                     
246                     
247                       ///////////////
248                       // Registers //
249                       ///////////////
250                     
251                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
252        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
253        1/1                state_q <= Idle;
           Tests:       T1 T2 T3 
254                         end else begin
255        1/1                state_q <= state_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (ping_en && ((!(&timeout_cnt))))
             ---1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (esc_req || ((&timeout_cnt)) || timeout_cnt_error)
             ---1---    --------2-------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       239
 EXPRESSION (sigint_detected && (state_q != SigInt))
             -------1-------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       239
 SUB-EXPRESSION (state_q != SigInt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	14	14	100.00
Total Bits 0->1	7	7	100.00
Total Bits 1->0	7	7	100.00

Ports	7	7	100.00
Port Bits	14	14	100.00
Port Bits 0->1	7	7	100.00
Port Bits 1->0	7	7	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

---

FSM Coverage for Module : prim_esc_receiver

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Check	182	Covered	T1,T2,T3
EscResp	194	Covered	T1,T2,T3
Idle	201	Covered	T1,T2,T3
PingResp	190	Covered	T1,T2,T3
SigInt	230	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
Check->EscResp	194	Covered	T1,T2,T3
Check->PingResp	190	Covered	T1,T2,T3
Check->SigInt	240	Covered	T2,T10,T6
EscResp->Idle	213	Covered	T1,T2,T3
EscResp->SigInt	240	Covered	T1,T3,T12
Idle->Check	182	Covered	T1,T2,T3
Idle->SigInt	240	Covered	T1,T2,T3
PingResp->EscResp	206	Covered	T10,T6,T7
PingResp->Idle	201	Covered	T1,T2,T3
PingResp->SigInt	240	Not Covered
SigInt->Idle	227	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_esc_receiver

	Line No.	Total	Covered	Percent
Branches		17	16	94.12
IF	133	2	2	100.00
CASE	178	11	10	90.91
IF	239	2	2	100.00
IF	252	2	2	100.00

133            if (!rst_ni) begin
               -1-  
134              esc_req_q <= 1'b0;
                 ==>
135            end else begin
136              esc_req_q <= esc_req_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

178            unique case (state_q)
                      -1-  
179              // wait for the esc_p/n diff pair
180              Idle: begin
181                if (esc_level) begin
                   -2-  
182                  state_d = Check;
                     ==>
183                  resp_pd = ~resp_pq;
184                  resp_nd = resp_pq;
185                end
                   MISSING_ELSE
                   ==>
186              end
187              // we decide here whether this is only a ping request or
188              // whether this is an escalation enable
189              Check: begin
190                state_d = PingResp;
191                resp_pd = ~resp_pq;
192                resp_nd = resp_pq;
193                if (esc_level) begin
                   -3-  
194                  state_d = EscResp;
                     ==>
195                  esc_req = 1'b1;
196                end
                   MISSING_ELSE
                   ==>
197              end
198              // finish ping response. in case esc_level is again asserted,
199              // we got an escalation signal (pings cannot occur back to back)
200              PingResp: begin
201                state_d = Idle;
202                resp_pd = ~resp_pq;
203                resp_nd = resp_pq;
204                ping_en = 1'b1;
205                if (esc_level) begin
                   -4-  
206                  state_d = EscResp;
                     ==>
207                  esc_req = 1'b1;
208                end
                   MISSING_ELSE
                   ==>
209              end
210              // we have got an escalation enable pulse,
211              // keep on toggling the outputs
212              EscResp: begin
213                state_d = Idle;
214                if (esc_level) begin
                   -5-  
215                  state_d = EscResp;
                     ==>
216                  resp_pd = ~resp_pq;
217                  resp_nd = resp_pq;
218                  esc_req = 1'b1;
219                end
                   MISSING_ELSE
                   ==>
220              end
221              // we have a signal integrity issue at one of
222              // the incoming diff pairs. this condition is
223              // signalled to the sender by setting the resp
224              // diffpair to the same value and continuously
225              // toggling them.
226              SigInt: begin
227                state_d = Idle;
228                esc_req = 1'b1;
229                if (sigint_detected) begin
                   -6-  
230                  state_d = SigInt;
                     ==>
231                  resp_pd = ~resp_pq;
232                  resp_nd = ~resp_pq;
233                end
                   MISSING_ELSE
                   ==>
234              end
235              default: state_d = Idle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
Idle	1	-	-	-	-	Covered	T1,T2,T3
Idle	0	-	-	-	-	Covered	T1,T2,T3
Check	-	1	-	-	-	Covered	T1,T2,T3
Check	-	0	-	-	-	Covered	T1,T2,T3
PingResp	-	-	1	-	-	Covered	T10,T6,T7
PingResp	-	-	0	-	-	Covered	T1,T2,T3
EscResp	-	-	-	1	-	Covered	T1,T2,T3
EscResp	-	-	-	0	-	Covered	T1,T2,T3
SigInt	-	-	-	-	1	Covered	T1,T2,T3
SigInt	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	Not Covered

239            if (sigint_detected && (state_q != SigInt)) begin
               -1-  
240              state_d = SigInt;
                 ==>
241              resp_pd = 1'b0;
242              resp_nd = 1'b0;
243            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

252            if (!rst_ni) begin
               -1-  
253              state_q <= Idle;
                 ==>
254            end else begin
255              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_esc_receiver

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	10	90.91
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	10	90.91

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DiffEncCheck_A	9829	5198	0	0
EscCntEsc_A	9829	20	0	0
EscCntWrap_A	9829	0	0	0
EscEnCheck_A	9829	338	0	0
EscEnKnownO_A	9829	5298	0	0
EscRespCheck_A	9829	358	0	20
PingRespCheck_A	9829	52	0	20
RespPKnownO_A	9829	5298	0	0
SigIntCheck0_A	9829	40	0	0
SigIntCheck1_A	9829	40	0	0
SigIntCheck2_A	9829	40	0	0

DiffEncCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	5198	0	0
T1	520	264	0	0
T2	465	223	0	0
T3	524	293	0	0
T4	494	262	0	0
T6	437	234	0	0
T7	470	272	0	0
T8	486	248	0	0
T9	418	251	0	0
T10	512	265	0	0
T12	546	269	0	0

EscCntEsc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	20	0	0
T1	520	1	0	0
T2	465	1	0	0
T3	524	1	0	0
T4	494	1	0	0
T6	437	1	0	0
T7	470	1	0	0
T8	486	1	0	0
T9	418	1	0	0
T10	512	1	0	0
T12	546	1	0	0

EscCntWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	0	0	0

EscEnCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	338	0	0
T1	520	14	0	0
T2	465	12	0	0
T3	524	20	0	0
T4	494	27	0	0
T6	437	10	0	0
T7	470	16	0	0
T8	486	9	0	0
T9	418	16	0	0
T10	512	20	0	0
T12	546	21	0	0

EscEnKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	5298	0	0
T1	520	269	0	0
T2	465	228	0	0
T3	524	298	0	0
T4	494	267	0	0
T6	437	239	0	0
T7	470	277	0	0
T8	486	253	0	0
T9	418	256	0	0
T10	512	270	0	0
T12	546	274	0	0

EscRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	358	0	20
T1	520	15	0	1
T2	465	13	0	1
T3	524	21	0	1
T4	494	28	0	1
T6	437	11	0	1
T7	470	17	0	1
T8	486	10	0	1
T9	418	17	0	1
T10	512	21	0	1
T12	546	22	0	1

PingRespCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	52	0	20
T1	520	2	0	1
T2	465	3	0	1
T3	524	3	0	1
T4	494	2	0	1
T6	437	3	0	1
T7	470	3	0	1
T8	486	3	0	1
T9	418	3	0	1
T10	512	3	0	1
T12	546	2	0	1

RespPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	5298	0	0
T1	520	269	0	0
T2	465	228	0	0
T3	524	298	0	0
T4	494	267	0	0
T6	437	239	0	0
T7	470	277	0	0
T8	486	253	0	0
T9	418	256	0	0
T10	512	270	0	0
T12	546	274	0	0

SigIntCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	40	0	0
T1	520	2	0	0
T2	465	2	0	0
T3	524	2	0	0
T4	494	2	0	0
T6	437	2	0	0
T7	470	2	0	0
T8	486	2	0	0
T9	418	2	0	0
T10	512	2	0	0
T12	546	2	0	0

SigIntCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	40	0	0
T1	520	2	0	0
T2	465	2	0	0
T3	524	2	0	0
T4	494	2	0	0
T6	437	2	0	0
T7	470	2	0	0
T8	486	2	0	0
T9	418	2	0	0
T10	512	2	0	0
T12	546	2	0	0

SigIntCheck2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9829	40	0	0
T1	520	2	0	0
T2	465	2	0	0
T3	524	2	0	0
T4	494	2	0	0
T6	437	2	0	0
T7	470	2	0	0
T8	486	2	0	0
T9	418	2	0	0
T10	512	2	0	0
T12	546	2	0	0