Unified Coverage Report :: Module :: prim_esc_sender

Module : prim_esc_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.78	91.53	86.21	100.00	100.00	85.71	81.25

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/prim_esc-sim-vcs/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_esc_tb.i_esc_sender	90.78	91.53	86.21	100.00	100.00	85.71	81.25

---

Module Instance : prim_esc_tb.i_esc_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.78	91.53	86.21	100.00	100.00	85.71	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.78	91.53	86.21	100.00	100.00	85.71	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_esc_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_esc_sender

	Line No.	Total	Covered	Percent
TOTAL		59	54	91.53
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	108	47	42	89.36
ALWAYS	216	9	9	100.00

78                      
79         1/1            assign ping_req_d = ping_req_i;
           Tests:       T1 T2 T3 
80         1/1            assign esc_req_d  = esc_req_i;
           Tests:       T1 T2 T3 
81                      
82                        // ping enable is 1 cycle pulse
83                        // escalation pulse is always longer than 2 cycles
84                        logic esc_p;
85         1/1            assign esc_p = esc_req_i | esc_req_q | (ping_req_d & ~ping_req_q);
           Tests:       T1 T2 T3 
86                      
87                        // This prevents further tool optimizations of the differential signal.
88                        prim_sec_anchor_buf #(
89                          .Width(2)
90                        ) u_prim_buf_esc (
91                          .in_i({~esc_p,
92                                 esc_p}),
93                          .out_o({esc_tx_o.esc_n,
94                                  esc_tx_o.esc_p})
95                        );
96                      
97                        //////////////
98                        // RX Logic //
99                        //////////////
100                     
101                       typedef enum logic [2:0] {Idle, CheckEscRespLo, CheckEscRespHi,
102                         CheckPingResp0, CheckPingResp1, CheckPingResp2, CheckPingResp3} fsm_e;
103                     
104                       fsm_e state_d, state_q;
105                     
106                       always_comb begin : p_fsm
107                         // default
108        1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
109        1/1              ping_ok_o    = 1'b0;
           Tests:       T1 T2 T3 
110        1/1              integ_fail_o = sigint_detected;
           Tests:       T1 T2 T3 
111                     
112        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
113                           // wait for ping or escalation enable
114                           Idle: begin
115        1/1                  if (esc_req_i) begin
           Tests:       T1 T2 T3 
116        1/1                    state_d = CheckEscRespHi;
           Tests:       T1 T2 T3 
117        1/1                  end else if (ping_req_d & ~ping_req_q) begin
           Tests:       T1 T2 T3 
118        1/1                    state_d = CheckPingResp0;
           Tests:       T1 T2 T3 
119                             end
                        MISSING_ELSE
120                             // any assertion of the response signal
121                             // signal here will trigger a sigint error
122        1/1                  if (resp) begin
           Tests:       T1 T2 T3 
123        1/1                    integ_fail_o = 1'b1;
           Tests:       T1 T2 T3 
124                             end
                        MISSING_ELSE
125                           end
126                           // check whether response is 0
127                           CheckEscRespLo: begin
128        1/1                  state_d      = CheckEscRespHi;
           Tests:       T1 T2 T3 
129        1/1                  if (!esc_tx_o.esc_p || resp) begin
           Tests:       T1 T2 T3 
130        1/1                    state_d = Idle;
           Tests:       T1 T2 T3 
131        1/1                    integ_fail_o = sigint_detected | resp;
           Tests:       T1 T2 T3 
132                             end
                        MISSING_ELSE
133                           end
134                           // check whether response is 1
135                           CheckEscRespHi: begin
136        1/1                  state_d = CheckEscRespLo;
           Tests:       T1 T2 T3 
137        1/1                  if (!esc_tx_o.esc_p || !resp) begin
           Tests:       T1 T2 T3 
138        1/1                    state_d = Idle;
           Tests:       T1 T2 T3 
139        1/1                    integ_fail_o = sigint_detected | ~resp;
           Tests:       T1 T2 T3 
140                             end
                        MISSING_ELSE
141                           end
142                           // start of ping response sequence
143                           // we expect the sequence "1010"
144                           CheckPingResp0: begin
145        1/1                  state_d = CheckPingResp1;
           Tests:       T1 T2 T3 
146                             // abort sequence immediately if escalation is signalled,
147                             // jump to escalation response checking (lo state)
148        1/1                  if (esc_req_i) begin
           Tests:       T1 T2 T3 
149        1/1                    state_d = CheckEscRespLo;
           Tests:       T4 T5 
150                             // abort if response is wrong
151        1/1                  end else if (!resp) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d = Idle;
           Tests:       T1 T2 T3 
153        1/1                    integ_fail_o = 1'b1;
           Tests:       T1 T2 T3 
154                             end
                        MISSING_ELSE
155                           end
156                           CheckPingResp1: begin
157        1/1                  state_d = CheckPingResp2;
           Tests:       T1 T2 T3 
158                             // abort sequence immediately if escalation is signalled,
159                             // jump to escalation response checking (hi state)
160        1/1                  if (esc_req_i) begin
           Tests:       T1 T2 T3 
161        1/1                    state_d = CheckEscRespHi;
           Tests:       T1 T6 T7 
162                             // abort if response is wrong
163        1/1                  end else if (resp) begin
           Tests:       T1 T2 T3 
164        0/1     ==>            state_d = Idle;
165        0/1     ==>            integ_fail_o = 1'b1;
166                             end
                        MISSING_ELSE
167                           end
168                           CheckPingResp2: begin
169        1/1                  state_d = CheckPingResp3;
           Tests:       T1 T2 T3 
170                             // abort sequence immediately if escalation is signalled,
171                             // jump to escalation response checking (lo state)
172        1/1                  if (esc_req_i) begin
           Tests:       T1 T2 T3 
173        1/1                    state_d = CheckEscRespLo;
           Tests:       T2 T8 T9 
174                             // abort if response is wrong
175        1/1                  end else if (!resp) begin
           Tests:       T1 T2 T3 
176        0/1     ==>            state_d = Idle;
177        0/1     ==>            integ_fail_o = 1'b1;
178                             end
                        MISSING_ELSE
179                           end
180                           CheckPingResp3: begin
181        1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
182                             // abort sequence immediately if escalation is signalled,
183                             // jump to escalation response checking (hi state)
184        1/1                  if (esc_req_i) begin
           Tests:       T1 T2 T3 
185        1/1                    state_d = CheckEscRespHi;
           Tests:       T10 T11 
186                             // abort if response is wrong
187        1/1                  end else if (resp) begin
           Tests:       T1 T2 T3 
188        0/1     ==>            integ_fail_o = 1'b1;
189                             end else begin
190        1/1                    ping_ok_o = ping_req_i;
           Tests:       T1 T2 T3 
191                             end
192                           end
193                           default : state_d = Idle;
194                         endcase
195                     
196                         // a sigint error will reset the state machine
197                         // and have it pause for two cycles to let the
198                         // receiver recover
199        1/1              if (sigint_detected) begin
           Tests:       T1 T2 T3 
200        1/1                ping_ok_o = 1'b0;
           Tests:       T1 T2 T3 
201        1/1                state_d = Idle;
           Tests:       T1 T2 T3 
202                         end
                        MISSING_ELSE
203                     
204                         // escalation takes precedence,
205                         // immediately return ok in that case
206        1/1              if ((esc_req_i || esc_req_q || esc_req_q1) && ping_req_i) begin
           Tests:       T1 T2 T3 
207        1/1                ping_ok_o = 1'b1;
           Tests:       T1 T2 T3 
208                         end
                        MISSING_ELSE
209                       end
210                     
211                       ///////////////
212                       // Registers //
213                       ///////////////
214                     
215                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
216        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
217        1/1                state_q   <= Idle;
           Tests:       T1 T2 T3 
218        1/1                esc_req_q  <= 1'b0;
           Tests:       T1 T2 T3 
219        1/1                esc_req_q1 <= 1'b0;
           Tests:       T1 T2 T3 
220        1/1                ping_req_q <= 1'b0;
           Tests:       T1 T2 T3 
221                         end else begin
222        1/1                state_q   <= state_d;
           Tests:       T1 T2 T3 
223        1/1                esc_req_q  <= esc_req_d;
           Tests:       T1 T2 T3 
224        1/1                esc_req_q1 <= esc_req_q;
           Tests:       T1 T2 T3 
225        1/1                ping_req_q <= ping_req_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_esc_sender

	Total	Covered	Percent
Conditions	29	25	86.21
Logical	29	25	86.21
Non-Logical	0	0
Event	0	0

 LINE       85
 EXPRESSION (esc_req_i | esc_req_q | (ping_req_d & ((~ping_req_q))))
             ----1----   ----2----   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       85
 SUB-EXPRESSION (ping_req_d & ((~ping_req_q)))
                 -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION (ping_req_d & ((~ping_req_q)))
             -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (((!esc_tx_o.esc_p)) || resp)
             ---------1---------    --2-

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T10
1	0	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (sigint_detected | resp)
             -------1-------   --2-

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       137
 EXPRESSION (((!esc_tx_o.esc_p)) || ((!resp)))
             ---------1---------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       139
 EXPRESSION (sigint_detected | ((~resp)))
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Not Covered

 LINE       206
 EXPRESSION ((esc_req_i || esc_req_q || esc_req_q1) && ping_req_i)
             -------------------1------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       206
 SUB-EXPRESSION (esc_req_i || esc_req_q || esc_req_q1)
                 ----1----    ----2----    -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T4,T6
1	0	0	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_esc_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00

Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ping_ok_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
integ_fail_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_req_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_rx_i.resp_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_rx_i.resp_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_o.esc_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
esc_tx_o.esc_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

FSM Coverage for Module : prim_esc_sender

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	17	17	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CheckEscRespHi	116	Covered	T1,T2,T3
CheckEscRespLo	136	Covered	T1,T2,T3
CheckPingResp0	118	Covered	T1,T2,T3
CheckPingResp1	145	Covered	T1,T2,T3
CheckPingResp2	157	Covered	T1,T2,T3
CheckPingResp3	169	Covered	T1,T2,T3
Idle	130	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
CheckEscRespHi->CheckEscRespLo	136	Covered	T1,T2,T3
CheckEscRespHi->Idle	138	Covered	T1,T2,T3
CheckEscRespLo->CheckEscRespHi	128	Covered	T1,T2,T3
CheckEscRespLo->Idle	130	Covered	T1,T2,T3
CheckPingResp0->CheckEscRespLo	149	Covered	T4,T5
CheckPingResp0->CheckPingResp1	145	Covered	T1,T2,T3
CheckPingResp0->Idle	152	Covered	T1,T2,T3
CheckPingResp1->CheckEscRespHi	161	Covered	T1,T6,T7
CheckPingResp1->CheckPingResp2	157	Covered	T1,T2,T3
CheckPingResp1->Idle	164	Covered	T3,T12,T5
CheckPingResp2->CheckEscRespLo	173	Covered	T2,T8,T9
CheckPingResp2->CheckPingResp3	169	Covered	T1,T2,T3
CheckPingResp2->Idle	176	Covered	T4,T13,T14
CheckPingResp3->CheckEscRespHi	185	Covered	T10,T11
CheckPingResp3->Idle	181	Covered	T1,T2,T3
Idle->CheckEscRespHi	116	Covered	T1,T2,T3
Idle->CheckPingResp0	118	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_esc_sender

	Line No.	Total	Covered	Percent
Branches		28	24	85.71
CASE	112	22	18	81.82
IF	199	2	2	100.00
IF	206	2	2	100.00
IF	216	2	2	100.00

112            unique case (state_q)
                      -1-  
113              // wait for ping or escalation enable
114              Idle: begin
115                if (esc_req_i) begin
                   -2-  
116                  state_d = CheckEscRespHi;
                     ==>
117                end else if (ping_req_d & ~ping_req_q) begin
                            -3-  
118                  state_d = CheckPingResp0;
                     ==>
119                end
                   MISSING_ELSE
                   ==>
120                // any assertion of the response signal
121                // signal here will trigger a sigint error
122                if (resp) begin
                   -4-  
123                  integ_fail_o = 1'b1;
                     ==>
124                end
                   MISSING_ELSE
                   ==>
125              end
126              // check whether response is 0
127              CheckEscRespLo: begin
128                state_d      = CheckEscRespHi;
129                if (!esc_tx_o.esc_p || resp) begin
                   -5-  
130                  state_d = Idle;
                     ==>
131                  integ_fail_o = sigint_detected | resp;
132                end
                   MISSING_ELSE
                   ==>
133              end
134              // check whether response is 1
135              CheckEscRespHi: begin
136                state_d = CheckEscRespLo;
137                if (!esc_tx_o.esc_p || !resp) begin
                   -6-  
138                  state_d = Idle;
                     ==>
139                  integ_fail_o = sigint_detected | ~resp;
140                end
                   MISSING_ELSE
                   ==>
141              end
142              // start of ping response sequence
143              // we expect the sequence "1010"
144              CheckPingResp0: begin
145                state_d = CheckPingResp1;
146                // abort sequence immediately if escalation is signalled,
147                // jump to escalation response checking (lo state)
148                if (esc_req_i) begin
                   -7-  
149                  state_d = CheckEscRespLo;
                     ==>
150                // abort if response is wrong
151                end else if (!resp) begin
                            -8-  
152                  state_d = Idle;
                     ==>
153                  integ_fail_o = 1'b1;
154                end
                   MISSING_ELSE
                   ==>
155              end
156              CheckPingResp1: begin
157                state_d = CheckPingResp2;
158                // abort sequence immediately if escalation is signalled,
159                // jump to escalation response checking (hi state)
160                if (esc_req_i) begin
                   -9-  
161                  state_d = CheckEscRespHi;
                     ==>
162                // abort if response is wrong
163                end else if (resp) begin
                            -10-  
164                  state_d = Idle;
                     ==>
165                  integ_fail_o = 1'b1;
166                end
                   MISSING_ELSE
                   ==>
167              end
168              CheckPingResp2: begin
169                state_d = CheckPingResp3;
170                // abort sequence immediately if escalation is signalled,
171                // jump to escalation response checking (lo state)
172                if (esc_req_i) begin
                   -11-  
173                  state_d = CheckEscRespLo;
                     ==>
174                // abort if response is wrong
175                end else if (!resp) begin
                            -12-  
176                  state_d = Idle;
                     ==>
177                  integ_fail_o = 1'b1;
178                end
                   MISSING_ELSE
                   ==>
179              end
180              CheckPingResp3: begin
181                state_d = Idle;
182                // abort sequence immediately if escalation is signalled,
183                // jump to escalation response checking (hi state)
184                if (esc_req_i) begin
                   -13-  
185                  state_d = CheckEscRespHi;
                     ==>
186                // abort if response is wrong
187                end else if (resp) begin
                            -14-  
188                  integ_fail_o = 1'b1;
                     ==>
189                end else begin
190                  ping_ok_o = ping_req_i;
                     ==>
191                end
192              end
193              default : state_d = Idle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckEscRespLo	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckEscRespLo	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckEscRespHi	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckEscRespHi	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CheckPingResp0	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5
CheckPingResp0	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
CheckPingResp0	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
CheckPingResp1	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T6,T7
CheckPingResp1	-	-	-	-	-	-	-	0	1	-	-	-	-	Not Covered
CheckPingResp1	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T3
CheckPingResp2	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T8,T9
CheckPingResp2	-	-	-	-	-	-	-	-	-	0	1	-	-	Not Covered
CheckPingResp2	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T3
CheckPingResp3	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11
CheckPingResp3	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
CheckPingResp3	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

199            if (sigint_detected) begin
               -1-  
200              ping_ok_o = 1'b0;
                 ==>
201              state_d = Idle;
202            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

206            if ((esc_req_i || esc_req_q || esc_req_q1) && ping_req_i) begin
               -1-  
207              ping_ok_o = 1'b1;
                 ==>
208            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

216            if (!rst_ni) begin
               -1-  
217              state_q   <= Idle;
                 ==>
218              esc_req_q  <= 1'b0;
219              esc_req_q1 <= 1'b0;
220              ping_req_q <= 1'b0;
221            end else begin
222              state_q   <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_esc_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DiffEncCheck_A	9487	5304	0	0
EscCheck_A	9487	399	0	0
EscPKnownO_A	9487	5304	0	0
EscPingCheck_A	9487	33	0	0
IntegFailKnownO_A	9487	5304	0	0
PingCheck_A	9487	0	0	20
PingOkKnownO_A	9487	5304	0	0
SigIntBackCheck_A	9487	97	0	0
SigIntCheck0_A	9487	42	0	0
SigIntCheck1_A	9487	0	0	20
SigIntCheck2_A	9487	0	0	20
SigIntCheck3_A	9487	55	0	0
StateEscRespHiBackCheck_A	9487	239	0	0
StateEscRespHiCheck_A	9487	166	0	0
StateEscRespLoBackCheck_A	9487	199	0	0
StateEscRespLoCheck_A	9487	194	0	0

DiffEncCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	5304	0	0
T1	444	244	0	0
T2	469	264	0	0
T3	472	258	0	0
T4	503	271	0	0
T6	450	281	0	0
T7	419	216	0	0
T8	465	262	0	0
T10	442	248	0	0
T12	474	276	0	0
T15	527	287	0	0

EscCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	399	0	0
T1	444	18	0	0
T2	469	10	0	0
T3	472	17	0	0
T4	503	30	0	0
T6	450	24	0	0
T7	419	25	0	0
T8	465	13	0	0
T10	442	10	0	0
T12	474	25	0	0
T15	527	22	0	0

EscPKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	5304	0	0
T1	444	244	0	0
T2	469	264	0	0
T3	472	258	0	0
T4	503	271	0	0
T6	450	281	0	0
T7	419	216	0	0
T8	465	262	0	0
T10	442	248	0	0
T12	474	276	0	0
T15	527	287	0	0

EscPingCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	33	0	0
T1	444	1	0	0
T2	469	2	0	0
T3	472	2	0	0
T4	503	1	0	0
T6	450	1	0	0
T7	419	1	0	0
T8	465	2	0	0
T10	442	2	0	0
T12	474	1	0	0
T15	527	2	0	0

IntegFailKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	5304	0	0
T1	444	244	0	0
T2	469	264	0	0
T3	472	258	0	0
T4	503	271	0	0
T6	450	281	0	0
T7	419	216	0	0
T8	465	262	0	0
T10	442	248	0	0
T12	474	276	0	0
T15	527	287	0	0

PingCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	0	0	20

PingOkKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	5304	0	0
T1	444	244	0	0
T2	469	264	0	0
T3	472	258	0	0
T4	503	271	0	0
T6	450	281	0	0
T7	419	216	0	0
T8	465	262	0	0
T10	442	248	0	0
T12	474	276	0	0
T15	527	287	0	0

SigIntBackCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	97	0	0
T1	444	4	0	0
T2	469	5	0	0
T3	472	5	0	0
T4	503	5	0	0
T6	450	5	0	0
T7	419	5	0	0
T8	465	5	0	0
T10	442	5	0	0
T12	474	5	0	0
T15	527	5	0	0

SigIntCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	42	0	0
T1	444	3	0	0
T2	469	2	0	0
T3	472	2	0	0
T4	503	2	0	0
T6	450	2	0	0
T7	419	2	0	0
T8	465	2	0	0
T10	442	2	0	0
T12	474	2	0	0
T15	527	2	0	0

SigIntCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	0	0	20

SigIntCheck2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	0	0	20

SigIntCheck3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	55	0	0
T1	444	1	0	0
T2	469	3	0	0
T3	472	3	0	0
T4	503	3	0	0
T6	450	3	0	0
T7	419	3	0	0
T8	465	3	0	0
T10	442	3	0	0
T12	474	3	0	0
T15	527	3	0	0

StateEscRespHiBackCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	239	0	0
T1	444	10	0	0
T2	469	6	0	0
T3	472	11	0	0
T4	503	17	0	0
T6	450	14	0	0
T7	419	15	0	0
T8	465	8	0	0
T10	442	7	0	0
T12	474	14	0	0
T15	527	14	0	0

StateEscRespHiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	166	0	0
T1	444	6	0	0
T2	469	3	0	0
T3	472	7	0	0
T4	503	14	0	0
T6	450	10	0	0
T7	419	11	0	0
T8	465	5	0	0
T10	442	4	0	0
T12	474	10	0	0
T15	527	10	0	0

StateEscRespLoBackCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	199	0	0
T1	444	9	0	0
T2	469	6	0	0
T3	472	8	0	0
T4	503	15	0	0
T6	450	12	0	0
T7	419	13	0	0
T8	465	7	0	0
T10	442	5	0	0
T12	474	13	0	0
T15	527	10	0	0

StateEscRespLoCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9487	194	0	0
T1	444	9	0	0
T2	469	5	0	0
T3	472	8	0	0
T4	503	14	0	0
T6	450	12	0	0
T7	419	13	0	0
T8	465	6	0	0
T10	442	5	0	0
T12	474	13	0	0
T15	527	10	0	0