Module Definition
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Module : prim_lfsr
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00

Source File(s) :
/workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_lfsr_tb.gen_duts[8].i_prim_lfsr 98.31 100.00 96.55 100.00 100.00 95.00



Module Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_lfsr_tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_lfsr
Line No.TotalCoveredPercent
TOTAL3232100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN46511100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
ALWAYS48733100.00
ROUTINE5101010100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61511100.00
ALWAYS61855100.00
WARNING: The source file '/workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' or '../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
296 1 1
299 1 1
345 1 1
465 1 1
472 8 8
487 1 1
488 1 1
490 1 1
510 1 1
513 1 1
514 1 1
515 1 1
517 1 1
518 1 1
519 2 2
MISSING_ELSE
520 1 1
523 unreachable
524 unreachable
525 unreachable
527 unreachable
528 unreachable
529 unreachable
530 unreachable
533 unreachable
536 1 1
610 1 1
615 1 1
618 1 1
619 1 1
620 1 1
622 1 1
623 1 1


Cond Coverage for Module : prim_lfsr
TotalCoveredPercent
Conditions292896.55
Logical292896.55
Non-Logical00
Event00

 LINE       345
 EXPRESSION (seed_en_i ? seed_i : ((lfsr_en_i && lockup) ? DefaultSeedLocal : (lfsr_en_i ? next_lfsr_state : lfsr_q)))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       345
 SUB-EXPRESSION ((lfsr_en_i && lockup) ? DefaultSeedLocal : (lfsr_en_i ? next_lfsr_state : lfsr_q))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       345
 SUB-EXPRESSION (lfsr_en_i && lockup)
                 ----1----    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       345
 SUB-EXPRESSION (lfsr_en_i ? next_lfsr_state : lfsr_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       514
 EXPRESSION (next_state == 8'b0)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       610
 EXPRESSION 
 Number  Term
      1  (lfsr_en_i && lockup) ? '0 : ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)) ? '0 : (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i && lockup)
                 ----1----    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)) ? '0 : (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q))
                 --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val))
                 ----1----    -------------------------2------------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)
                -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       615
 EXPRESSION (gen_max_len_sva.perturbed_q | ((|entropy_i)) | seed_en_i)
             -------------1-------------   -------2------   ----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Toggle Coverage for Module : prim_lfsr
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 56 56 100.00
Total Bits 0->1 28 28 100.00
Total Bits 1->0 28 28 100.00

Ports 7 7 100.00
Port Bits 56 56 100.00
Port Bits 0->1 28 28 100.00
Port Bits 1->0 28 28 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_i[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
state_o[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT


Branch Coverage for Module : prim_lfsr
Line No.TotalCoveredPercent
Branches 15 15 100.00
TERNARY 345 4 4 100.00
TERNARY 610 4 4 100.00
IF 487 2 2 100.00
IF 618 2 2 100.00
IF 513 3 3 100.00

WARNING: The source file /workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' or '../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 345 (seed_en_i) ? -2-: 345 ((lfsr_en_i && lockup)) ? -3-: 345 (lfsr_en_i) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 610 ((lfsr_en_i && lockup)) ? -2-: 610 ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val))) ? -3-: 610 (lfsr_en_i) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 487 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 618 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 513 if ((64'(LfsrType) == 64'("GAL_XOR"))) -2-: 514 if ((next_state == 8'b0)) -3-: 519 if (state0) -4-: 523 if ((64'(LfsrType) == "FIB_XNOR")) -5-: 524 if ((&next_state))

Branches:
-1--2--3--4--5-StatusTests
1 1 - - - Covered T1,T2,T3
1 0 1 - - Covered T1,T2,T3
1 0 0 - - Covered T1,T2,T3
0 - - 1 1 Unreachable T4,T5,T6
0 - - 1 0 Unreachable T4,T5,T6
0 - - 0 - Unreachable


Assert Coverage for Module : prim_lfsr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 20 19 95.00 19 95.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 20 19 95.00 19 95.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CoeffCheck_A 1695063842 1679991861 0 0
DataKnownO_A 1695063842 1679991861 0 0
InputWidth_A 300 300 0 0
NextStateCheck_A 1695063842 1678227828 0 300
NoLockups_A 1695063842 1677774137 0 0
OutputKnown_A 1695063842 1679991861 0 0
OutputWidth_A 300 300 0 0
gen_ext_seed_sva.ExtDefaultSeedInputCheck_A 1695063842 1004473 0 0
gen_fib_xnor.DefaultSeedNzCheck_A 150 150 0 0
gen_fib_xnor.gen_lut.MaxLfsrWidth_A 150 150 0 0
gen_fib_xnor.gen_lut.MinLfsrWidth_A 150 150 0 0
gen_gal_xor.DefaultSeedNzCheck_A 150 150 0 0
gen_gal_xor.gen_lut.MaxLfsrWidth_A 150 150 0 0
gen_gal_xor.gen_lut.MinLfsrWidth_A 150 150 0 0
gen_lockup_mechanism_sva.LfsrLockupCheck_A 1695063842 1439 0 0
gen_max_len_sva.MaximalLengthCheck0_A 1695063842 6864 0 0
gen_max_len_sva.MaximalLengthCheck1_A 1695063842 1677772200 0 0
gen_perm_check.p_perm_check.PermutationCheck_A 300 300 0 0
p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A 300 300 0 0
p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A 0 0 0 0


CoeffCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 1679991861 0 0
T1 67533 9040 0 0
T2 54049 7046 0 0
T3 58941 8167 0 0
T7 65927 8210 0 0
T8 55826 7248 0 0
T9 64742 8456 0 0
T10 61018 8253 0 0
T11 70901 9100 0 0
T12 59698 7538 0 0
T13 42439 6007 0 0
T14 168182 167827 0 0
T15 168389 167855 0 0
T16 168216 167827 0 0
T17 168501 167864 0 0
T18 168211 167829 0 0
T19 168356 167847 0 0
T20 168232 167831 0 0
T21 168218 167832 0 0
T22 168481 167863 0 0
T23 168477 167863 0 0

DataKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 1679991861 0 0
T1 67533 9040 0 0
T2 54049 7046 0 0
T3 58941 8167 0 0
T7 65927 8210 0 0
T8 55826 7248 0 0
T9 64742 8456 0 0
T10 61018 8253 0 0
T11 70901 9100 0 0
T12 59698 7538 0 0
T13 42439 6007 0 0
T14 168182 167827 0 0
T15 168389 167855 0 0
T16 168216 167827 0 0
T17 168501 167864 0 0
T18 168211 167829 0 0
T19 168356 167847 0 0
T20 168232 167831 0 0
T21 168218 167832 0 0
T22 168481 167863 0 0
T23 168477 167863 0 0

InputWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 300 300 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

NextStateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 1678227828 0 300
T1 67533 2046 0 1
T2 54049 1659 0 1
T3 58941 1890 0 1
T7 65927 1926 0 1
T8 55826 1690 0 1
T9 64742 1916 0 1
T10 61018 1916 0 1
T11 70901 2107 0 1
T12 59698 1743 0 1
T13 42439 1373 0 1
T14 168182 167783 0 1
T15 168389 167789 0 1
T16 168216 167783 0 1
T17 168501 167790 0 1
T18 168211 167784 0 1
T19 168356 167787 0 1
T20 168232 167784 0 1
T21 168218 167784 0 1
T22 168481 167791 0 1
T23 168477 167790 0 1

NoLockups_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 1677774137 0 0
T1 67533 262 0 0
T2 54049 262 0 0
T3 58941 257 0 0
T7 65927 262 0 0
T8 55826 263 0 0
T9 64742 263 0 0
T10 61018 270 0 0
T11 70901 270 0 0
T12 59698 265 0 0
T13 42439 262 0 0
T14 168182 167772 0 0
T15 168389 167772 0 0
T16 168216 167772 0 0
T17 168501 167772 0 0
T18 168211 167772 0 0
T19 168356 167772 0 0
T20 168232 167772 0 0
T21 168218 167772 0 0
T22 168481 167772 0 0
T23 168477 167772 0 0

OutputKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 1679991861 0 0
T1 67533 9040 0 0
T2 54049 7046 0 0
T3 58941 8167 0 0
T7 65927 8210 0 0
T8 55826 7248 0 0
T9 64742 8456 0 0
T10 61018 8253 0 0
T11 70901 9100 0 0
T12 59698 7538 0 0
T13 42439 6007 0 0
T14 168182 167827 0 0
T15 168389 167855 0 0
T16 168216 167827 0 0
T17 168501 167864 0 0
T18 168211 167829 0 0
T19 168356 167847 0 0
T20 168232 167831 0 0
T21 168218 167832 0 0
T22 168481 167863 0 0
T23 168477 167863 0 0

OutputWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 300 300 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

gen_ext_seed_sva.ExtDefaultSeedInputCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 1004473 0 0
T1 67533 4068 0 0
T2 54049 3081 0 0
T3 58941 3648 0 0
T7 65927 3504 0 0
T8 55826 3171 0 0
T9 64742 3714 0 0
T10 61018 3669 0 0
T11 70901 3962 0 0
T12 59698 3301 0 0
T13 42439 2612 0 0
T14 168182 2520 0 0
T15 168389 3839 0 0
T16 168216 2504 0 0
T17 168501 4277 0 0
T18 168211 2581 0 0
T19 168356 3339 0 0
T20 168232 2646 0 0
T21 168218 2812 0 0
T22 168481 4084 0 0
T23 168477 4182 0 0

gen_fib_xnor.DefaultSeedNzCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150 150 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0
T36 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

gen_fib_xnor.gen_lut.MaxLfsrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150 150 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0
T36 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

gen_fib_xnor.gen_lut.MinLfsrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150 150 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0
T36 1 1 0 0
T37 1 1 0 0
T38 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

gen_gal_xor.DefaultSeedNzCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150 150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

gen_gal_xor.gen_lut.MaxLfsrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150 150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

gen_gal_xor.gen_lut.MinLfsrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 150 150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

gen_lockup_mechanism_sva.LfsrLockupCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 1439 0 0
T1 67533 12 0 0
T2 54049 6 0 0
T3 58941 9 0 0
T7 65927 11 0 0
T8 55826 4 0 0
T9 64742 7 0 0
T10 61018 6 0 0
T11 70901 3 0 0
T12 59698 6 0 0
T13 42439 2 0 0
T14 168182 1 0 0
T15 168389 1 0 0
T16 168216 1 0 0
T17 168501 1 0 0
T18 168211 1 0 0
T19 168356 1 0 0
T20 168232 1 0 0
T21 168218 1 0 0
T22 168481 1 0 0
T23 168477 1 0 0

gen_max_len_sva.MaximalLengthCheck0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 6864 0 0
T1 67533 20 0 0
T2 54049 19 0 0
T3 58941 14 0 0
T7 65927 29 0 0
T8 55826 16 0 0
T9 64742 27 0 0
T10 61018 19 0 0
T11 70901 24 0 0
T12 59698 22 0 0
T13 42439 19 0 0
T14 168182 30 0 0
T15 168389 15 0 0
T16 168216 23 0 0
T17 168501 20 0 0
T18 168211 17 0 0
T19 168356 13 0 0
T20 168232 20 0 0
T21 168218 15 0 0
T22 168481 30 0 0
T23 168477 20 0 0

gen_max_len_sva.MaximalLengthCheck1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1695063842 1677772200 0 0
T1 67533 254 0 0
T2 54049 254 0 0
T3 58941 254 0 0
T7 65927 254 0 0
T8 55826 254 0 0
T9 64742 254 0 0
T10 61018 254 0 0
T11 70901 254 0 0
T12 59698 254 0 0
T13 42439 254 0 0
T14 168182 167772 0 0
T15 168389 167772 0 0
T16 168216 167772 0 0
T17 168501 167772 0 0
T18 168211 167772 0 0
T19 168356 167772 0 0
T20 168232 167772 0 0
T21 168218 167772 0 0
T22 168481 167772 0 0
T23 168477 167772 0 0

gen_perm_check.p_perm_check.PermutationCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 300 300 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 300 300 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

Line Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr
Line No.TotalCoveredPercent
TOTAL3232100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN46511100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
CONT_ASSIGN47211100.00
ALWAYS48733100.00
ROUTINE5101010100.00
CONT_ASSIGN61011100.00
CONT_ASSIGN61511100.00
ALWAYS61855100.00
WARNING: The source file '/workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' or '../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
296 1 1
299 1 1
345 1 1
465 1 1
472 8 8
487 1 1
488 1 1
490 1 1
510 1 1
513 1 1
514 1 1
515 1 1
517 1 1
518 1 1
519 2 2
MISSING_ELSE
520 1 1
523 unreachable
524 unreachable
525 unreachable
527 unreachable
528 unreachable
529 unreachable
530 unreachable
533 unreachable
536 1 1
610 1 1
615 1 1
618 1 1
619 1 1
620 1 1
622 1 1
623 1 1


Cond Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr
TotalCoveredPercent
Conditions292896.55
Logical292896.55
Non-Logical00
Event00

 LINE       345
 EXPRESSION (seed_en_i ? seed_i : ((lfsr_en_i && lockup) ? DefaultSeedLocal : (lfsr_en_i ? next_lfsr_state : lfsr_q)))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       345
 SUB-EXPRESSION ((lfsr_en_i && lockup) ? DefaultSeedLocal : (lfsr_en_i ? next_lfsr_state : lfsr_q))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       345
 SUB-EXPRESSION (lfsr_en_i && lockup)
                 ----1----    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       345
 SUB-EXPRESSION (lfsr_en_i ? next_lfsr_state : lfsr_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       514
 EXPRESSION (next_state == 8'b0)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       610
 EXPRESSION 
 Number  Term
      1  (lfsr_en_i && lockup) ? '0 : ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)) ? '0 : (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i && lockup)
                 ----1----    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)) ? '0 : (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q))
                 --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val))
                 ----1----    -------------------------2------------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)
                -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       615
 EXPRESSION (gen_max_len_sva.perturbed_q | ((|entropy_i)) | seed_en_i)
             -------------1-------------   -------2------   ----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

Toggle Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 56 56 100.00
Total Bits 0->1 28 28 100.00
Total Bits 1->0 28 28 100.00

Ports 7 7 100.00
Port Bits 56 56 100.00
Port Bits 0->1 28 28 100.00
Port Bits 1->0 28 28 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
seed_i[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
state_o[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT


Branch Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr
Line No.TotalCoveredPercent
Branches 15 15 100.00
TERNARY 345 4 4 100.00
TERNARY 610 4 4 100.00
IF 487 2 2 100.00
IF 618 2 2 100.00
IF 513 3 3 100.00

WARNING: The source file /workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' or '../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 345 (seed_en_i) ? -2-: 345 ((lfsr_en_i && lockup)) ? -3-: 345 (lfsr_en_i) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 610 ((lfsr_en_i && lockup)) ? -2-: 610 ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val))) ? -3-: 610 (lfsr_en_i) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 487 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 618 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 513 if ((64'(LfsrType) == 64'("GAL_XOR"))) -2-: 514 if ((next_state == 8'b0)) -3-: 519 if (state0) -4-: 523 if ((64'(LfsrType) == "FIB_XNOR")) -5-: 524 if ((&next_state))

Branches:
-1--2--3--4--5-StatusTests
1 1 - - - Covered T1,T2,T3
1 0 1 - - Covered T1,T2,T3
1 0 0 - - Covered T1,T2,T3
0 - - 1 1 Unreachable T4,T5,T6
0 - - 1 0 Unreachable T4,T5,T6
0 - - 0 - Unreachable


Assert Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 20 19 95.00 19 95.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 20 19 95.00 19 95.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CoeffCheck_A 11565912 1530139 0 0
DataKnownO_A 11565912 1530139 0 0
InputWidth_A 200 200 0 0
NextStateCheck_A 11565912 354682 0 200
NoLockups_A 11565912 52537 0 0
OutputKnown_A 11565912 1530139 0 0
OutputWidth_A 200 200 0 0
gen_ext_seed_sva.ExtDefaultSeedInputCheck_A 11565912 670024 0 0
gen_fib_xnor.DefaultSeedNzCheck_A 100 100 0 0
gen_fib_xnor.gen_lut.MaxLfsrWidth_A 100 100 0 0
gen_fib_xnor.gen_lut.MinLfsrWidth_A 100 100 0 0
gen_gal_xor.DefaultSeedNzCheck_A 100 100 0 0
gen_gal_xor.gen_lut.MaxLfsrWidth_A 100 100 0 0
gen_gal_xor.gen_lut.MinLfsrWidth_A 100 100 0 0
gen_lockup_mechanism_sva.LfsrLockupCheck_A 11565912 1339 0 0
gen_max_len_sva.MaximalLengthCheck0_A 11565912 4569 0 0
gen_max_len_sva.MaximalLengthCheck1_A 11565912 50800 0 0
gen_perm_check.p_perm_check.PermutationCheck_A 200 200 0 0
p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A 200 200 0 0
p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A 0 0 0 0


CoeffCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 1530139 0 0
T1 67533 9040 0 0
T2 54049 7046 0 0
T3 58941 8167 0 0
T7 65927 8210 0 0
T8 55826 7248 0 0
T9 64742 8456 0 0
T10 61018 8253 0 0
T11 70901 9100 0 0
T12 59698 7538 0 0
T13 42439 6007 0 0

DataKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 1530139 0 0
T1 67533 9040 0 0
T2 54049 7046 0 0
T3 58941 8167 0 0
T7 65927 8210 0 0
T8 55826 7248 0 0
T9 64742 8456 0 0
T10 61018 8253 0 0
T11 70901 9100 0 0
T12 59698 7538 0 0
T13 42439 6007 0 0

InputWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200 200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

NextStateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 354682 0 200
T1 67533 2046 0 1
T2 54049 1659 0 1
T3 58941 1890 0 1
T7 65927 1926 0 1
T8 55826 1690 0 1
T9 64742 1916 0 1
T10 61018 1916 0 1
T11 70901 2107 0 1
T12 59698 1743 0 1
T13 42439 1373 0 1

NoLockups_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 52537 0 0
T1 67533 262 0 0
T2 54049 262 0 0
T3 58941 257 0 0
T7 65927 262 0 0
T8 55826 263 0 0
T9 64742 263 0 0
T10 61018 270 0 0
T11 70901 270 0 0
T12 59698 265 0 0
T13 42439 262 0 0

OutputKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 1530139 0 0
T1 67533 9040 0 0
T2 54049 7046 0 0
T3 58941 8167 0 0
T7 65927 8210 0 0
T8 55826 7248 0 0
T9 64742 8456 0 0
T10 61018 8253 0 0
T11 70901 9100 0 0
T12 59698 7538 0 0
T13 42439 6007 0 0

OutputWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200 200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

gen_ext_seed_sva.ExtDefaultSeedInputCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 670024 0 0
T1 67533 4068 0 0
T2 54049 3081 0 0
T3 58941 3648 0 0
T7 65927 3504 0 0
T8 55826 3171 0 0
T9 64742 3714 0 0
T10 61018 3669 0 0
T11 70901 3962 0 0
T12 59698 3301 0 0
T13 42439 2612 0 0

gen_fib_xnor.DefaultSeedNzCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100 100 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

gen_fib_xnor.gen_lut.MaxLfsrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100 100 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

gen_fib_xnor.gen_lut.MinLfsrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100 100 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

gen_gal_xor.DefaultSeedNzCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100 100 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

gen_gal_xor.gen_lut.MaxLfsrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100 100 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

gen_gal_xor.gen_lut.MinLfsrWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100 100 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

gen_lockup_mechanism_sva.LfsrLockupCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 1339 0 0
T1 67533 12 0 0
T2 54049 6 0 0
T3 58941 9 0 0
T7 65927 11 0 0
T8 55826 4 0 0
T9 64742 7 0 0
T10 61018 6 0 0
T11 70901 3 0 0
T12 59698 6 0 0
T13 42439 2 0 0

gen_max_len_sva.MaximalLengthCheck0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 4569 0 0
T1 67533 20 0 0
T2 54049 19 0 0
T3 58941 14 0 0
T7 65927 29 0 0
T8 55826 16 0 0
T9 64742 27 0 0
T10 61018 19 0 0
T11 70901 24 0 0
T12 59698 22 0 0
T13 42439 19 0 0

gen_max_len_sva.MaximalLengthCheck1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11565912 50800 0 0
T1 67533 254 0 0
T2 54049 254 0 0
T3 58941 254 0 0
T7 65927 254 0 0
T8 55826 254 0 0
T9 64742 254 0 0
T10 61018 254 0 0
T11 70901 254 0 0
T12 59698 254 0 0
T13 42439 254 0 0

gen_perm_check.p_perm_check.PermutationCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200 200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200 200 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%