Detail Report for Assertions
Assertions Uncovered:
| ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A | 0 | 0 | 0 | 0 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A | 0 | 0 | 0 | 0 | 0 | 0 |
Assertions Success:
| ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.CoeffCheck_A | 0 | 0 | 1683336307 | 1678443994 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.DataKnownO_A | 0 | 0 | 1683336307 | 1678443994 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.InputWidth_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.NextStateCheck_A | 0 | 0 | 1683336307 | 1677870471 | 0 | 100 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.NoLockups_A | 0 | 0 | 1683336307 | 1677721600 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.OutputKnown_A | 0 | 0 | 1683336307 | 1678443994 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.OutputWidth_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_ext_seed_sva.ExtDefaultSeedInputCheck_A | 0 | 0 | 1683336307 | 326671 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_fib_xnor.DefaultSeedNzCheck_A | 0 | 0 | 50 | 50 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_fib_xnor.gen_lut.MaxLfsrWidth_A | 0 | 0 | 50 | 50 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_fib_xnor.gen_lut.MinLfsrWidth_A | 0 | 0 | 50 | 50 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_gal_xor.DefaultSeedNzCheck_A | 0 | 0 | 50 | 50 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_gal_xor.gen_lut.MaxLfsrWidth_A | 0 | 0 | 50 | 50 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_gal_xor.gen_lut.MinLfsrWidth_A | 0 | 0 | 50 | 50 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_lockup_mechanism_sva.LfsrLockupCheck_A | 0 | 0 | 1683336307 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_max_len_sva.MaximalLengthCheck0_A | 0 | 0 | 1683336307 | 2155 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_max_len_sva.MaximalLengthCheck1_A | 0 | 0 | 1683336307 | 1677721400 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.gen_perm_check.p_perm_check.PermutationCheck_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.CoeffCheck_A | 0 | 0 | 11873866 | 1574346 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.DataKnownO_A | 0 | 0 | 11873866 | 1574346 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.InputWidth_A | 0 | 0 | 200 | 200 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.NextStateCheck_A | 0 | 0 | 11873866 | 364895 | 0 | 200 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.NoLockups_A | 0 | 0 | 11873866 | 52502 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.OutputKnown_A | 0 | 0 | 11873866 | 1574346 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.OutputWidth_A | 0 | 0 | 200 | 200 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_ext_seed_sva.ExtDefaultSeedInputCheck_A | 0 | 0 | 11873866 | 689452 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_fib_xnor.DefaultSeedNzCheck_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_fib_xnor.gen_lut.MaxLfsrWidth_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_fib_xnor.gen_lut.MinLfsrWidth_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_gal_xor.DefaultSeedNzCheck_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_gal_xor.gen_lut.MaxLfsrWidth_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_gal_xor.gen_lut.MinLfsrWidth_A | 0 | 0 | 100 | 100 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_lockup_mechanism_sva.LfsrLockupCheck_A | 0 | 0 | 11873866 | 1401 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_max_len_sva.MaximalLengthCheck0_A | 0 | 0 | 11873866 | 4691 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_max_len_sva.MaximalLengthCheck1_A | 0 | 0 | 11873866 | 50800 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.gen_perm_check.p_perm_check.PermutationCheck_A | 0 | 0 | 200 | 200 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A | 0 | 0 | 200 | 200 | 0 | 0 |
Assertions Incomplete:
| ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.NextStateCheck_A | 0 | 0 | 1683336307 | 1677870471 | 0 | 100 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.NextStateCheck_A | 0 | 0 | 11873866 | 364895 | 0 | 200 |
Assertions Without Attempts:
| ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
| prim_lfsr_tb.gen_duts[24].i_prim_lfsr.p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A | 0 | 0 | 0 | 0 | 0 | 0 | |
| prim_lfsr_tb.gen_duts[8].i_prim_lfsr.p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A | 0 | 0 | 0 | 0 | 0 | 0 |