Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2858041077
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3779402438
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.846704213

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4140093234
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3563486675
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3087539650
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.876622648
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2896199383
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.449059376
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2313872343
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1998850839
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3653966497
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2517509749
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1463624301
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1786459908
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3433125306
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2011856799
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4005355206
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1839057695
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2290578878
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2944055268
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1935442173
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2509019674
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.360969807
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1713424868
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.591013863
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.86029580
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4166464410
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.676095443
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1110431458
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2084735306
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1751458456
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1058818498
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3037338026
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2000072971
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4111475312
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1403888324
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2782977121
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4050324753
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1677160713
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2395086192
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1655595580
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4273991732
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3478721723
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.324810456
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3652573017
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3646302846
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2760150386
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.190110193
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.513475817
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1440314649
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1489289643
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2895798184
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.191602611
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2846406912
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2500990583
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3542169214
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1000688123
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4035817158
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.529105590
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1436813221
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2452090955
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3542773396
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2468221158
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1474108456
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4135825171
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4073460178
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2814547419
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2878969361
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3328135095
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4039968938
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4208833959
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3748177429
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3348129831
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1050479509
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3761916805
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4113653496
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.821931263
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2331900235
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1092123130
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2057121192
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1180490223
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.982312640
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2174913601
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2118776866
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.621109816
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3851571281
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1917442320
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3703196880
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1320862398
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4101295309
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2642112632
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3917583833
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4181994430
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1022758405
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4204955510
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3706484734
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.182262262
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2901631035
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2182220974
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3783439263
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3341653338
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1332077878
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4119999150
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3394636792
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3843664218
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1624474501
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3509621274
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1898919063
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3315798509
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3339512848
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1178526131
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3653576292
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1118213642
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.495520417
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2299692737
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3801193949
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3403121318
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2051215522
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3119135089
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1394862793
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2556717023
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4127729052
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2071944003
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2182381298
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3554915160
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3050182031
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1485438547
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3329755449
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4292904128
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1902190092
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4154226150
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1392468287
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3986847919
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1792018871
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1771019916
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1996207753
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1492323614
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.254000690
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3206231314
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.741492079
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1995780239
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2017426376
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3670542178
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3841710440
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1622961790
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1601473908
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.875432126
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.279746474
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3946284489
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3803179183
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.865254497
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4117181555
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2805804946
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3314286598
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3377144710
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.765037675
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.548039330
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2696570742
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1627693219
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1999272020
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3129860475
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3417459559
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3413818718
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3555320966
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3865279766
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1767762953
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2635805779
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2805941199
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2290065779
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2360196886
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.39747250
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1505484110
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2975727320
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2796295466
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3057156090
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.505778362
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2951973390
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2521160008
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.47780841
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1369972971
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3509945708
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2809803832
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3981682916
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.905481507
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3783399600
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.780650493
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2131042934
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.386019518
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2312222354
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2273688585
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3793413833
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1066946525
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3701582339
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2802480042
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3226731613
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2724584583
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1880250166
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.613585364
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3249338254



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.386019518 Jul 04 04:19:31 PM PDT 24 Jul 04 04:19:42 PM PDT 24 1559830000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.765037675 Jul 04 04:23:22 PM PDT 24 Jul 04 04:23:32 PM PDT 24 1537290000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2273688585 Jul 04 04:19:38 PM PDT 24 Jul 04 04:19:48 PM PDT 24 1497890000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1066946525 Jul 04 04:19:40 PM PDT 24 Jul 04 04:19:47 PM PDT 24 1389750000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2858041077 Jul 04 04:21:35 PM PDT 24 Jul 04 04:21:46 PM PDT 24 1599810000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3783399600 Jul 04 04:20:35 PM PDT 24 Jul 04 04:20:46 PM PDT 24 1551750000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2360196886 Jul 04 04:20:48 PM PDT 24 Jul 04 04:20:58 PM PDT 24 1379850000 ps
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T12 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.39747250 Jul 04 04:23:39 PM PDT 24 Jul 04 04:23:48 PM PDT 24 1546710000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1880250166 Jul 04 04:21:31 PM PDT 24 Jul 04 04:21:41 PM PDT 24 1602870000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4117181555 Jul 04 04:23:51 PM PDT 24 Jul 04 04:23:58 PM PDT 24 1618610000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2951973390 Jul 04 04:23:22 PM PDT 24 Jul 04 04:23:31 PM PDT 24 1594130000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1767762953 Jul 04 04:24:10 PM PDT 24 Jul 04 04:24:21 PM PDT 24 1576070000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3129860475 Jul 04 04:24:56 PM PDT 24 Jul 04 04:25:04 PM PDT 24 1356750000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1627693219 Jul 04 04:23:52 PM PDT 24 Jul 04 04:24:02 PM PDT 24 1460510000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3249338254 Jul 04 04:20:56 PM PDT 24 Jul 04 04:21:05 PM PDT 24 1532830000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2635805779 Jul 04 04:23:21 PM PDT 24 Jul 04 04:23:30 PM PDT 24 1506130000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3509945708 Jul 04 04:20:28 PM PDT 24 Jul 04 04:20:39 PM PDT 24 1313210000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2809803832 Jul 04 04:20:36 PM PDT 24 Jul 04 04:20:43 PM PDT 24 1299950000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2696570742 Jul 04 04:23:35 PM PDT 24 Jul 04 04:23:44 PM PDT 24 1565730000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2521160008 Jul 04 04:19:39 PM PDT 24 Jul 04 04:19:48 PM PDT 24 1573690000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3981682916 Jul 04 04:24:05 PM PDT 24 Jul 04 04:24:12 PM PDT 24 1273450000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2131042934 Jul 04 04:22:08 PM PDT 24 Jul 04 04:22:18 PM PDT 24 1392430000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2724584583 Jul 04 04:19:41 PM PDT 24 Jul 04 04:19:49 PM PDT 24 1352410000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3377144710 Jul 04 04:21:10 PM PDT 24 Jul 04 04:21:18 PM PDT 24 1348270000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3555320966 Jul 04 04:21:13 PM PDT 24 Jul 04 04:21:22 PM PDT 24 1420610000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2802480042 Jul 04 04:21:59 PM PDT 24 Jul 04 04:22:07 PM PDT 24 1124790000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3417459559 Jul 04 04:24:10 PM PDT 24 Jul 04 04:24:19 PM PDT 24 1538090000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2805804946 Jul 04 04:24:09 PM PDT 24 Jul 04 04:24:18 PM PDT 24 1599770000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3793413833 Jul 04 04:20:25 PM PDT 24 Jul 04 04:20:34 PM PDT 24 1447890000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2805941199 Jul 04 04:23:52 PM PDT 24 Jul 04 04:24:04 PM PDT 24 1545930000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3057156090 Jul 04 04:23:39 PM PDT 24 Jul 04 04:23:47 PM PDT 24 1240350000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1999272020 Jul 04 04:23:21 PM PDT 24 Jul 04 04:23:30 PM PDT 24 1441910000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2312222354 Jul 04 04:19:38 PM PDT 24 Jul 04 04:19:46 PM PDT 24 1368410000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.47780841 Jul 04 04:20:09 PM PDT 24 Jul 04 04:20:19 PM PDT 24 1345430000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.905481507 Jul 04 04:23:51 PM PDT 24 Jul 04 04:23:59 PM PDT 24 1468210000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.613585364 Jul 04 04:20:42 PM PDT 24 Jul 04 04:20:49 PM PDT 24 1422290000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1505484110 Jul 04 04:21:01 PM PDT 24 Jul 04 04:21:10 PM PDT 24 1402910000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3701582339 Jul 04 04:23:53 PM PDT 24 Jul 04 04:24:01 PM PDT 24 1485950000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2975727320 Jul 04 04:24:51 PM PDT 24 Jul 04 04:24:59 PM PDT 24 1509970000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.548039330 Jul 04 04:23:56 PM PDT 24 Jul 04 04:24:04 PM PDT 24 1359510000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3865279766 Jul 04 04:23:35 PM PDT 24 Jul 04 04:23:44 PM PDT 24 1624810000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3314286598 Jul 04 04:23:23 PM PDT 24 Jul 04 04:23:30 PM PDT 24 1299790000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1369972971 Jul 04 04:19:52 PM PDT 24 Jul 04 04:20:02 PM PDT 24 1505070000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.505778362 Jul 04 04:21:23 PM PDT 24 Jul 04 04:21:31 PM PDT 24 1452550000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2796295466 Jul 04 04:21:19 PM PDT 24 Jul 04 04:21:29 PM PDT 24 1426970000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2290065779 Jul 04 04:23:54 PM PDT 24 Jul 04 04:24:03 PM PDT 24 1419190000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3226731613 Jul 04 04:24:56 PM PDT 24 Jul 04 04:25:05 PM PDT 24 1446450000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.865254497 Jul 04 04:21:37 PM PDT 24 Jul 04 04:21:47 PM PDT 24 1593550000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.780650493 Jul 04 04:20:36 PM PDT 24 Jul 04 04:20:46 PM PDT 24 1561430000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1655595580 Jul 04 05:32:51 PM PDT 24 Jul 04 06:09:38 PM PDT 24 336559030000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3646302846 Jul 04 05:32:31 PM PDT 24 Jul 04 06:07:18 PM PDT 24 336757350000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.591013863 Jul 04 05:32:32 PM PDT 24 Jul 04 06:12:12 PM PDT 24 336739170000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.86029580 Jul 04 05:32:30 PM PDT 24 Jul 04 06:09:34 PM PDT 24 336540230000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2313872343 Jul 04 05:32:30 PM PDT 24 Jul 04 06:02:46 PM PDT 24 336588690000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3779402438 Jul 04 05:32:35 PM PDT 24 Jul 04 06:05:51 PM PDT 24 336789770000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1403888324 Jul 04 05:32:42 PM PDT 24 Jul 04 06:06:57 PM PDT 24 336346510000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.190110193 Jul 04 05:32:45 PM PDT 24 Jul 04 06:06:09 PM PDT 24 336965030000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2896199383 Jul 04 05:32:51 PM PDT 24 Jul 04 06:05:50 PM PDT 24 336646010000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2782977121 Jul 04 05:32:33 PM PDT 24 Jul 04 06:12:21 PM PDT 24 336584570000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1751458456 Jul 04 05:32:42 PM PDT 24 Jul 04 06:03:22 PM PDT 24 336435410000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3563486675 Jul 04 05:32:29 PM PDT 24 Jul 04 06:03:18 PM PDT 24 336566130000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3037338026 Jul 04 05:32:34 PM PDT 24 Jul 04 06:07:09 PM PDT 24 336662450000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3652573017 Jul 04 05:32:38 PM PDT 24 Jul 04 06:09:52 PM PDT 24 336749130000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.876622648 Jul 04 05:32:40 PM PDT 24 Jul 04 06:05:13 PM PDT 24 336683830000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2395086192 Jul 04 05:32:31 PM PDT 24 Jul 04 06:11:23 PM PDT 24 336967030000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.449059376 Jul 04 05:32:31 PM PDT 24 Jul 04 06:06:52 PM PDT 24 336569290000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1058818498 Jul 04 05:32:30 PM PDT 24 Jul 04 06:02:48 PM PDT 24 336411070000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3087539650 Jul 04 05:32:31 PM PDT 24 Jul 04 06:07:20 PM PDT 24 336584150000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1786459908 Jul 04 05:32:33 PM PDT 24 Jul 04 06:05:43 PM PDT 24 336603250000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4005355206 Jul 04 05:32:37 PM PDT 24 Jul 04 06:09:36 PM PDT 24 336358610000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1440314649 Jul 04 05:32:39 PM PDT 24 Jul 04 06:06:24 PM PDT 24 336843130000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2509019674 Jul 04 05:32:32 PM PDT 24 Jul 04 06:12:21 PM PDT 24 336950330000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4166464410 Jul 04 05:32:31 PM PDT 24 Jul 04 06:08:51 PM PDT 24 336853910000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3433125306 Jul 04 05:32:34 PM PDT 24 Jul 04 06:07:10 PM PDT 24 336415690000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1839057695 Jul 04 05:32:39 PM PDT 24 Jul 04 06:02:21 PM PDT 24 336364130000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4140093234 Jul 04 05:32:30 PM PDT 24 Jul 04 06:02:14 PM PDT 24 336511090000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2944055268 Jul 04 05:32:31 PM PDT 24 Jul 04 06:05:40 PM PDT 24 336498770000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4273991732 Jul 04 05:32:33 PM PDT 24 Jul 04 06:11:28 PM PDT 24 336988290000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2000072971 Jul 04 05:32:47 PM PDT 24 Jul 04 06:10:31 PM PDT 24 336625210000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1463624301 Jul 04 05:32:31 PM PDT 24 Jul 04 06:06:40 PM PDT 24 337009150000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.513475817 Jul 04 05:32:30 PM PDT 24 Jul 04 06:05:37 PM PDT 24 336932910000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1998850839 Jul 04 05:32:42 PM PDT 24 Jul 04 06:09:46 PM PDT 24 336979310000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2011856799 Jul 04 05:32:41 PM PDT 24 Jul 04 06:10:06 PM PDT 24 336469910000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1110431458 Jul 04 05:32:36 PM PDT 24 Jul 04 06:05:47 PM PDT 24 337117010000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.360969807 Jul 04 05:32:52 PM PDT 24 Jul 04 06:03:19 PM PDT 24 336473810000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3653966497 Jul 04 05:32:35 PM PDT 24 Jul 04 06:08:47 PM PDT 24 337063830000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4050324753 Jul 04 05:32:30 PM PDT 24 Jul 04 06:03:00 PM PDT 24 336568910000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1677160713 Jul 04 05:32:50 PM PDT 24 Jul 04 06:09:19 PM PDT 24 337071850000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4111475312 Jul 04 05:32:58 PM PDT 24 Jul 04 06:03:57 PM PDT 24 336419610000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2760150386 Jul 04 05:32:31 PM PDT 24 Jul 04 06:12:14 PM PDT 24 336392290000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2517509749 Jul 04 05:32:29 PM PDT 24 Jul 04 06:08:49 PM PDT 24 336894270000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.676095443 Jul 04 05:32:37 PM PDT 24 Jul 04 06:09:08 PM PDT 24 336532970000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3478721723 Jul 04 05:32:28 PM PDT 24 Jul 04 06:07:45 PM PDT 24 336857890000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.324810456 Jul 04 05:32:32 PM PDT 24 Jul 04 06:12:14 PM PDT 24 336555670000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1713424868 Jul 04 05:32:45 PM PDT 24 Jul 04 06:08:56 PM PDT 24 336424670000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2084735306 Jul 04 05:32:34 PM PDT 24 Jul 04 06:03:24 PM PDT 24 336636790000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1935442173 Jul 04 05:32:34 PM PDT 24 Jul 04 06:07:29 PM PDT 24 336682450000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2290578878 Jul 04 05:32:34 PM PDT 24 Jul 04 06:07:27 PM PDT 24 336740890000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1489289643 Jul 04 05:32:29 PM PDT 24 Jul 04 06:03:48 PM PDT 24 336443270000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3843664218 Jul 04 04:23:35 PM PDT 24 Jul 04 04:23:42 PM PDT 24 1521990000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3206231314 Jul 04 04:23:38 PM PDT 24 Jul 04 04:23:48 PM PDT 24 1499770000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3403121318 Jul 04 04:20:38 PM PDT 24 Jul 04 04:20:49 PM PDT 24 1413250000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3315798509 Jul 04 04:20:12 PM PDT 24 Jul 04 04:20:19 PM PDT 24 1498330000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.495520417 Jul 04 04:20:26 PM PDT 24 Jul 04 04:20:36 PM PDT 24 1542030000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1392468287 Jul 04 04:23:22 PM PDT 24 Jul 04 04:23:30 PM PDT 24 1332310000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1178526131 Jul 04 04:20:38 PM PDT 24 Jul 04 04:20:49 PM PDT 24 1474910000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3946284489 Jul 04 04:19:36 PM PDT 24 Jul 04 04:19:44 PM PDT 24 1404610000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1996207753 Jul 04 04:23:22 PM PDT 24 Jul 04 04:23:31 PM PDT 24 1609390000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1624474501 Jul 04 04:20:00 PM PDT 24 Jul 04 04:20:10 PM PDT 24 1513650000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3509621274 Jul 04 04:24:11 PM PDT 24 Jul 04 04:24:21 PM PDT 24 1386130000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4119999150 Jul 04 04:20:26 PM PDT 24 Jul 04 04:20:36 PM PDT 24 1588990000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3841710440 Jul 04 04:30:39 PM PDT 24 Jul 04 04:30:49 PM PDT 24 1613490000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1492323614 Jul 04 04:23:38 PM PDT 24 Jul 04 04:23:47 PM PDT 24 1609850000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3050182031 Jul 04 04:23:38 PM PDT 24 Jul 04 04:23:47 PM PDT 24 1482370000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2556717023 Jul 04 04:20:37 PM PDT 24 Jul 04 04:20:45 PM PDT 24 1573750000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.875432126 Jul 04 04:23:49 PM PDT 24 Jul 04 04:23:56 PM PDT 24 1357670000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2299692737 Jul 04 04:24:17 PM PDT 24 Jul 04 04:24:25 PM PDT 24 1629610000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3554915160 Jul 04 04:20:19 PM PDT 24 Jul 04 04:20:29 PM PDT 24 1446010000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3329755449 Jul 04 04:23:46 PM PDT 24 Jul 04 04:23:51 PM PDT 24 1049550000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3341653338 Jul 04 04:23:38 PM PDT 24 Jul 04 04:23:47 PM PDT 24 1477690000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1485438547 Jul 04 04:24:30 PM PDT 24 Jul 04 04:24:39 PM PDT 24 1541710000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4292904128 Jul 04 04:20:48 PM PDT 24 Jul 04 04:20:55 PM PDT 24 1341050000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1771019916 Jul 04 04:23:52 PM PDT 24 Jul 04 04:24:03 PM PDT 24 1361450000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1622961790 Jul 04 04:30:39 PM PDT 24 Jul 04 04:30:49 PM PDT 24 1509950000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1898919063 Jul 04 04:23:35 PM PDT 24 Jul 04 04:23:43 PM PDT 24 1436670000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2071944003 Jul 04 04:24:26 PM PDT 24 Jul 04 04:24:34 PM PDT 24 1470790000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1332077878 Jul 04 04:19:40 PM PDT 24 Jul 04 04:19:48 PM PDT 24 1484310000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3803179183 Jul 04 04:20:12 PM PDT 24 Jul 04 04:20:23 PM PDT 24 1557930000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1601473908 Jul 04 04:23:46 PM PDT 24 Jul 04 04:23:54 PM PDT 24 1509710000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1118213642 Jul 04 04:21:24 PM PDT 24 Jul 04 04:21:36 PM PDT 24 1445410000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3670542178 Jul 04 04:30:38 PM PDT 24 Jul 04 04:30:46 PM PDT 24 1186490000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.279746474 Jul 04 04:24:12 PM PDT 24 Jul 04 04:24:19 PM PDT 24 1562150000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2017426376 Jul 04 04:30:40 PM PDT 24 Jul 04 04:30:49 PM PDT 24 1585370000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.741492079 Jul 04 04:30:40 PM PDT 24 Jul 04 04:30:50 PM PDT 24 1452010000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2182381298 Jul 04 04:21:44 PM PDT 24 Jul 04 04:21:56 PM PDT 24 1516410000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4154226150 Jul 04 04:23:52 PM PDT 24 Jul 04 04:24:02 PM PDT 24 1516610000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3119135089 Jul 04 04:22:08 PM PDT 24 Jul 04 04:22:16 PM PDT 24 1358130000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1394862793 Jul 04 04:24:06 PM PDT 24 Jul 04 04:24:14 PM PDT 24 1533730000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3339512848 Jul 04 04:23:43 PM PDT 24 Jul 04 04:23:50 PM PDT 24 1275930000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4127729052 Jul 04 04:24:56 PM PDT 24 Jul 04 04:25:05 PM PDT 24 1653290000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3653576292 Jul 04 04:24:30 PM PDT 24 Jul 04 04:24:39 PM PDT 24 1511950000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1792018871 Jul 04 04:20:57 PM PDT 24 Jul 04 04:21:07 PM PDT 24 1577750000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1902190092 Jul 04 04:24:26 PM PDT 24 Jul 04 04:24:33 PM PDT 24 1363990000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.254000690 Jul 04 04:19:42 PM PDT 24 Jul 04 04:19:50 PM PDT 24 1527930000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2051215522 Jul 04 04:20:54 PM PDT 24 Jul 04 04:21:04 PM PDT 24 1489250000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1995780239 Jul 04 04:30:42 PM PDT 24 Jul 04 04:30:53 PM PDT 24 1506570000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3394636792 Jul 04 04:24:30 PM PDT 24 Jul 04 04:24:39 PM PDT 24 1525390000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3986847919 Jul 04 04:23:23 PM PDT 24 Jul 04 04:23:31 PM PDT 24 1531870000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3801193949 Jul 04 04:23:53 PM PDT 24 Jul 04 04:24:00 PM PDT 24 1347350000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4101295309 Jul 04 05:32:33 PM PDT 24 Jul 04 06:03:59 PM PDT 24 336923190000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1092123130 Jul 04 05:32:39 PM PDT 24 Jul 04 06:08:24 PM PDT 24 336651150000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4035817158 Jul 04 05:32:44 PM PDT 24 Jul 04 06:06:08 PM PDT 24 336730470000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4181994430 Jul 04 05:32:55 PM PDT 24 Jul 04 06:06:35 PM PDT 24 336444110000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3703196880 Jul 04 05:32:35 PM PDT 24 Jul 04 06:11:37 PM PDT 24 336541010000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3706484734 Jul 04 05:32:31 PM PDT 24 Jul 04 06:10:19 PM PDT 24 336466590000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.846704213 Jul 04 05:32:38 PM PDT 24 Jul 04 06:09:54 PM PDT 24 336820890000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1050479509 Jul 04 05:32:31 PM PDT 24 Jul 04 06:11:28 PM PDT 24 337018770000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4073460178 Jul 04 05:32:31 PM PDT 24 Jul 04 06:10:04 PM PDT 24 336654750000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2174913601 Jul 04 05:32:53 PM PDT 24 Jul 04 06:09:01 PM PDT 24 337148770000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3542169214 Jul 04 05:32:50 PM PDT 24 Jul 04 06:07:56 PM PDT 24 336420650000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1180490223 Jul 04 05:32:39 PM PDT 24 Jul 04 06:00:52 PM PDT 24 336706510000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2452090955 Jul 04 05:32:50 PM PDT 24 Jul 04 06:06:35 PM PDT 24 336518050000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.191602611 Jul 04 05:32:54 PM PDT 24 Jul 04 06:02:48 PM PDT 24 336855590000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1436813221 Jul 04 05:32:38 PM PDT 24 Jul 04 06:08:28 PM PDT 24 336585030000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2878969361 Jul 04 05:32:44 PM PDT 24 Jul 04 06:06:26 PM PDT 24 336311970000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3542773396 Jul 04 05:32:41 PM PDT 24 Jul 04 06:09:28 PM PDT 24 336880170000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1320862398 Jul 04 05:32:46 PM PDT 24 Jul 04 06:06:08 PM PDT 24 336831470000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3748177429 Jul 04 05:32:38 PM PDT 24 Jul 04 06:08:32 PM PDT 24 336319290000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2895798184 Jul 04 05:32:39 PM PDT 24 Jul 04 06:09:14 PM PDT 24 336421910000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3348129831 Jul 04 05:32:52 PM PDT 24 Jul 04 06:10:15 PM PDT 24 336733690000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3783439263 Jul 04 05:32:36 PM PDT 24 Jul 04 06:08:24 PM PDT 24 336741630000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.529105590 Jul 04 05:32:34 PM PDT 24 Jul 04 06:11:32 PM PDT 24 336538250000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2057121192 Jul 04 05:32:57 PM PDT 24 Jul 04 06:04:07 PM PDT 24 336956730000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4204955510 Jul 04 05:32:35 PM PDT 24 Jul 04 06:00:48 PM PDT 24 336494150000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3328135095 Jul 04 05:32:30 PM PDT 24 Jul 04 06:09:47 PM PDT 24 336556550000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2182220974 Jul 04 05:32:48 PM PDT 24 Jul 04 06:06:34 PM PDT 24 337074470000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3761916805 Jul 04 05:32:38 PM PDT 24 Jul 04 06:07:26 PM PDT 24 336862510000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.982312640 Jul 04 05:32:39 PM PDT 24 Jul 04 06:07:11 PM PDT 24 336740470000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2642112632 Jul 04 05:32:50 PM PDT 24 Jul 04 06:02:42 PM PDT 24 337092390000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4113653496 Jul 04 05:32:37 PM PDT 24 Jul 04 06:05:25 PM PDT 24 336441090000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3851571281 Jul 04 05:32:55 PM PDT 24 Jul 04 06:06:06 PM PDT 24 336619710000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2500990583 Jul 04 05:32:38 PM PDT 24 Jul 04 06:08:19 PM PDT 24 336801130000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2814547419 Jul 04 05:32:28 PM PDT 24 Jul 04 06:09:14 PM PDT 24 336420210000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.821931263 Jul 04 05:32:45 PM PDT 24 Jul 04 06:05:49 PM PDT 24 336451950000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.621109816 Jul 04 05:32:37 PM PDT 24 Jul 04 06:08:30 PM PDT 24 336542390000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1022758405 Jul 04 05:32:35 PM PDT 24 Jul 04 06:04:37 PM PDT 24 336475430000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2846406912 Jul 04 05:32:48 PM PDT 24 Jul 04 06:06:15 PM PDT 24 336779310000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3917583833 Jul 04 05:32:49 PM PDT 24 Jul 04 06:09:45 PM PDT 24 336815750000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2468221158 Jul 04 05:32:39 PM PDT 24 Jul 04 06:06:44 PM PDT 24 336784110000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1000688123 Jul 04 05:32:48 PM PDT 24 Jul 04 06:09:56 PM PDT 24 336461290000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.182262262 Jul 04 05:32:53 PM PDT 24 Jul 04 06:10:13 PM PDT 24 336447150000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2331900235 Jul 04 05:32:47 PM PDT 24 Jul 04 06:10:13 PM PDT 24 336651750000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2901631035 Jul 04 05:32:47 PM PDT 24 Jul 04 06:10:09 PM PDT 24 336508210000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1474108456 Jul 04 05:32:31 PM PDT 24 Jul 04 06:10:14 PM PDT 24 337069730000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4135825171 Jul 04 05:32:33 PM PDT 24 Jul 04 06:11:31 PM PDT 24 336412830000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2118776866 Jul 04 05:32:41 PM PDT 24 Jul 04 06:03:24 PM PDT 24 336449610000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4208833959 Jul 04 05:32:34 PM PDT 24 Jul 04 06:11:31 PM PDT 24 337064630000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1917442320 Jul 04 05:32:55 PM PDT 24 Jul 04 06:06:25 PM PDT 24 336777210000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4039968938 Jul 04 05:32:33 PM PDT 24 Jul 04 06:11:36 PM PDT 24 336287750000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2858041077
Short name T8
Test name
Test status
Simulation time 1599810000 ps
CPU time 5.06 seconds
Started Jul 04 04:21:35 PM PDT 24
Finished Jul 04 04:21:46 PM PDT 24
Peak memory 164768 kb
Host smart-fcae2ec1-a5c7-4710-a75c-518514c33276
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2858041077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2858041077
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3779402438
Short name T16
Test name
Test status
Simulation time 336789770000 ps
CPU time 815.47 seconds
Started Jul 04 05:32:35 PM PDT 24
Finished Jul 04 06:05:51 PM PDT 24
Peak memory 160784 kb
Host smart-f098f3ac-b19c-4bea-8d35-80148ccee4cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3779402438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.3779402438
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.846704213
Short name T27
Test name
Test status
Simulation time 336820890000 ps
CPU time 876.94 seconds
Started Jul 04 05:32:38 PM PDT 24
Finished Jul 04 06:09:54 PM PDT 24
Peak memory 160772 kb
Host smart-4bf901a3-35e3-4678-992b-01897ffef683
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=846704213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.846704213
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4140093234
Short name T87
Test name
Test status
Simulation time 336511090000 ps
CPU time 731.5 seconds
Started Jul 04 05:32:30 PM PDT 24
Finished Jul 04 06:02:14 PM PDT 24
Peak memory 160768 kb
Host smart-08cb54f6-ed5c-4d88-90d3-43c1c6b15b34
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4140093234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.4140093234
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.3563486675
Short name T72
Test name
Test status
Simulation time 336566130000 ps
CPU time 749.12 seconds
Started Jul 04 05:32:29 PM PDT 24
Finished Jul 04 06:03:18 PM PDT 24
Peak memory 160788 kb
Host smart-18e2a6aa-eea7-4cb7-a849-78529d35c914
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3563486675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.3563486675
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3087539650
Short name T79
Test name
Test status
Simulation time 336584150000 ps
CPU time 820.57 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:07:20 PM PDT 24
Peak memory 160772 kb
Host smart-ebb2590b-44af-4c41-8a90-eb857a7b5be8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3087539650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3087539650
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.876622648
Short name T75
Test name
Test status
Simulation time 336683830000 ps
CPU time 792.85 seconds
Started Jul 04 05:32:40 PM PDT 24
Finished Jul 04 06:05:13 PM PDT 24
Peak memory 160780 kb
Host smart-45e7aaac-df80-4969-8078-b8cc7000e9c8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=876622648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.876622648
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2896199383
Short name T19
Test name
Test status
Simulation time 336646010000 ps
CPU time 803.52 seconds
Started Jul 04 05:32:51 PM PDT 24
Finished Jul 04 06:05:50 PM PDT 24
Peak memory 160804 kb
Host smart-a4cfebc9-580d-49be-901d-ffa8b5c03bdb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2896199383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2896199383
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.449059376
Short name T77
Test name
Test status
Simulation time 336569290000 ps
CPU time 814.09 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:06:52 PM PDT 24
Peak memory 160784 kb
Host smart-dacb5323-d4a1-4098-b14d-77d0f2ee4e60
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=449059376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.449059376
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2313872343
Short name T15
Test name
Test status
Simulation time 336588690000 ps
CPU time 737.34 seconds
Started Jul 04 05:32:30 PM PDT 24
Finished Jul 04 06:02:46 PM PDT 24
Peak memory 160780 kb
Host smart-6b46f4d9-ed8b-4e5d-8ac3-0474cf627eb4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2313872343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2313872343
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1998850839
Short name T93
Test name
Test status
Simulation time 336979310000 ps
CPU time 907.68 seconds
Started Jul 04 05:32:42 PM PDT 24
Finished Jul 04 06:09:46 PM PDT 24
Peak memory 160776 kb
Host smart-3d9d5735-580d-49fe-862b-f8db30d83c0f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1998850839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1998850839
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.3653966497
Short name T97
Test name
Test status
Simulation time 337063830000 ps
CPU time 878.65 seconds
Started Jul 04 05:32:35 PM PDT 24
Finished Jul 04 06:08:47 PM PDT 24
Peak memory 160776 kb
Host smart-3b3e7166-490d-4da5-93e6-c90b2415afec
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3653966497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.3653966497
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.2517509749
Short name T102
Test name
Test status
Simulation time 336894270000 ps
CPU time 869.68 seconds
Started Jul 04 05:32:29 PM PDT 24
Finished Jul 04 06:08:49 PM PDT 24
Peak memory 160772 kb
Host smart-5f3ebe02-7d57-4765-85e1-339166b5544a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2517509749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.2517509749
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1463624301
Short name T91
Test name
Test status
Simulation time 337009150000 ps
CPU time 835.07 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:06:40 PM PDT 24
Peak memory 160788 kb
Host smart-c210c163-04ba-48bb-a8b9-9cba9db78b62
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1463624301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1463624301
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1786459908
Short name T80
Test name
Test status
Simulation time 336603250000 ps
CPU time 793.85 seconds
Started Jul 04 05:32:33 PM PDT 24
Finished Jul 04 06:05:43 PM PDT 24
Peak memory 160784 kb
Host smart-0bacfeb1-df15-4d63-b647-1184b8aeaabe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1786459908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1786459908
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3433125306
Short name T85
Test name
Test status
Simulation time 336415690000 ps
CPU time 824.62 seconds
Started Jul 04 05:32:34 PM PDT 24
Finished Jul 04 06:07:10 PM PDT 24
Peak memory 160764 kb
Host smart-41fee41c-9dcb-462c-aa66-bc9b0ca3bfe4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3433125306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3433125306
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.2011856799
Short name T94
Test name
Test status
Simulation time 336469910000 ps
CPU time 891.41 seconds
Started Jul 04 05:32:41 PM PDT 24
Finished Jul 04 06:10:06 PM PDT 24
Peak memory 160752 kb
Host smart-bdb5419b-a98f-40fc-8e5c-7bfc97839251
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2011856799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.2011856799
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.4005355206
Short name T81
Test name
Test status
Simulation time 336358610000 ps
CPU time 856.47 seconds
Started Jul 04 05:32:37 PM PDT 24
Finished Jul 04 06:09:36 PM PDT 24
Peak memory 160752 kb
Host smart-eb6a4233-976e-417f-b77f-de65f505208f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4005355206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.4005355206
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1839057695
Short name T86
Test name
Test status
Simulation time 336364130000 ps
CPU time 717.72 seconds
Started Jul 04 05:32:39 PM PDT 24
Finished Jul 04 06:02:21 PM PDT 24
Peak memory 160800 kb
Host smart-4a50c538-e976-4668-a11a-9b91942ee0d8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1839057695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1839057695
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2290578878
Short name T109
Test name
Test status
Simulation time 336740890000 ps
CPU time 844.02 seconds
Started Jul 04 05:32:34 PM PDT 24
Finished Jul 04 06:07:27 PM PDT 24
Peak memory 160764 kb
Host smart-817a91ee-3f07-4f64-9036-9240131ef2cc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2290578878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2290578878
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2944055268
Short name T88
Test name
Test status
Simulation time 336498770000 ps
CPU time 816.13 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:05:40 PM PDT 24
Peak memory 160788 kb
Host smart-92ef03db-9a56-4887-8b9d-3c93fbec01db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2944055268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2944055268
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1935442173
Short name T108
Test name
Test status
Simulation time 336682450000 ps
CPU time 831.73 seconds
Started Jul 04 05:32:34 PM PDT 24
Finished Jul 04 06:07:29 PM PDT 24
Peak memory 160764 kb
Host smart-707d7007-e90a-4711-ba10-24dca3d2e756
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1935442173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1935442173
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2509019674
Short name T83
Test name
Test status
Simulation time 336950330000 ps
CPU time 943.45 seconds
Started Jul 04 05:32:32 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 160688 kb
Host smart-fa29d552-1b65-42e3-8976-39496c812b76
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2509019674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2509019674
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.360969807
Short name T96
Test name
Test status
Simulation time 336473810000 ps
CPU time 731.42 seconds
Started Jul 04 05:32:52 PM PDT 24
Finished Jul 04 06:03:19 PM PDT 24
Peak memory 160672 kb
Host smart-143ef4dd-4b4d-40aa-8063-ee5d5561a55b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=360969807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.360969807
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.1713424868
Short name T106
Test name
Test status
Simulation time 336424670000 ps
CPU time 880.79 seconds
Started Jul 04 05:32:45 PM PDT 24
Finished Jul 04 06:08:56 PM PDT 24
Peak memory 160780 kb
Host smart-802b3594-9dbc-4be7-9f5f-4e2fd4a44bbe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1713424868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.1713424868
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.591013863
Short name T6
Test name
Test status
Simulation time 336739170000 ps
CPU time 940.09 seconds
Started Jul 04 05:32:32 PM PDT 24
Finished Jul 04 06:12:12 PM PDT 24
Peak memory 160692 kb
Host smart-70d391ec-4fec-42f4-82ce-39f46f764969
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=591013863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.591013863
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.86029580
Short name T14
Test name
Test status
Simulation time 336540230000 ps
CPU time 892.26 seconds
Started Jul 04 05:32:30 PM PDT 24
Finished Jul 04 06:09:34 PM PDT 24
Peak memory 160776 kb
Host smart-bc4f1621-bf16-43f7-983b-1ce0db1e519f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=86029580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.86029580
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.4166464410
Short name T84
Test name
Test status
Simulation time 336853910000 ps
CPU time 870.61 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:08:51 PM PDT 24
Peak memory 160772 kb
Host smart-f232e21e-1e84-4113-b4cc-8ccf6891ec55
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4166464410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.4166464410
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.676095443
Short name T103
Test name
Test status
Simulation time 336532970000 ps
CPU time 887.66 seconds
Started Jul 04 05:32:37 PM PDT 24
Finished Jul 04 06:09:08 PM PDT 24
Peak memory 160756 kb
Host smart-c1bfb1f8-5c5e-4514-9a43-1be6dcc0c7db
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=676095443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.676095443
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1110431458
Short name T95
Test name
Test status
Simulation time 337117010000 ps
CPU time 797.24 seconds
Started Jul 04 05:32:36 PM PDT 24
Finished Jul 04 06:05:47 PM PDT 24
Peak memory 160788 kb
Host smart-8ed7aae3-9dbc-41c6-9bd7-42fb0184a2f7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1110431458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1110431458
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.2084735306
Short name T107
Test name
Test status
Simulation time 336636790000 ps
CPU time 737.02 seconds
Started Jul 04 05:32:34 PM PDT 24
Finished Jul 04 06:03:24 PM PDT 24
Peak memory 160792 kb
Host smart-3c34210b-d888-4610-b1b1-13503dd84183
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2084735306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.2084735306
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1751458456
Short name T71
Test name
Test status
Simulation time 336435410000 ps
CPU time 731.72 seconds
Started Jul 04 05:32:42 PM PDT 24
Finished Jul 04 06:03:22 PM PDT 24
Peak memory 160792 kb
Host smart-d75c23b5-3da9-4135-b421-5dfccaa6926e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1751458456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1751458456
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1058818498
Short name T78
Test name
Test status
Simulation time 336411070000 ps
CPU time 737.82 seconds
Started Jul 04 05:32:30 PM PDT 24
Finished Jul 04 06:02:48 PM PDT 24
Peak memory 160788 kb
Host smart-56080a37-d8ed-404c-9547-e24c95d76e86
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1058818498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1058818498
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3037338026
Short name T73
Test name
Test status
Simulation time 336662450000 ps
CPU time 831.55 seconds
Started Jul 04 05:32:34 PM PDT 24
Finished Jul 04 06:07:09 PM PDT 24
Peak memory 160764 kb
Host smart-4a5c2cae-218d-414c-a730-e4c3aef74570
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3037338026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3037338026
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2000072971
Short name T90
Test name
Test status
Simulation time 336625210000 ps
CPU time 891.58 seconds
Started Jul 04 05:32:47 PM PDT 24
Finished Jul 04 06:10:31 PM PDT 24
Peak memory 160752 kb
Host smart-fe5894de-43c4-4ce0-93e0-b941830f54de
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2000072971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.2000072971
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4111475312
Short name T100
Test name
Test status
Simulation time 336419610000 ps
CPU time 735.82 seconds
Started Jul 04 05:32:58 PM PDT 24
Finished Jul 04 06:03:57 PM PDT 24
Peak memory 160680 kb
Host smart-186be090-c011-4af2-9eb3-5ea7df94c4e5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4111475312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4111475312
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1403888324
Short name T17
Test name
Test status
Simulation time 336346510000 ps
CPU time 823.74 seconds
Started Jul 04 05:32:42 PM PDT 24
Finished Jul 04 06:06:57 PM PDT 24
Peak memory 160764 kb
Host smart-12275440-f7a7-4fa9-bbcb-94f5e3d80bfe
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1403888324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1403888324
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2782977121
Short name T20
Test name
Test status
Simulation time 336584570000 ps
CPU time 944.67 seconds
Started Jul 04 05:32:33 PM PDT 24
Finished Jul 04 06:12:21 PM PDT 24
Peak memory 160688 kb
Host smart-dc87306b-42f2-4ff9-8d91-ce1337ab378f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2782977121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2782977121
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.4050324753
Short name T98
Test name
Test status
Simulation time 336568910000 ps
CPU time 739.86 seconds
Started Jul 04 05:32:30 PM PDT 24
Finished Jul 04 06:03:00 PM PDT 24
Peak memory 160780 kb
Host smart-2ad96369-01bb-4254-b612-2e58503ac8f3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4050324753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.4050324753
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1677160713
Short name T99
Test name
Test status
Simulation time 337071850000 ps
CPU time 877.35 seconds
Started Jul 04 05:32:50 PM PDT 24
Finished Jul 04 06:09:19 PM PDT 24
Peak memory 160796 kb
Host smart-8c062c81-2062-441c-8ef3-919849f83875
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1677160713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1677160713
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.2395086192
Short name T76
Test name
Test status
Simulation time 336967030000 ps
CPU time 945.61 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:11:23 PM PDT 24
Peak memory 160780 kb
Host smart-ad18e984-220d-454e-a439-6f353efb5427
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2395086192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.2395086192
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1655595580
Short name T4
Test name
Test status
Simulation time 336559030000 ps
CPU time 880.76 seconds
Started Jul 04 05:32:51 PM PDT 24
Finished Jul 04 06:09:38 PM PDT 24
Peak memory 160800 kb
Host smart-8838dafc-1479-4602-99d9-87825b16fe95
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1655595580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1655595580
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.4273991732
Short name T89
Test name
Test status
Simulation time 336988290000 ps
CPU time 907.38 seconds
Started Jul 04 05:32:33 PM PDT 24
Finished Jul 04 06:11:28 PM PDT 24
Peak memory 160724 kb
Host smart-46d5b342-9051-407d-a84d-a963481d6baf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4273991732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.4273991732
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3478721723
Short name T104
Test name
Test status
Simulation time 336857890000 ps
CPU time 841.65 seconds
Started Jul 04 05:32:28 PM PDT 24
Finished Jul 04 06:07:45 PM PDT 24
Peak memory 160784 kb
Host smart-e916f2e5-0d16-44da-aa63-7cc1e52c5814
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3478721723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3478721723
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.324810456
Short name T105
Test name
Test status
Simulation time 336555670000 ps
CPU time 940.29 seconds
Started Jul 04 05:32:32 PM PDT 24
Finished Jul 04 06:12:14 PM PDT 24
Peak memory 160688 kb
Host smart-a4b9b7e0-13a2-49e0-a224-9963ca24bd90
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=324810456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.324810456
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3652573017
Short name T74
Test name
Test status
Simulation time 336749130000 ps
CPU time 870.78 seconds
Started Jul 04 05:32:38 PM PDT 24
Finished Jul 04 06:09:52 PM PDT 24
Peak memory 160752 kb
Host smart-41b05a76-1484-43e6-bfaa-052df4aef954
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3652573017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3652573017
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.3646302846
Short name T5
Test name
Test status
Simulation time 336757350000 ps
CPU time 826.03 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:07:18 PM PDT 24
Peak memory 160784 kb
Host smart-35dd40af-4e94-4ed4-94e5-a2a9196e1baf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3646302846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.3646302846
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2760150386
Short name T101
Test name
Test status
Simulation time 336392290000 ps
CPU time 945.54 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:12:14 PM PDT 24
Peak memory 160680 kb
Host smart-0ae8284b-25d8-416e-a3f9-2ea09b04ee9f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2760150386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2760150386
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.190110193
Short name T18
Test name
Test status
Simulation time 336965030000 ps
CPU time 822.15 seconds
Started Jul 04 05:32:45 PM PDT 24
Finished Jul 04 06:06:09 PM PDT 24
Peak memory 160780 kb
Host smart-2193c00d-cb03-48d4-9915-70be1085e78b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=190110193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.190110193
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.513475817
Short name T92
Test name
Test status
Simulation time 336932910000 ps
CPU time 795.9 seconds
Started Jul 04 05:32:30 PM PDT 24
Finished Jul 04 06:05:37 PM PDT 24
Peak memory 160780 kb
Host smart-ccd19449-a232-4870-aaf1-d31e440db4a6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=513475817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.513475817
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1440314649
Short name T82
Test name
Test status
Simulation time 336843130000 ps
CPU time 815.57 seconds
Started Jul 04 05:32:39 PM PDT 24
Finished Jul 04 06:06:24 PM PDT 24
Peak memory 160764 kb
Host smart-a8d31c8f-81f1-49d2-bd09-5b9eb91f3667
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1440314649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1440314649
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1489289643
Short name T110
Test name
Test status
Simulation time 336443270000 ps
CPU time 756.48 seconds
Started Jul 04 05:32:29 PM PDT 24
Finished Jul 04 06:03:48 PM PDT 24
Peak memory 160780 kb
Host smart-65ddbf7f-250a-43a5-8b50-051c8abc4abf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1489289643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1489289643
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2895798184
Short name T170
Test name
Test status
Simulation time 336421910000 ps
CPU time 878.56 seconds
Started Jul 04 05:32:39 PM PDT 24
Finished Jul 04 06:09:14 PM PDT 24
Peak memory 160792 kb
Host smart-0f1933b8-e463-4253-a735-c45b132243fb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2895798184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2895798184
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.191602611
Short name T164
Test name
Test status
Simulation time 336855590000 ps
CPU time 719.58 seconds
Started Jul 04 05:32:54 PM PDT 24
Finished Jul 04 06:02:48 PM PDT 24
Peak memory 160676 kb
Host smart-e13c0f0b-23f6-4c16-9b4f-3cdf3f4ee28d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=191602611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.191602611
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2846406912
Short name T188
Test name
Test status
Simulation time 336779310000 ps
CPU time 795.58 seconds
Started Jul 04 05:32:48 PM PDT 24
Finished Jul 04 06:06:15 PM PDT 24
Peak memory 160792 kb
Host smart-818c0a6b-7f5a-4df4-9d42-00c8b7fd0146
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2846406912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2846406912
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2500990583
Short name T183
Test name
Test status
Simulation time 336801130000 ps
CPU time 846.51 seconds
Started Jul 04 05:32:38 PM PDT 24
Finished Jul 04 06:08:19 PM PDT 24
Peak memory 160764 kb
Host smart-00186ba8-cf43-4c31-9f47-795e6823b51f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2500990583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2500990583
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3542169214
Short name T161
Test name
Test status
Simulation time 336420650000 ps
CPU time 852.67 seconds
Started Jul 04 05:32:50 PM PDT 24
Finished Jul 04 06:07:56 PM PDT 24
Peak memory 160776 kb
Host smart-35fe7219-524c-4f4b-ac83-941549b22d24
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3542169214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3542169214
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1000688123
Short name T191
Test name
Test status
Simulation time 336461290000 ps
CPU time 861.42 seconds
Started Jul 04 05:32:48 PM PDT 24
Finished Jul 04 06:09:56 PM PDT 24
Peak memory 160792 kb
Host smart-8e169a1c-87fb-4bd8-a219-a3dd09611551
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1000688123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1000688123
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.4035817158
Short name T23
Test name
Test status
Simulation time 336730470000 ps
CPU time 826.27 seconds
Started Jul 04 05:32:44 PM PDT 24
Finished Jul 04 06:06:08 PM PDT 24
Peak memory 160788 kb
Host smart-0f34001d-d33d-4151-8ec5-20398a5678ab
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4035817158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.4035817158
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.529105590
Short name T173
Test name
Test status
Simulation time 336538250000 ps
CPU time 912.01 seconds
Started Jul 04 05:32:34 PM PDT 24
Finished Jul 04 06:11:32 PM PDT 24
Peak memory 160728 kb
Host smart-bcadfbab-feb9-4bfb-8f2a-d43cebe924bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=529105590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.529105590
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.1436813221
Short name T165
Test name
Test status
Simulation time 336585030000 ps
CPU time 854.43 seconds
Started Jul 04 05:32:38 PM PDT 24
Finished Jul 04 06:08:28 PM PDT 24
Peak memory 160764 kb
Host smart-b7190a24-30a6-41b4-be33-e8cbbb6464d2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1436813221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.1436813221
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2452090955
Short name T163
Test name
Test status
Simulation time 336518050000 ps
CPU time 798.24 seconds
Started Jul 04 05:32:50 PM PDT 24
Finished Jul 04 06:06:35 PM PDT 24
Peak memory 160792 kb
Host smart-a094143b-a372-483a-83fb-47f4b4dbb7d2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2452090955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2452090955
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3542773396
Short name T167
Test name
Test status
Simulation time 336880170000 ps
CPU time 882.84 seconds
Started Jul 04 05:32:41 PM PDT 24
Finished Jul 04 06:09:28 PM PDT 24
Peak memory 160804 kb
Host smart-1f9aa084-83d5-4006-a8ca-f156a2e6a025
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3542773396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3542773396
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.2468221158
Short name T190
Test name
Test status
Simulation time 336784110000 ps
CPU time 813.42 seconds
Started Jul 04 05:32:39 PM PDT 24
Finished Jul 04 06:06:44 PM PDT 24
Peak memory 160788 kb
Host smart-2f49e83a-1ead-4e68-970e-4acfdc6f0cbb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2468221158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.2468221158
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1474108456
Short name T195
Test name
Test status
Simulation time 337069730000 ps
CPU time 895.08 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:10:14 PM PDT 24
Peak memory 160780 kb
Host smart-588aaea9-21e9-435e-acb4-d548276bb39b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1474108456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1474108456
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.4135825171
Short name T196
Test name
Test status
Simulation time 336412830000 ps
CPU time 912.54 seconds
Started Jul 04 05:32:33 PM PDT 24
Finished Jul 04 06:11:31 PM PDT 24
Peak memory 160728 kb
Host smart-5da287fa-780c-42ec-891e-f5b81123a1e8
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4135825171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.4135825171
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.4073460178
Short name T29
Test name
Test status
Simulation time 336654750000 ps
CPU time 889.75 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:10:04 PM PDT 24
Peak memory 160780 kb
Host smart-960c2d8e-7109-43f7-a04b-3e293cb2a03b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4073460178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.4073460178
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.2814547419
Short name T184
Test name
Test status
Simulation time 336420210000 ps
CPU time 888.59 seconds
Started Jul 04 05:32:28 PM PDT 24
Finished Jul 04 06:09:14 PM PDT 24
Peak memory 160772 kb
Host smart-035bc8fe-e149-47d8-a2f5-4f1685ebd4b2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2814547419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.2814547419
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2878969361
Short name T166
Test name
Test status
Simulation time 336311970000 ps
CPU time 824.55 seconds
Started Jul 04 05:32:44 PM PDT 24
Finished Jul 04 06:06:26 PM PDT 24
Peak memory 160792 kb
Host smart-1630003b-677f-408e-a512-4eefbde61468
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2878969361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2878969361
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3328135095
Short name T176
Test name
Test status
Simulation time 336556550000 ps
CPU time 880.32 seconds
Started Jul 04 05:32:30 PM PDT 24
Finished Jul 04 06:09:47 PM PDT 24
Peak memory 160780 kb
Host smart-4a393859-10c0-4a4e-82ee-7d626bfb9457
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328135095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3328135095
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.4039968938
Short name T200
Test name
Test status
Simulation time 336287750000 ps
CPU time 917.46 seconds
Started Jul 04 05:32:33 PM PDT 24
Finished Jul 04 06:11:36 PM PDT 24
Peak memory 160728 kb
Host smart-dc1a505a-6adb-48d4-b258-301d4cada340
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4039968938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.4039968938
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4208833959
Short name T198
Test name
Test status
Simulation time 337064630000 ps
CPU time 913.38 seconds
Started Jul 04 05:32:34 PM PDT 24
Finished Jul 04 06:11:31 PM PDT 24
Peak memory 160728 kb
Host smart-f81c9078-d371-4155-b665-53b17b564e72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4208833959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4208833959
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3748177429
Short name T169
Test name
Test status
Simulation time 336319290000 ps
CPU time 827.65 seconds
Started Jul 04 05:32:38 PM PDT 24
Finished Jul 04 06:08:32 PM PDT 24
Peak memory 160784 kb
Host smart-f1be5094-e2c8-494b-a62c-89f6718fe9b7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3748177429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3748177429
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3348129831
Short name T171
Test name
Test status
Simulation time 336733690000 ps
CPU time 894.52 seconds
Started Jul 04 05:32:52 PM PDT 24
Finished Jul 04 06:10:15 PM PDT 24
Peak memory 160792 kb
Host smart-1159436c-91ea-4721-abb0-0bbe1a610fb9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3348129831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3348129831
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1050479509
Short name T28
Test name
Test status
Simulation time 337018770000 ps
CPU time 929.6 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:11:28 PM PDT 24
Peak memory 160784 kb
Host smart-8a01da6a-3d43-4c09-8a25-0120eb0a3ff2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1050479509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1050479509
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.3761916805
Short name T178
Test name
Test status
Simulation time 336862510000 ps
CPU time 860.86 seconds
Started Jul 04 05:32:38 PM PDT 24
Finished Jul 04 06:07:26 PM PDT 24
Peak memory 160792 kb
Host smart-a036452b-137c-4c72-a5d2-08c00a9a00e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3761916805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.3761916805
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.4113653496
Short name T181
Test name
Test status
Simulation time 336441090000 ps
CPU time 813.06 seconds
Started Jul 04 05:32:37 PM PDT 24
Finished Jul 04 06:05:25 PM PDT 24
Peak memory 160784 kb
Host smart-0b7ccc56-5d80-4d30-aff5-e2a11639e3f6
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4113653496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.4113653496
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.821931263
Short name T185
Test name
Test status
Simulation time 336451950000 ps
CPU time 807.58 seconds
Started Jul 04 05:32:45 PM PDT 24
Finished Jul 04 06:05:49 PM PDT 24
Peak memory 160780 kb
Host smart-e98e973e-5bfb-498e-94c1-413bbf1bff3d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=821931263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.821931263
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2331900235
Short name T193
Test name
Test status
Simulation time 336651750000 ps
CPU time 894.39 seconds
Started Jul 04 05:32:47 PM PDT 24
Finished Jul 04 06:10:13 PM PDT 24
Peak memory 160788 kb
Host smart-2d730506-e940-4250-ab7b-c2ad04f9e9ec
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2331900235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2331900235
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1092123130
Short name T22
Test name
Test status
Simulation time 336651150000 ps
CPU time 823.48 seconds
Started Jul 04 05:32:39 PM PDT 24
Finished Jul 04 06:08:24 PM PDT 24
Peak memory 160784 kb
Host smart-ea70d968-2d4c-47cc-97a3-6b339bd2ade3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1092123130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1092123130
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.2057121192
Short name T174
Test name
Test status
Simulation time 336956730000 ps
CPU time 755.67 seconds
Started Jul 04 05:32:57 PM PDT 24
Finished Jul 04 06:04:07 PM PDT 24
Peak memory 160784 kb
Host smart-c604068f-7c8a-457a-b419-1e1797aa14d9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2057121192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.2057121192
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1180490223
Short name T162
Test name
Test status
Simulation time 336706510000 ps
CPU time 693.08 seconds
Started Jul 04 05:32:39 PM PDT 24
Finished Jul 04 06:00:52 PM PDT 24
Peak memory 160768 kb
Host smart-8b3d6911-7fe2-4ec7-aaeb-fab94fa4439d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1180490223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1180490223
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.982312640
Short name T179
Test name
Test status
Simulation time 336740470000 ps
CPU time 845.33 seconds
Started Jul 04 05:32:39 PM PDT 24
Finished Jul 04 06:07:11 PM PDT 24
Peak memory 160792 kb
Host smart-54c49664-c223-43ff-9aa9-918dad6ec9f9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=982312640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.982312640
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2174913601
Short name T30
Test name
Test status
Simulation time 337148770000 ps
CPU time 877.37 seconds
Started Jul 04 05:32:53 PM PDT 24
Finished Jul 04 06:09:01 PM PDT 24
Peak memory 160784 kb
Host smart-a62c1945-aea1-4cac-9b25-4037d182b2cd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2174913601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2174913601
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2118776866
Short name T197
Test name
Test status
Simulation time 336449610000 ps
CPU time 740.22 seconds
Started Jul 04 05:32:41 PM PDT 24
Finished Jul 04 06:03:24 PM PDT 24
Peak memory 160804 kb
Host smart-8213c8e1-08e7-4f01-a1b5-38bc515a4a6c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2118776866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2118776866
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.621109816
Short name T186
Test name
Test status
Simulation time 336542390000 ps
CPU time 855.03 seconds
Started Jul 04 05:32:37 PM PDT 24
Finished Jul 04 06:08:30 PM PDT 24
Peak memory 160768 kb
Host smart-9c6aea16-4232-40e8-a12e-1c1270cf0b12
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=621109816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.621109816
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.3851571281
Short name T182
Test name
Test status
Simulation time 336619710000 ps
CPU time 815.19 seconds
Started Jul 04 05:32:55 PM PDT 24
Finished Jul 04 06:06:06 PM PDT 24
Peak memory 160808 kb
Host smart-7e7a37e7-6a45-4190-b96f-49416bfe0f92
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3851571281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.3851571281
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1917442320
Short name T199
Test name
Test status
Simulation time 336777210000 ps
CPU time 813.91 seconds
Started Jul 04 05:32:55 PM PDT 24
Finished Jul 04 06:06:25 PM PDT 24
Peak memory 160792 kb
Host smart-dda4977d-792b-4096-87da-83c513dcd62f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1917442320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1917442320
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3703196880
Short name T25
Test name
Test status
Simulation time 336541010000 ps
CPU time 914.3 seconds
Started Jul 04 05:32:35 PM PDT 24
Finished Jul 04 06:11:37 PM PDT 24
Peak memory 160728 kb
Host smart-c7083901-960d-4dd7-a8d1-3de85969852e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3703196880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3703196880
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1320862398
Short name T168
Test name
Test status
Simulation time 336831470000 ps
CPU time 814.27 seconds
Started Jul 04 05:32:46 PM PDT 24
Finished Jul 04 06:06:08 PM PDT 24
Peak memory 160792 kb
Host smart-c74f7714-6fff-4cb5-8ec8-17ec201c0b8b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1320862398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1320862398
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.4101295309
Short name T21
Test name
Test status
Simulation time 336923190000 ps
CPU time 771.2 seconds
Started Jul 04 05:32:33 PM PDT 24
Finished Jul 04 06:03:59 PM PDT 24
Peak memory 160776 kb
Host smart-0d42908f-e1f1-4a2f-b6bf-1800998f213c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4101295309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.4101295309
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2642112632
Short name T180
Test name
Test status
Simulation time 337092390000 ps
CPU time 701.11 seconds
Started Jul 04 05:32:50 PM PDT 24
Finished Jul 04 06:02:42 PM PDT 24
Peak memory 160796 kb
Host smart-3b48e4b8-04cb-494b-b07b-2a813966d8db
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2642112632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2642112632
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3917583833
Short name T189
Test name
Test status
Simulation time 336815750000 ps
CPU time 884.66 seconds
Started Jul 04 05:32:49 PM PDT 24
Finished Jul 04 06:09:45 PM PDT 24
Peak memory 160804 kb
Host smart-7233cc23-a9b7-452b-b94d-2c04e0e15658
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3917583833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3917583833
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.4181994430
Short name T24
Test name
Test status
Simulation time 336444110000 ps
CPU time 822.18 seconds
Started Jul 04 05:32:55 PM PDT 24
Finished Jul 04 06:06:35 PM PDT 24
Peak memory 160772 kb
Host smart-9f1e0cb6-6a8b-4c7f-a949-2b645ebf3a17
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4181994430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.4181994430
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1022758405
Short name T187
Test name
Test status
Simulation time 336475430000 ps
CPU time 793.07 seconds
Started Jul 04 05:32:35 PM PDT 24
Finished Jul 04 06:04:37 PM PDT 24
Peak memory 160788 kb
Host smart-07d49018-dd7f-4543-8d5d-691662687f1b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1022758405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1022758405
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.4204955510
Short name T175
Test name
Test status
Simulation time 336494150000 ps
CPU time 690.76 seconds
Started Jul 04 05:32:35 PM PDT 24
Finished Jul 04 06:00:48 PM PDT 24
Peak memory 160824 kb
Host smart-d579fc3f-67f2-4f07-8b5e-edf2265e125d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4204955510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.4204955510
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3706484734
Short name T26
Test name
Test status
Simulation time 336466590000 ps
CPU time 893.73 seconds
Started Jul 04 05:32:31 PM PDT 24
Finished Jul 04 06:10:19 PM PDT 24
Peak memory 160780 kb
Host smart-cbb0b099-5ef3-46c6-a3fc-acb39e33fdc3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3706484734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3706484734
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.182262262
Short name T192
Test name
Test status
Simulation time 336447150000 ps
CPU time 897.31 seconds
Started Jul 04 05:32:53 PM PDT 24
Finished Jul 04 06:10:13 PM PDT 24
Peak memory 160784 kb
Host smart-77f38aef-29d5-44a5-8e68-c68b9199f0c2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=182262262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.182262262
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2901631035
Short name T194
Test name
Test status
Simulation time 336508210000 ps
CPU time 910.15 seconds
Started Jul 04 05:32:47 PM PDT 24
Finished Jul 04 06:10:09 PM PDT 24
Peak memory 160788 kb
Host smart-5fcf47f5-0052-46cb-961f-13221f79358e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2901631035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2901631035
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.2182220974
Short name T177
Test name
Test status
Simulation time 337074470000 ps
CPU time 800.72 seconds
Started Jul 04 05:32:48 PM PDT 24
Finished Jul 04 06:06:34 PM PDT 24
Peak memory 160788 kb
Host smart-62bfa5d5-72ab-4081-8450-f7776eb149f1
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2182220974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.2182220974
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3783439263
Short name T172
Test name
Test status
Simulation time 336741630000 ps
CPU time 860.25 seconds
Started Jul 04 05:32:36 PM PDT 24
Finished Jul 04 06:08:24 PM PDT 24
Peak memory 160760 kb
Host smart-ab2aa791-9a13-493b-8519-95f0e7332b8e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3783439263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.3783439263
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.3341653338
Short name T131
Test name
Test status
Simulation time 1477690000 ps
CPU time 3.47 seconds
Started Jul 04 04:23:38 PM PDT 24
Finished Jul 04 04:23:47 PM PDT 24
Peak memory 164456 kb
Host smart-afc3ffb9-3bce-4f4e-b494-fd5e4ca1cbba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3341653338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.3341653338
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1332077878
Short name T138
Test name
Test status
Simulation time 1484310000 ps
CPU time 3.54 seconds
Started Jul 04 04:19:40 PM PDT 24
Finished Jul 04 04:19:48 PM PDT 24
Peak memory 165036 kb
Host smart-99269f95-3b3c-4cb3-8291-d1f00b34ccfa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332077878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.1332077878
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.4119999150
Short name T122
Test name
Test status
Simulation time 1588990000 ps
CPU time 4.44 seconds
Started Jul 04 04:20:26 PM PDT 24
Finished Jul 04 04:20:36 PM PDT 24
Peak memory 164832 kb
Host smart-a6ae2f33-988f-451b-ad40-d43013e10cfa
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4119999150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.4119999150
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.3394636792
Short name T158
Test name
Test status
Simulation time 1525390000 ps
CPU time 3.77 seconds
Started Jul 04 04:24:30 PM PDT 24
Finished Jul 04 04:24:39 PM PDT 24
Peak memory 164740 kb
Host smart-c9da8e68-3a3d-4633-a1da-5ce955517769
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394636792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.3394636792
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3843664218
Short name T111
Test name
Test status
Simulation time 1521990000 ps
CPU time 3.21 seconds
Started Jul 04 04:23:35 PM PDT 24
Finished Jul 04 04:23:42 PM PDT 24
Peak memory 164304 kb
Host smart-eb1ec53d-f331-46c3-b8a1-c66dd207800e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3843664218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3843664218
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1624474501
Short name T120
Test name
Test status
Simulation time 1513650000 ps
CPU time 4.69 seconds
Started Jul 04 04:20:00 PM PDT 24
Finished Jul 04 04:20:10 PM PDT 24
Peak memory 164796 kb
Host smart-f3834f88-8b74-470b-b952-f00bd69f2054
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1624474501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1624474501
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3509621274
Short name T121
Test name
Test status
Simulation time 1386130000 ps
CPU time 4.57 seconds
Started Jul 04 04:24:11 PM PDT 24
Finished Jul 04 04:24:21 PM PDT 24
Peak memory 164716 kb
Host smart-14c3627d-e7df-4820-a581-0cc162cd93c1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3509621274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3509621274
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1898919063
Short name T136
Test name
Test status
Simulation time 1436670000 ps
CPU time 3.39 seconds
Started Jul 04 04:23:35 PM PDT 24
Finished Jul 04 04:23:43 PM PDT 24
Peak memory 164748 kb
Host smart-0a104c12-816b-494e-ad8b-52c36de29270
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1898919063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1898919063
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3315798509
Short name T114
Test name
Test status
Simulation time 1498330000 ps
CPU time 3.09 seconds
Started Jul 04 04:20:12 PM PDT 24
Finished Jul 04 04:20:19 PM PDT 24
Peak memory 165096 kb
Host smart-7eb67be0-4628-4505-8f66-480b38448296
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315798509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3315798509
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3339512848
Short name T150
Test name
Test status
Simulation time 1275930000 ps
CPU time 2.73 seconds
Started Jul 04 04:23:43 PM PDT 24
Finished Jul 04 04:23:50 PM PDT 24
Peak memory 164508 kb
Host smart-e42c1358-3a1a-4984-bffd-3017966ffa73
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3339512848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3339512848
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.1178526131
Short name T117
Test name
Test status
Simulation time 1474910000 ps
CPU time 5.13 seconds
Started Jul 04 04:20:38 PM PDT 24
Finished Jul 04 04:20:49 PM PDT 24
Peak memory 164832 kb
Host smart-a30d8390-ca0a-4eda-9b8f-da159cfd0a0c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1178526131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.1178526131
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3653576292
Short name T152
Test name
Test status
Simulation time 1511950000 ps
CPU time 3.84 seconds
Started Jul 04 04:24:30 PM PDT 24
Finished Jul 04 04:24:39 PM PDT 24
Peak memory 164728 kb
Host smart-11973d53-d356-4184-8f9c-adf43f954e13
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3653576292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3653576292
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1118213642
Short name T141
Test name
Test status
Simulation time 1445410000 ps
CPU time 5.56 seconds
Started Jul 04 04:21:24 PM PDT 24
Finished Jul 04 04:21:36 PM PDT 24
Peak memory 164828 kb
Host smart-83eec2f6-325b-4cc2-ab35-e9151ab5b7e1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1118213642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1118213642
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.495520417
Short name T115
Test name
Test status
Simulation time 1542030000 ps
CPU time 4.39 seconds
Started Jul 04 04:20:26 PM PDT 24
Finished Jul 04 04:20:36 PM PDT 24
Peak memory 164828 kb
Host smart-fa66493e-b1f4-458e-a6e4-b8b3e9924408
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=495520417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.495520417
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2299692737
Short name T128
Test name
Test status
Simulation time 1629610000 ps
CPU time 3.13 seconds
Started Jul 04 04:24:17 PM PDT 24
Finished Jul 04 04:24:25 PM PDT 24
Peak memory 164756 kb
Host smart-797b1c27-15bf-4b6e-bd25-554670afd222
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2299692737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2299692737
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3801193949
Short name T160
Test name
Test status
Simulation time 1347350000 ps
CPU time 3.45 seconds
Started Jul 04 04:23:53 PM PDT 24
Finished Jul 04 04:24:00 PM PDT 24
Peak memory 164792 kb
Host smart-60f7e9ab-c764-4a92-83b1-31c1283dd617
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3801193949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3801193949
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3403121318
Short name T113
Test name
Test status
Simulation time 1413250000 ps
CPU time 4.91 seconds
Started Jul 04 04:20:38 PM PDT 24
Finished Jul 04 04:20:49 PM PDT 24
Peak memory 164764 kb
Host smart-5e71011f-d130-4c92-813f-b60d9341a179
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3403121318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3403121318
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.2051215522
Short name T156
Test name
Test status
Simulation time 1489250000 ps
CPU time 4.65 seconds
Started Jul 04 04:20:54 PM PDT 24
Finished Jul 04 04:21:04 PM PDT 24
Peak memory 164796 kb
Host smart-2962ba3c-ff9d-43ac-bf79-e42c77522f93
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2051215522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.2051215522
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3119135089
Short name T148
Test name
Test status
Simulation time 1358130000 ps
CPU time 4.04 seconds
Started Jul 04 04:22:08 PM PDT 24
Finished Jul 04 04:22:16 PM PDT 24
Peak memory 166320 kb
Host smart-06198773-5e3e-433a-953c-c9f7fcd01763
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3119135089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3119135089
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.1394862793
Short name T149
Test name
Test status
Simulation time 1533730000 ps
CPU time 3.71 seconds
Started Jul 04 04:24:06 PM PDT 24
Finished Jul 04 04:24:14 PM PDT 24
Peak memory 166312 kb
Host smart-5ba7b2bf-7bad-4b97-87d0-6375874eb30a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394862793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.1394862793
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.2556717023
Short name T126
Test name
Test status
Simulation time 1573750000 ps
CPU time 3.48 seconds
Started Jul 04 04:20:37 PM PDT 24
Finished Jul 04 04:20:45 PM PDT 24
Peak memory 164864 kb
Host smart-290326e9-ca20-4f25-ad8e-8d6a8b30281a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2556717023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.2556717023
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.4127729052
Short name T151
Test name
Test status
Simulation time 1653290000 ps
CPU time 3.89 seconds
Started Jul 04 04:24:56 PM PDT 24
Finished Jul 04 04:25:05 PM PDT 24
Peak memory 164700 kb
Host smart-36977e1d-ef7b-43e5-84fc-4bff3de982c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4127729052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.4127729052
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2071944003
Short name T137
Test name
Test status
Simulation time 1470790000 ps
CPU time 3.32 seconds
Started Jul 04 04:24:26 PM PDT 24
Finished Jul 04 04:24:34 PM PDT 24
Peak memory 164452 kb
Host smart-b5b85651-b11d-48f5-bbb0-eec665af965a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071944003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2071944003
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2182381298
Short name T146
Test name
Test status
Simulation time 1516410000 ps
CPU time 5.38 seconds
Started Jul 04 04:21:44 PM PDT 24
Finished Jul 04 04:21:56 PM PDT 24
Peak memory 164772 kb
Host smart-b14eadbf-40cf-49e7-ae98-df3d265abd7f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2182381298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2182381298
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3554915160
Short name T129
Test name
Test status
Simulation time 1446010000 ps
CPU time 4.53 seconds
Started Jul 04 04:20:19 PM PDT 24
Finished Jul 04 04:20:29 PM PDT 24
Peak memory 164824 kb
Host smart-3b7d5408-076c-4031-91eb-d735787b9f03
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554915160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.3554915160
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3050182031
Short name T125
Test name
Test status
Simulation time 1482370000 ps
CPU time 3.78 seconds
Started Jul 04 04:23:38 PM PDT 24
Finished Jul 04 04:23:47 PM PDT 24
Peak memory 162876 kb
Host smart-69e90acf-13a0-4c3f-af5d-257dd40b3c19
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3050182031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3050182031
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1485438547
Short name T132
Test name
Test status
Simulation time 1541710000 ps
CPU time 3.76 seconds
Started Jul 04 04:24:30 PM PDT 24
Finished Jul 04 04:24:39 PM PDT 24
Peak memory 164736 kb
Host smart-8728fdf9-a4c5-47d8-8f60-a6535139e738
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1485438547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1485438547
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3329755449
Short name T130
Test name
Test status
Simulation time 1049550000 ps
CPU time 2.59 seconds
Started Jul 04 04:23:46 PM PDT 24
Finished Jul 04 04:23:51 PM PDT 24
Peak memory 164508 kb
Host smart-968b61a5-3dcd-49d3-a2f0-6e3fe9229256
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3329755449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3329755449
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.4292904128
Short name T133
Test name
Test status
Simulation time 1341050000 ps
CPU time 3.05 seconds
Started Jul 04 04:20:48 PM PDT 24
Finished Jul 04 04:20:55 PM PDT 24
Peak memory 164800 kb
Host smart-668e2269-b24c-4523-a8dd-f0824956d05f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4292904128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.4292904128
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.1902190092
Short name T154
Test name
Test status
Simulation time 1363990000 ps
CPU time 3.09 seconds
Started Jul 04 04:24:26 PM PDT 24
Finished Jul 04 04:24:33 PM PDT 24
Peak memory 164452 kb
Host smart-8d354923-1eb4-4b43-99b4-5db52f72394d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1902190092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.1902190092
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4154226150
Short name T147
Test name
Test status
Simulation time 1516610000 ps
CPU time 3.95 seconds
Started Jul 04 04:23:52 PM PDT 24
Finished Jul 04 04:24:02 PM PDT 24
Peak memory 166340 kb
Host smart-f280939b-f4fd-447b-b229-0b5fc2dd850e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4154226150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.4154226150
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1392468287
Short name T116
Test name
Test status
Simulation time 1332310000 ps
CPU time 3.15 seconds
Started Jul 04 04:23:22 PM PDT 24
Finished Jul 04 04:23:30 PM PDT 24
Peak memory 163016 kb
Host smart-e6d4060c-6fc1-42ff-892a-a75ebb2d99b0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1392468287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1392468287
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.3986847919
Short name T159
Test name
Test status
Simulation time 1531870000 ps
CPU time 3.49 seconds
Started Jul 04 04:23:23 PM PDT 24
Finished Jul 04 04:23:31 PM PDT 24
Peak memory 164808 kb
Host smart-f59e7750-672a-466d-a6ac-4983fb1b173c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3986847919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.3986847919
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1792018871
Short name T153
Test name
Test status
Simulation time 1577750000 ps
CPU time 4.5 seconds
Started Jul 04 04:20:57 PM PDT 24
Finished Jul 04 04:21:07 PM PDT 24
Peak memory 164748 kb
Host smart-f691b6ba-883a-4dd1-979d-9dda28fa9254
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1792018871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1792018871
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.1771019916
Short name T134
Test name
Test status
Simulation time 1361450000 ps
CPU time 4.71 seconds
Started Jul 04 04:23:52 PM PDT 24
Finished Jul 04 04:24:03 PM PDT 24
Peak memory 164748 kb
Host smart-c13346f5-d0d3-4a81-9000-89701afa630e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1771019916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.1771019916
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1996207753
Short name T119
Test name
Test status
Simulation time 1609390000 ps
CPU time 3.53 seconds
Started Jul 04 04:23:22 PM PDT 24
Finished Jul 04 04:23:31 PM PDT 24
Peak memory 164328 kb
Host smart-4525ada6-f4f1-46d9-b8d3-2de3c579f311
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1996207753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1996207753
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1492323614
Short name T124
Test name
Test status
Simulation time 1609850000 ps
CPU time 3.82 seconds
Started Jul 04 04:23:38 PM PDT 24
Finished Jul 04 04:23:47 PM PDT 24
Peak memory 164752 kb
Host smart-2c09bc8a-5302-43ff-8958-cee4f6f57c7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1492323614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1492323614
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.254000690
Short name T155
Test name
Test status
Simulation time 1527930000 ps
CPU time 3.78 seconds
Started Jul 04 04:19:42 PM PDT 24
Finished Jul 04 04:19:50 PM PDT 24
Peak memory 164812 kb
Host smart-9360de8e-acb0-49da-b393-df53775c5328
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=254000690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.254000690
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.3206231314
Short name T112
Test name
Test status
Simulation time 1499770000 ps
CPU time 4.19 seconds
Started Jul 04 04:23:38 PM PDT 24
Finished Jul 04 04:23:48 PM PDT 24
Peak memory 163052 kb
Host smart-89b63074-3a47-4c8c-8814-a04764c235f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3206231314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.3206231314
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.741492079
Short name T145
Test name
Test status
Simulation time 1452010000 ps
CPU time 4.36 seconds
Started Jul 04 04:30:40 PM PDT 24
Finished Jul 04 04:30:50 PM PDT 24
Peak memory 164816 kb
Host smart-d07ad7d1-1fb9-49ac-b2ed-236d790abf08
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=741492079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.741492079
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1995780239
Short name T157
Test name
Test status
Simulation time 1506570000 ps
CPU time 5.22 seconds
Started Jul 04 04:30:42 PM PDT 24
Finished Jul 04 04:30:53 PM PDT 24
Peak memory 164808 kb
Host smart-9adee40f-fc53-4dbd-aca9-7fa350f6d832
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1995780239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1995780239
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2017426376
Short name T144
Test name
Test status
Simulation time 1585370000 ps
CPU time 3.84 seconds
Started Jul 04 04:30:40 PM PDT 24
Finished Jul 04 04:30:49 PM PDT 24
Peak memory 164744 kb
Host smart-396232d7-ae14-4052-b1ff-d91170c10bc1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2017426376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2017426376
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3670542178
Short name T142
Test name
Test status
Simulation time 1186490000 ps
CPU time 3.28 seconds
Started Jul 04 04:30:38 PM PDT 24
Finished Jul 04 04:30:46 PM PDT 24
Peak memory 164796 kb
Host smart-cde4ef0a-934a-47f0-a590-4aaceb28da20
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3670542178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3670542178
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.3841710440
Short name T123
Test name
Test status
Simulation time 1613490000 ps
CPU time 4.21 seconds
Started Jul 04 04:30:39 PM PDT 24
Finished Jul 04 04:30:49 PM PDT 24
Peak memory 166356 kb
Host smart-cb9e041f-3b0b-4b23-ae98-9273038344c6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3841710440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.3841710440
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1622961790
Short name T135
Test name
Test status
Simulation time 1509950000 ps
CPU time 4.35 seconds
Started Jul 04 04:30:39 PM PDT 24
Finished Jul 04 04:30:49 PM PDT 24
Peak memory 164776 kb
Host smart-6c33acfc-9f35-42cc-80cd-04c519f1b370
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1622961790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1622961790
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.1601473908
Short name T140
Test name
Test status
Simulation time 1509710000 ps
CPU time 3.39 seconds
Started Jul 04 04:23:46 PM PDT 24
Finished Jul 04 04:23:54 PM PDT 24
Peak memory 164452 kb
Host smart-2df48d37-8be2-4751-b3aa-2884c55a0ac1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1601473908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.1601473908
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.875432126
Short name T127
Test name
Test status
Simulation time 1357670000 ps
CPU time 3.14 seconds
Started Jul 04 04:23:49 PM PDT 24
Finished Jul 04 04:23:56 PM PDT 24
Peak memory 164728 kb
Host smart-d7b00686-766f-4184-8998-b12752e1599a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=875432126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.875432126
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.279746474
Short name T143
Test name
Test status
Simulation time 1562150000 ps
CPU time 3.37 seconds
Started Jul 04 04:24:12 PM PDT 24
Finished Jul 04 04:24:19 PM PDT 24
Peak memory 164296 kb
Host smart-edca29d7-10eb-4d2d-9a86-f1ed03578fe4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=279746474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.279746474
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.3946284489
Short name T118
Test name
Test status
Simulation time 1404610000 ps
CPU time 3.6 seconds
Started Jul 04 04:19:36 PM PDT 24
Finished Jul 04 04:19:44 PM PDT 24
Peak memory 164772 kb
Host smart-7e9ba5b8-c29d-41e2-a074-372767fdbd6b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946284489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.3946284489
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.3803179183
Short name T139
Test name
Test status
Simulation time 1557930000 ps
CPU time 5.27 seconds
Started Jul 04 04:20:12 PM PDT 24
Finished Jul 04 04:20:23 PM PDT 24
Peak memory 164732 kb
Host smart-0849095d-71e8-43b2-a972-bc4f0ecab7f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3803179183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.3803179183
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.865254497
Short name T69
Test name
Test status
Simulation time 1593550000 ps
CPU time 4.75 seconds
Started Jul 04 04:21:37 PM PDT 24
Finished Jul 04 04:21:47 PM PDT 24
Peak memory 164828 kb
Host smart-4c9169bb-2553-497a-966a-aa2f3406dc3c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=865254497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.865254497
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4117181555
Short name T31
Test name
Test status
Simulation time 1618610000 ps
CPU time 3.29 seconds
Started Jul 04 04:23:51 PM PDT 24
Finished Jul 04 04:23:58 PM PDT 24
Peak memory 164560 kb
Host smart-55fe4c9b-2a4d-446d-a7c9-05420c374757
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4117181555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4117181555
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2805804946
Short name T49
Test name
Test status
Simulation time 1599770000 ps
CPU time 3.78 seconds
Started Jul 04 04:24:09 PM PDT 24
Finished Jul 04 04:24:18 PM PDT 24
Peak memory 164372 kb
Host smart-8928d0d7-a452-4a8f-a751-31d194cc046d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2805804946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2805804946
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.3314286598
Short name T63
Test name
Test status
Simulation time 1299790000 ps
CPU time 2.96 seconds
Started Jul 04 04:23:23 PM PDT 24
Finished Jul 04 04:23:30 PM PDT 24
Peak memory 163560 kb
Host smart-4d5cc41c-e327-4633-86f7-52ec1e3ade88
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3314286598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.3314286598
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3377144710
Short name T45
Test name
Test status
Simulation time 1348270000 ps
CPU time 3.37 seconds
Started Jul 04 04:21:10 PM PDT 24
Finished Jul 04 04:21:18 PM PDT 24
Peak memory 164756 kb
Host smart-5db7e1a0-fc50-4a25-aa4b-e0cd27bc9686
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3377144710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3377144710
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.765037675
Short name T2
Test name
Test status
Simulation time 1537290000 ps
CPU time 3.72 seconds
Started Jul 04 04:23:22 PM PDT 24
Finished Jul 04 04:23:32 PM PDT 24
Peak memory 163600 kb
Host smart-4e8a49ed-bc94-4095-9e86-e99b3a60c2d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=765037675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.765037675
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.548039330
Short name T61
Test name
Test status
Simulation time 1359510000 ps
CPU time 3.2 seconds
Started Jul 04 04:23:56 PM PDT 24
Finished Jul 04 04:24:04 PM PDT 24
Peak memory 163632 kb
Host smart-f9c7fd45-5e38-4de6-b7da-1968b3364e7f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=548039330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.548039330
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2696570742
Short name T40
Test name
Test status
Simulation time 1565730000 ps
CPU time 3.78 seconds
Started Jul 04 04:23:35 PM PDT 24
Finished Jul 04 04:23:44 PM PDT 24
Peak memory 166036 kb
Host smart-31fb7012-f729-4889-8ba8-338de72f98ad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2696570742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2696570742
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1627693219
Short name T35
Test name
Test status
Simulation time 1460510000 ps
CPU time 4.5 seconds
Started Jul 04 04:23:52 PM PDT 24
Finished Jul 04 04:24:02 PM PDT 24
Peak memory 166344 kb
Host smart-6ceefe74-b658-4b47-a2ed-2a4ba1e282b1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1627693219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1627693219
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1999272020
Short name T53
Test name
Test status
Simulation time 1441910000 ps
CPU time 3.29 seconds
Started Jul 04 04:23:21 PM PDT 24
Finished Jul 04 04:23:30 PM PDT 24
Peak memory 163816 kb
Host smart-08f6f361-e9cb-4569-9af2-cf2a9a45b36c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1999272020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1999272020
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3129860475
Short name T34
Test name
Test status
Simulation time 1356750000 ps
CPU time 3.5 seconds
Started Jul 04 04:24:56 PM PDT 24
Finished Jul 04 04:25:04 PM PDT 24
Peak memory 164756 kb
Host smart-ab84eb10-2b76-469f-b2a3-53e193506eaa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3129860475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.3129860475
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3417459559
Short name T48
Test name
Test status
Simulation time 1538090000 ps
CPU time 4.06 seconds
Started Jul 04 04:24:10 PM PDT 24
Finished Jul 04 04:24:19 PM PDT 24
Peak memory 164288 kb
Host smart-905f5d75-2926-49b3-8e83-0dd4bf277a98
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3417459559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3417459559
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.3413818718
Short name T11
Test name
Test status
Simulation time 1200210000 ps
CPU time 2.8 seconds
Started Jul 04 04:24:54 PM PDT 24
Finished Jul 04 04:25:01 PM PDT 24
Peak memory 166108 kb
Host smart-2bd388bc-ca34-4dd1-bcca-4cd0cd21e831
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3413818718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.3413818718
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.3555320966
Short name T46
Test name
Test status
Simulation time 1420610000 ps
CPU time 3.91 seconds
Started Jul 04 04:21:13 PM PDT 24
Finished Jul 04 04:21:22 PM PDT 24
Peak memory 164824 kb
Host smart-f9366bdf-ad3e-4263-9d24-59c4b4bbdd88
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3555320966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.3555320966
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3865279766
Short name T62
Test name
Test status
Simulation time 1624810000 ps
CPU time 4.03 seconds
Started Jul 04 04:23:35 PM PDT 24
Finished Jul 04 04:23:44 PM PDT 24
Peak memory 164428 kb
Host smart-e05505d4-ec0f-4dbc-aa00-c5791d179350
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3865279766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3865279766
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1767762953
Short name T33
Test name
Test status
Simulation time 1576070000 ps
CPU time 5.13 seconds
Started Jul 04 04:24:10 PM PDT 24
Finished Jul 04 04:24:21 PM PDT 24
Peak memory 164740 kb
Host smart-ce6f7442-d311-4733-adb0-c38b0301ace3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1767762953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1767762953
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2635805779
Short name T37
Test name
Test status
Simulation time 1506130000 ps
CPU time 3.48 seconds
Started Jul 04 04:23:21 PM PDT 24
Finished Jul 04 04:23:30 PM PDT 24
Peak memory 164572 kb
Host smart-4d90a82e-1ab6-43a6-80d2-19e633f0873b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2635805779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2635805779
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2805941199
Short name T51
Test name
Test status
Simulation time 1545930000 ps
CPU time 5 seconds
Started Jul 04 04:23:52 PM PDT 24
Finished Jul 04 04:24:04 PM PDT 24
Peak memory 166348 kb
Host smart-1bafa28e-f3e3-443b-8166-c6d7f48cfcfe
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2805941199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2805941199
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2290065779
Short name T67
Test name
Test status
Simulation time 1419190000 ps
CPU time 4.2 seconds
Started Jul 04 04:23:54 PM PDT 24
Finished Jul 04 04:24:03 PM PDT 24
Peak memory 164716 kb
Host smart-e75ef0ca-8b5c-4dc7-9b7c-eb5ad166cc2f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2290065779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2290065779
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2360196886
Short name T10
Test name
Test status
Simulation time 1379850000 ps
CPU time 4.42 seconds
Started Jul 04 04:20:48 PM PDT 24
Finished Jul 04 04:20:58 PM PDT 24
Peak memory 166312 kb
Host smart-56fe82d8-a643-4b71-b146-947c6b64c91a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2360196886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2360196886
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.39747250
Short name T12
Test name
Test status
Simulation time 1546710000 ps
CPU time 3.86 seconds
Started Jul 04 04:23:39 PM PDT 24
Finished Jul 04 04:23:48 PM PDT 24
Peak memory 163528 kb
Host smart-430278c1-a369-4079-8af6-9fa21f1fdd14
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=39747250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.39747250
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1505484110
Short name T58
Test name
Test status
Simulation time 1402910000 ps
CPU time 3.9 seconds
Started Jul 04 04:21:01 PM PDT 24
Finished Jul 04 04:21:10 PM PDT 24
Peak memory 164828 kb
Host smart-24954694-f741-4e9c-bf0a-412d39fc078e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1505484110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1505484110
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2975727320
Short name T60
Test name
Test status
Simulation time 1509970000 ps
CPU time 3.59 seconds
Started Jul 04 04:24:51 PM PDT 24
Finished Jul 04 04:24:59 PM PDT 24
Peak memory 164812 kb
Host smart-0214b505-d7c6-4fce-acb6-769af4cb759c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2975727320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2975727320
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2796295466
Short name T66
Test name
Test status
Simulation time 1426970000 ps
CPU time 4.67 seconds
Started Jul 04 04:21:19 PM PDT 24
Finished Jul 04 04:21:29 PM PDT 24
Peak memory 166312 kb
Host smart-4dcac633-73c7-4206-9531-9fc9b7744f54
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2796295466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2796295466
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3057156090
Short name T52
Test name
Test status
Simulation time 1240350000 ps
CPU time 3.24 seconds
Started Jul 04 04:23:39 PM PDT 24
Finished Jul 04 04:23:47 PM PDT 24
Peak memory 165044 kb
Host smart-b1014655-c4ab-40c7-97ea-05add5f36540
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3057156090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3057156090
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.505778362
Short name T65
Test name
Test status
Simulation time 1452550000 ps
CPU time 3.77 seconds
Started Jul 04 04:21:23 PM PDT 24
Finished Jul 04 04:21:31 PM PDT 24
Peak memory 164816 kb
Host smart-4ac5456f-f8e3-4c49-9bb2-2d598ad46a56
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=505778362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.505778362
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2951973390
Short name T32
Test name
Test status
Simulation time 1594130000 ps
CPU time 3.51 seconds
Started Jul 04 04:23:22 PM PDT 24
Finished Jul 04 04:23:31 PM PDT 24
Peak memory 166060 kb
Host smart-0f29df40-c428-47f9-a4fe-dbe6b39e1755
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2951973390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.2951973390
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2521160008
Short name T41
Test name
Test status
Simulation time 1573690000 ps
CPU time 3.76 seconds
Started Jul 04 04:19:39 PM PDT 24
Finished Jul 04 04:19:48 PM PDT 24
Peak memory 164828 kb
Host smart-73bf7ecd-3200-44de-8a37-b48a3ceac15d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2521160008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.2521160008
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.47780841
Short name T55
Test name
Test status
Simulation time 1345430000 ps
CPU time 4.48 seconds
Started Jul 04 04:20:09 PM PDT 24
Finished Jul 04 04:20:19 PM PDT 24
Peak memory 164812 kb
Host smart-41681bce-f571-4404-a386-a2a85ec87e9a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=47780841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.47780841
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1369972971
Short name T64
Test name
Test status
Simulation time 1505070000 ps
CPU time 4.41 seconds
Started Jul 04 04:19:52 PM PDT 24
Finished Jul 04 04:20:02 PM PDT 24
Peak memory 164800 kb
Host smart-3fa426ea-cbf6-4e26-b183-4a7c48b0f487
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1369972971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1369972971
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3509945708
Short name T38
Test name
Test status
Simulation time 1313210000 ps
CPU time 4.75 seconds
Started Jul 04 04:20:28 PM PDT 24
Finished Jul 04 04:20:39 PM PDT 24
Peak memory 164744 kb
Host smart-e84bb66a-746f-4464-9b39-c4ca4644bfe7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3509945708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.3509945708
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2809803832
Short name T39
Test name
Test status
Simulation time 1299950000 ps
CPU time 3.5 seconds
Started Jul 04 04:20:36 PM PDT 24
Finished Jul 04 04:20:43 PM PDT 24
Peak memory 164780 kb
Host smart-c9b9ce6f-c40f-4a87-91b8-a91784256d46
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2809803832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2809803832
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3981682916
Short name T42
Test name
Test status
Simulation time 1273450000 ps
CPU time 3.15 seconds
Started Jul 04 04:24:05 PM PDT 24
Finished Jul 04 04:24:12 PM PDT 24
Peak memory 166200 kb
Host smart-b0f087a1-ddc3-4fbd-affd-06fa9eb4c9fa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981682916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3981682916
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.905481507
Short name T56
Test name
Test status
Simulation time 1468210000 ps
CPU time 3.53 seconds
Started Jul 04 04:23:51 PM PDT 24
Finished Jul 04 04:23:59 PM PDT 24
Peak memory 164796 kb
Host smart-bfa97099-e14e-4f21-b764-9e2f95c6c998
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905481507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.905481507
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.3783399600
Short name T9
Test name
Test status
Simulation time 1551750000 ps
CPU time 4.65 seconds
Started Jul 04 04:20:35 PM PDT 24
Finished Jul 04 04:20:46 PM PDT 24
Peak memory 164812 kb
Host smart-059da1a2-8749-48b3-a307-7f9ecd2f7ed3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3783399600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.3783399600
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.780650493
Short name T70
Test name
Test status
Simulation time 1561430000 ps
CPU time 4.72 seconds
Started Jul 04 04:20:36 PM PDT 24
Finished Jul 04 04:20:46 PM PDT 24
Peak memory 164836 kb
Host smart-632f388e-1dc7-4c0b-a877-3b921e04f955
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=780650493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.780650493
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2131042934
Short name T43
Test name
Test status
Simulation time 1392430000 ps
CPU time 4.57 seconds
Started Jul 04 04:22:08 PM PDT 24
Finished Jul 04 04:22:18 PM PDT 24
Peak memory 164824 kb
Host smart-04f7847f-00a8-4cd6-a30d-88fe2d7e8585
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2131042934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2131042934
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.386019518
Short name T1
Test name
Test status
Simulation time 1559830000 ps
CPU time 5.03 seconds
Started Jul 04 04:19:31 PM PDT 24
Finished Jul 04 04:19:42 PM PDT 24
Peak memory 164620 kb
Host smart-9976773b-08a5-4cf0-bb38-ad002d60c3ac
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=386019518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.386019518
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.2312222354
Short name T54
Test name
Test status
Simulation time 1368410000 ps
CPU time 3.47 seconds
Started Jul 04 04:19:38 PM PDT 24
Finished Jul 04 04:19:46 PM PDT 24
Peak memory 164808 kb
Host smart-f1f981fc-02ee-4bfe-8cf4-e5cdfea3422f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2312222354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.2312222354
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2273688585
Short name T3
Test name
Test status
Simulation time 1497890000 ps
CPU time 4.95 seconds
Started Jul 04 04:19:38 PM PDT 24
Finished Jul 04 04:19:48 PM PDT 24
Peak memory 164744 kb
Host smart-118a4d88-8156-4d23-9f01-ec31e072cf8e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2273688585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2273688585
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3793413833
Short name T50
Test name
Test status
Simulation time 1447890000 ps
CPU time 3.72 seconds
Started Jul 04 04:20:25 PM PDT 24
Finished Jul 04 04:20:34 PM PDT 24
Peak memory 165096 kb
Host smart-5e918456-0f76-41c3-8912-117211f22c82
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3793413833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.3793413833
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1066946525
Short name T7
Test name
Test status
Simulation time 1389750000 ps
CPU time 3.43 seconds
Started Jul 04 04:19:40 PM PDT 24
Finished Jul 04 04:19:47 PM PDT 24
Peak memory 164744 kb
Host smart-0da1a85c-1392-48d1-8789-9b272ae35ae6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1066946525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1066946525
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.3701582339
Short name T59
Test name
Test status
Simulation time 1485950000 ps
CPU time 3.55 seconds
Started Jul 04 04:23:53 PM PDT 24
Finished Jul 04 04:24:01 PM PDT 24
Peak memory 164792 kb
Host smart-c89394ce-5eee-4544-84f4-64b6a4bf67ad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3701582339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.3701582339
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2802480042
Short name T47
Test name
Test status
Simulation time 1124790000 ps
CPU time 3.76 seconds
Started Jul 04 04:21:59 PM PDT 24
Finished Jul 04 04:22:07 PM PDT 24
Peak memory 164824 kb
Host smart-fa3b361b-6d23-4ab2-b8d7-1264b9709772
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2802480042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2802480042
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3226731613
Short name T68
Test name
Test status
Simulation time 1446450000 ps
CPU time 3.69 seconds
Started Jul 04 04:24:56 PM PDT 24
Finished Jul 04 04:25:05 PM PDT 24
Peak memory 164812 kb
Host smart-d7cd32ac-b1fd-49ca-8ad5-90e427a415c1
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3226731613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3226731613
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2724584583
Short name T44
Test name
Test status
Simulation time 1352410000 ps
CPU time 3.42 seconds
Started Jul 04 04:19:41 PM PDT 24
Finished Jul 04 04:19:49 PM PDT 24
Peak memory 164748 kb
Host smart-3241517b-91d9-4b5f-bd56-8445c35536b6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2724584583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2724584583
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1880250166
Short name T13
Test name
Test status
Simulation time 1602870000 ps
CPU time 4.32 seconds
Started Jul 04 04:21:31 PM PDT 24
Finished Jul 04 04:21:41 PM PDT 24
Peak memory 164864 kb
Host smart-646617ef-a842-46a3-8d11-2786084a0edd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1880250166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1880250166
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.613585364
Short name T57
Test name
Test status
Simulation time 1422290000 ps
CPU time 3.12 seconds
Started Jul 04 04:20:42 PM PDT 24
Finished Jul 04 04:20:49 PM PDT 24
Peak memory 164696 kb
Host smart-2a5612ff-b89b-4609-abbd-50975e495a41
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=613585364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.613585364
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3249338254
Short name T36
Test name
Test status
Simulation time 1532830000 ps
CPU time 4.23 seconds
Started Jul 04 04:20:56 PM PDT 24
Finished Jul 04 04:21:05 PM PDT 24
Peak memory 164768 kb
Host smart-483dcb8f-66af-454e-81b9-5eb362520d84
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3249338254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3249338254
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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