Design Hierarchy
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hierarchy
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modlist
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tests
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asserts
NAME
SCORE
LINE
COND
TOGGLE
FSM
BRANCH
ASSERT
prim_lfsr_tb
98.31
100.00
96.55
100.00
100.00
95.00
gen_duts[8].i_prim_lfsr
98.31
100.00
96.55
100.00
100.00
95.00
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%