Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.800648780
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.126601865
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2756490694

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1635163715
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2549569583
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3944249225
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4138007579
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.311612619
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.600775077
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.475402225
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2585467687
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2406919898
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.14020714
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3478629512
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1307850418
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3787141706
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4137725036
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1705094559
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1035055512
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3109040822
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2115684510
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.728981110
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1084703893
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3169318290
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2354432345
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3806729215
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3650207917
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1132858326
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1834484105
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4236603075
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.503788137
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2317464358
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.377570855
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1932348115
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3926344760
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.257994591
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2820688557
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4027281021
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.245606287
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.354727000
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4179818094
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.499463154
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3774163386
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3355521915
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1044758441
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1475274621
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4075632432
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.376433653
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3265462803
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.180944264
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3695317909
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1328866314
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3261976361
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3602265349
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3650256465
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3176330434
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3750168115
/workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1350434354
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3024316796
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1810390712
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.14051320
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3901458890
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1037440767
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1489924340
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3288937607
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2208211356
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.919445857
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1291986854
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3315374052
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1087855806
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.576010787
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2983527039
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1966065689
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2781919321
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.804583287
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1053160514
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3880412037
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.279012612
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2912457472
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1148309196
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1341093963
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1765360697
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2836583747
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.870483160
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4243597179
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.731933501
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2420565670
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.620030550
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3747739430
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3065190181
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3295323187
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1923620379
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4189723194
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1719680364
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2186953039
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3938411372
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1817720692
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1133316822
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.753326426
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3580283960
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1343442863
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4285080345
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4036155206
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1684793505
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1907247594
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3659813617
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1191876470
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3118126908
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.113153753
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3916342176
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4044004668
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3573501475
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3455511536
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1082025419
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.557265889
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1739978219
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3805156084
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3368122062
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1421799666
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1708588534
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.517201350
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.813689787
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3688328277
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.638482118
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2432256919
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.345377484
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2083338488
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4233345658
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.435184337
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1580819516
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.974405461
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.674258598
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1620436186
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.243179744
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3394028445
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.80518325
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1289216823
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3253798244
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.934168954
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2519609330
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1406057529
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3583922255
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1171343853
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3732637978
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2372889984
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2797034586
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.769159775
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3728422137
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3363059139
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1955153017
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2044979965
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2368304433
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1542924883
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.409634465
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3333803368
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1750377523
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1722355378
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2546692658
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1893654112
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.31620088
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2388595130
/workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.452678317
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3391943865
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1978425804
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1995174325
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.962671321
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1617881406
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2721457528
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.827407704
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2074482034
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.327763658
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3788970076
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2774296059
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2814137876
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1565876430
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1456747763
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4207786483
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3492891240
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1900938752
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1756151450
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.947820307
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.889762710
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2609520479
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2486935282
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3182628964
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.103581546
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.201964612
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2041227590
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1517923676
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4236891206
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2000097608
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2454726851
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1258708641
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.419943416
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.795147746
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1638103446
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.308499028
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1265708209
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.548306008
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2177710836



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.419943416 Jul 14 06:00:27 PM PDT 24 Jul 14 06:00:37 PM PDT 24 1532990000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.827407704 Jul 14 06:00:21 PM PDT 24 Jul 14 06:00:31 PM PDT 24 1585630000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.947820307 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:30 PM PDT 24 1537110000 ps
T7 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1995174325 Jul 14 06:00:17 PM PDT 24 Jul 14 06:00:30 PM PDT 24 1521130000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.962671321 Jul 14 06:00:17 PM PDT 24 Jul 14 06:00:27 PM PDT 24 1461210000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.103581546 Jul 14 06:00:27 PM PDT 24 Jul 14 06:00:37 PM PDT 24 1308790000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1722355378 Jul 14 06:00:21 PM PDT 24 Jul 14 06:00:32 PM PDT 24 1359430000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3788970076 Jul 14 06:00:21 PM PDT 24 Jul 14 06:00:33 PM PDT 24 1519090000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.800648780 Jul 14 06:00:14 PM PDT 24 Jul 14 06:00:24 PM PDT 24 1328810000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1638103446 Jul 14 06:00:13 PM PDT 24 Jul 14 06:00:24 PM PDT 24 1436230000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1750377523 Jul 14 06:00:09 PM PDT 24 Jul 14 06:00:21 PM PDT 24 1536710000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2388595130 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:29 PM PDT 24 1313470000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2074482034 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:32 PM PDT 24 1460630000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1517923676 Jul 14 06:00:27 PM PDT 24 Jul 14 06:00:39 PM PDT 24 1379530000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2546692658 Jul 14 06:00:18 PM PDT 24 Jul 14 06:00:33 PM PDT 24 1528970000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1756151450 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:33 PM PDT 24 1670590000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1456747763 Jul 14 06:00:20 PM PDT 24 Jul 14 06:00:30 PM PDT 24 1238310000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1258708641 Jul 14 06:00:29 PM PDT 24 Jul 14 06:00:39 PM PDT 24 1281550000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3333803368 Jul 14 06:00:14 PM PDT 24 Jul 14 06:00:25 PM PDT 24 1208310000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.452678317 Jul 14 06:00:20 PM PDT 24 Jul 14 06:00:33 PM PDT 24 1457330000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2486935282 Jul 14 06:00:20 PM PDT 24 Jul 14 06:00:34 PM PDT 24 1649650000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2041227590 Jul 14 06:00:27 PM PDT 24 Jul 14 06:00:37 PM PDT 24 1160870000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4207786483 Jul 14 06:00:20 PM PDT 24 Jul 14 06:00:32 PM PDT 24 1503110000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1265708209 Jul 14 06:00:15 PM PDT 24 Jul 14 06:00:25 PM PDT 24 1499650000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1978425804 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:33 PM PDT 24 1496750000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.327763658 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:30 PM PDT 24 1268450000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2609520479 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:33 PM PDT 24 1628630000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1893654112 Jul 14 06:00:20 PM PDT 24 Jul 14 06:00:30 PM PDT 24 1320270000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2774296059 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:33 PM PDT 24 1442050000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3182628964 Jul 14 06:00:14 PM PDT 24 Jul 14 06:00:25 PM PDT 24 1554410000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3492891240 Jul 14 06:00:20 PM PDT 24 Jul 14 06:00:33 PM PDT 24 1487690000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1565876430 Jul 14 06:00:18 PM PDT 24 Jul 14 06:00:31 PM PDT 24 1497170000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.795147746 Jul 14 06:00:27 PM PDT 24 Jul 14 06:00:39 PM PDT 24 1486730000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1617881406 Jul 14 06:00:18 PM PDT 24 Jul 14 06:00:30 PM PDT 24 1512690000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2000097608 Jul 14 06:00:24 PM PDT 24 Jul 14 06:00:37 PM PDT 24 1468230000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1900938752 Jul 14 06:00:20 PM PDT 24 Jul 14 06:00:31 PM PDT 24 1569570000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2177710836 Jul 14 06:00:12 PM PDT 24 Jul 14 06:00:22 PM PDT 24 1468370000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.548306008 Jul 14 06:00:13 PM PDT 24 Jul 14 06:00:24 PM PDT 24 1497010000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2721457528 Jul 14 06:00:17 PM PDT 24 Jul 14 06:00:28 PM PDT 24 1420970000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.409634465 Jul 14 06:00:12 PM PDT 24 Jul 14 06:00:21 PM PDT 24 1416170000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2368304433 Jul 14 06:00:14 PM PDT 24 Jul 14 06:00:25 PM PDT 24 1328290000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2454726851 Jul 14 06:00:27 PM PDT 24 Jul 14 06:00:41 PM PDT 24 1564910000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.201964612 Jul 14 06:00:26 PM PDT 24 Jul 14 06:00:39 PM PDT 24 1564590000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.31620088 Jul 14 06:00:18 PM PDT 24 Jul 14 06:00:28 PM PDT 24 1464370000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3391943865 Jul 14 06:00:14 PM PDT 24 Jul 14 06:00:26 PM PDT 24 1402310000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.308499028 Jul 14 06:00:11 PM PDT 24 Jul 14 06:00:21 PM PDT 24 1512430000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4236891206 Jul 14 06:00:29 PM PDT 24 Jul 14 06:00:39 PM PDT 24 1462690000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1542924883 Jul 14 06:00:12 PM PDT 24 Jul 14 06:00:23 PM PDT 24 1557450000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2814137876 Jul 14 06:00:12 PM PDT 24 Jul 14 06:00:23 PM PDT 24 1550450000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.889762710 Jul 14 06:00:19 PM PDT 24 Jul 14 06:00:32 PM PDT 24 1489230000 ps
T4 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1084703893 Jul 14 06:00:03 PM PDT 24 Jul 14 06:34:14 PM PDT 24 336672690000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2317464358 Jul 14 06:00:07 PM PDT 24 Jul 14 06:30:44 PM PDT 24 336494050000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1035055512 Jul 14 06:00:02 PM PDT 24 Jul 14 06:37:12 PM PDT 24 336771030000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1307850418 Jul 14 05:59:51 PM PDT 24 Jul 14 06:36:54 PM PDT 24 336790030000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3944249225 Jul 14 05:59:57 PM PDT 24 Jul 14 06:37:56 PM PDT 24 336458490000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.126601865 Jul 14 05:59:58 PM PDT 24 Jul 14 06:37:03 PM PDT 24 337123710000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4027281021 Jul 14 06:00:04 PM PDT 24 Jul 14 06:32:18 PM PDT 24 336942870000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1705094559 Jul 14 05:59:59 PM PDT 24 Jul 14 06:29:47 PM PDT 24 336333850000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2820688557 Jul 14 05:59:52 PM PDT 24 Jul 14 06:30:35 PM PDT 24 336318730000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2585467687 Jul 14 05:59:59 PM PDT 24 Jul 14 06:34:02 PM PDT 24 336417130000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3926344760 Jul 14 06:00:05 PM PDT 24 Jul 14 06:31:20 PM PDT 24 336441870000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1328866314 Jul 14 05:59:51 PM PDT 24 Jul 14 06:34:30 PM PDT 24 336853530000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3650207917 Jul 14 06:00:06 PM PDT 24 Jul 14 06:30:36 PM PDT 24 336930790000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3109040822 Jul 14 06:00:01 PM PDT 24 Jul 14 06:31:46 PM PDT 24 336615610000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.600775077 Jul 14 05:59:59 PM PDT 24 Jul 14 06:31:57 PM PDT 24 336445030000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3265462803 Jul 14 05:59:49 PM PDT 24 Jul 14 06:34:11 PM PDT 24 336439170000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4236603075 Jul 14 06:00:05 PM PDT 24 Jul 14 06:35:27 PM PDT 24 336418470000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1132858326 Jul 14 06:00:05 PM PDT 24 Jul 14 06:32:03 PM PDT 24 336327050000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3774163386 Jul 14 06:00:11 PM PDT 24 Jul 14 06:32:02 PM PDT 24 336933430000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.311612619 Jul 14 05:59:59 PM PDT 24 Jul 14 06:30:32 PM PDT 24 336663050000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1475274621 Jul 14 06:00:11 PM PDT 24 Jul 14 06:32:31 PM PDT 24 336588730000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4137725036 Jul 14 05:59:59 PM PDT 24 Jul 14 06:31:53 PM PDT 24 337048750000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4138007579 Jul 14 05:59:57 PM PDT 24 Jul 14 06:33:13 PM PDT 24 336886910000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2115684510 Jul 14 05:59:59 PM PDT 24 Jul 14 06:31:34 PM PDT 24 336377130000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.180944264 Jul 14 05:59:56 PM PDT 24 Jul 14 06:36:36 PM PDT 24 337071090000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.503788137 Jul 14 06:00:03 PM PDT 24 Jul 14 06:29:30 PM PDT 24 336867030000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4179818094 Jul 14 06:00:11 PM PDT 24 Jul 14 06:34:29 PM PDT 24 336552230000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.475402225 Jul 14 06:00:00 PM PDT 24 Jul 14 06:39:44 PM PDT 24 337054490000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3695317909 Jul 14 05:59:51 PM PDT 24 Jul 14 06:37:08 PM PDT 24 337138170000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1635163715 Jul 14 05:59:53 PM PDT 24 Jul 14 06:33:28 PM PDT 24 336343950000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3478629512 Jul 14 05:59:58 PM PDT 24 Jul 14 06:32:20 PM PDT 24 336948230000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.354727000 Jul 14 06:00:11 PM PDT 24 Jul 14 06:41:15 PM PDT 24 336520970000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3169318290 Jul 14 06:00:07 PM PDT 24 Jul 14 06:35:20 PM PDT 24 337025770000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1834484105 Jul 14 06:00:04 PM PDT 24 Jul 14 06:33:46 PM PDT 24 337042550000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.14020714 Jul 14 05:59:58 PM PDT 24 Jul 14 06:35:04 PM PDT 24 336720490000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2354432345 Jul 14 06:00:06 PM PDT 24 Jul 14 06:35:13 PM PDT 24 336611850000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4075632432 Jul 14 06:00:12 PM PDT 24 Jul 14 06:27:48 PM PDT 24 336646190000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.728981110 Jul 14 05:59:58 PM PDT 24 Jul 14 06:34:31 PM PDT 24 336876990000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1932348115 Jul 14 06:00:04 PM PDT 24 Jul 14 06:30:16 PM PDT 24 336543770000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.499463154 Jul 14 06:00:10 PM PDT 24 Jul 14 06:35:56 PM PDT 24 337034610000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1044758441 Jul 14 06:00:14 PM PDT 24 Jul 14 06:40:05 PM PDT 24 336679110000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.377570855 Jul 14 06:00:04 PM PDT 24 Jul 14 06:37:09 PM PDT 24 336995510000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.257994591 Jul 14 06:00:04 PM PDT 24 Jul 14 06:36:24 PM PDT 24 336979690000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.245606287 Jul 14 06:00:12 PM PDT 24 Jul 14 06:35:58 PM PDT 24 336632810000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3355521915 Jul 14 06:00:11 PM PDT 24 Jul 14 06:32:12 PM PDT 24 336522650000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.376433653 Jul 14 05:59:55 PM PDT 24 Jul 14 06:36:30 PM PDT 24 336546210000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2406919898 Jul 14 05:59:57 PM PDT 24 Jul 14 06:41:02 PM PDT 24 336560550000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2549569583 Jul 14 05:59:56 PM PDT 24 Jul 14 06:36:28 PM PDT 24 336715010000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3787141706 Jul 14 05:59:59 PM PDT 24 Jul 14 06:34:50 PM PDT 24 336590270000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3806729215 Jul 14 05:59:52 PM PDT 24 Jul 14 06:29:35 PM PDT 24 336689610000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1708588534 Jul 14 04:27:33 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1509850000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1620436186 Jul 14 04:27:37 PM PDT 24 Jul 14 04:27:45 PM PDT 24 1388510000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.638482118 Jul 14 04:27:37 PM PDT 24 Jul 14 04:27:46 PM PDT 24 1535190000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3728422137 Jul 14 04:21:45 PM PDT 24 Jul 14 04:21:52 PM PDT 24 1136370000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4044004668 Jul 14 04:17:55 PM PDT 24 Jul 14 04:18:02 PM PDT 24 1341270000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3363059139 Jul 14 04:17:52 PM PDT 24 Jul 14 04:17:59 PM PDT 24 1263750000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.674258598 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1463530000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1580819516 Jul 14 04:27:35 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1341570000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.80518325 Jul 14 04:21:45 PM PDT 24 Jul 14 04:21:53 PM PDT 24 1489150000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3368122062 Jul 14 04:27:35 PM PDT 24 Jul 14 04:27:45 PM PDT 24 1534510000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1191876470 Jul 14 04:20:42 PM PDT 24 Jul 14 04:20:49 PM PDT 24 1085170000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3455511536 Jul 14 04:18:53 PM PDT 24 Jul 14 04:19:01 PM PDT 24 1509790000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2432256919 Jul 14 04:18:10 PM PDT 24 Jul 14 04:18:18 PM PDT 24 1517510000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1289216823 Jul 14 04:27:37 PM PDT 24 Jul 14 04:27:47 PM PDT 24 1492310000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3659813617 Jul 14 04:22:41 PM PDT 24 Jul 14 04:22:52 PM PDT 24 1282930000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1907247594 Jul 14 04:22:17 PM PDT 24 Jul 14 04:22:27 PM PDT 24 1606610000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3688328277 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:45 PM PDT 24 1373710000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1739978219 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:45 PM PDT 24 1556250000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2083338488 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:47 PM PDT 24 1585470000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3732637978 Jul 14 04:27:35 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1382870000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.345377484 Jul 14 04:27:35 PM PDT 24 Jul 14 04:27:45 PM PDT 24 1495670000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.813689787 Jul 14 04:27:34 PM PDT 24 Jul 14 04:27:46 PM PDT 24 1420170000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2044979965 Jul 14 04:18:54 PM PDT 24 Jul 14 04:19:05 PM PDT 24 1543430000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.113153753 Jul 14 04:22:42 PM PDT 24 Jul 14 04:22:52 PM PDT 24 1163930000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2372889984 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1398210000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1171343853 Jul 14 04:27:33 PM PDT 24 Jul 14 04:27:48 PM PDT 24 1536030000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3916342176 Jul 14 04:22:19 PM PDT 24 Jul 14 04:22:28 PM PDT 24 1637650000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4285080345 Jul 14 04:21:59 PM PDT 24 Jul 14 04:22:09 PM PDT 24 1540170000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1421799666 Jul 14 04:27:37 PM PDT 24 Jul 14 04:27:47 PM PDT 24 1647870000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1406057529 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1462130000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4233345658 Jul 14 04:27:35 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1488570000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2519609330 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:51 PM PDT 24 1535330000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3583922255 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1373090000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.557265889 Jul 14 04:27:35 PM PDT 24 Jul 14 04:27:43 PM PDT 24 1497350000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3394028445 Jul 14 04:27:39 PM PDT 24 Jul 14 04:27:46 PM PDT 24 1134470000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1082025419 Jul 14 04:22:29 PM PDT 24 Jul 14 04:22:38 PM PDT 24 1280130000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3253798244 Jul 14 04:27:35 PM PDT 24 Jul 14 04:27:48 PM PDT 24 1499790000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3573501475 Jul 14 04:21:57 PM PDT 24 Jul 14 04:22:06 PM PDT 24 1551650000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.243179744 Jul 14 04:27:36 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1472850000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.974405461 Jul 14 04:27:34 PM PDT 24 Jul 14 04:27:42 PM PDT 24 1527470000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2797034586 Jul 14 04:27:44 PM PDT 24 Jul 14 04:27:52 PM PDT 24 1378470000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1684793505 Jul 14 04:22:32 PM PDT 24 Jul 14 04:22:41 PM PDT 24 1326170000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.517201350 Jul 14 04:27:39 PM PDT 24 Jul 14 04:27:48 PM PDT 24 1536790000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.435184337 Jul 14 04:27:34 PM PDT 24 Jul 14 04:27:46 PM PDT 24 1482850000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.934168954 Jul 14 04:27:35 PM PDT 24 Jul 14 04:27:44 PM PDT 24 1445470000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3805156084 Jul 14 04:27:37 PM PDT 24 Jul 14 04:27:51 PM PDT 24 1592130000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1955153017 Jul 14 04:21:44 PM PDT 24 Jul 14 04:21:52 PM PDT 24 1447190000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4036155206 Jul 14 04:21:04 PM PDT 24 Jul 14 04:21:12 PM PDT 24 1598710000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3118126908 Jul 14 04:22:42 PM PDT 24 Jul 14 04:22:54 PM PDT 24 1569590000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.769159775 Jul 14 04:18:44 PM PDT 24 Jul 14 04:18:56 PM PDT 24 1443650000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2186953039 Jul 14 06:09:46 PM PDT 24 Jul 14 06:42:40 PM PDT 24 336556710000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1966065689 Jul 14 06:09:44 PM PDT 24 Jul 14 06:39:10 PM PDT 24 336330810000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.870483160 Jul 14 06:09:42 PM PDT 24 Jul 14 06:41:50 PM PDT 24 336803850000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1343442863 Jul 14 06:09:44 PM PDT 24 Jul 14 06:48:49 PM PDT 24 336513710000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1087855806 Jul 14 06:09:41 PM PDT 24 Jul 14 06:39:56 PM PDT 24 336580510000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.620030550 Jul 14 06:09:49 PM PDT 24 Jul 14 06:43:31 PM PDT 24 336673430000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2756490694 Jul 14 06:09:39 PM PDT 24 Jul 14 06:42:06 PM PDT 24 336385690000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1817720692 Jul 14 06:09:42 PM PDT 24 Jul 14 06:46:26 PM PDT 24 336871130000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.731933501 Jul 14 06:09:36 PM PDT 24 Jul 14 06:41:24 PM PDT 24 336613950000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1923620379 Jul 14 06:09:45 PM PDT 24 Jul 14 06:45:42 PM PDT 24 336951570000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.919445857 Jul 14 06:09:42 PM PDT 24 Jul 14 06:46:06 PM PDT 24 336431070000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2781919321 Jul 14 06:09:42 PM PDT 24 Jul 14 06:38:55 PM PDT 24 336363130000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3065190181 Jul 14 06:09:46 PM PDT 24 Jul 14 06:46:05 PM PDT 24 336556810000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.576010787 Jul 14 06:09:41 PM PDT 24 Jul 14 06:42:26 PM PDT 24 336641830000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1350434354 Jul 14 06:09:35 PM PDT 24 Jul 14 06:40:37 PM PDT 24 336462370000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3024316796 Jul 14 06:09:38 PM PDT 24 Jul 14 06:41:22 PM PDT 24 336848810000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1765360697 Jul 14 06:09:41 PM PDT 24 Jul 14 06:39:25 PM PDT 24 337104870000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.279012612 Jul 14 06:09:41 PM PDT 24 Jul 14 06:43:24 PM PDT 24 336967850000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.14051320 Jul 14 06:09:44 PM PDT 24 Jul 14 06:39:24 PM PDT 24 337069730000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2983527039 Jul 14 06:09:43 PM PDT 24 Jul 14 06:42:07 PM PDT 24 336351910000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1291986854 Jul 14 06:09:42 PM PDT 24 Jul 14 06:44:21 PM PDT 24 336676290000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1037440767 Jul 14 06:09:45 PM PDT 24 Jul 14 06:46:10 PM PDT 24 336895650000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1489924340 Jul 14 06:09:42 PM PDT 24 Jul 14 06:48:30 PM PDT 24 336524650000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3747739430 Jul 14 06:09:43 PM PDT 24 Jul 14 06:41:24 PM PDT 24 336663210000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3750168115 Jul 14 06:09:35 PM PDT 24 Jul 14 06:43:15 PM PDT 24 336519950000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3580283960 Jul 14 06:09:37 PM PDT 24 Jul 14 06:49:31 PM PDT 24 336601050000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2836583747 Jul 14 06:09:43 PM PDT 24 Jul 14 06:41:34 PM PDT 24 336824470000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2420565670 Jul 14 06:09:41 PM PDT 24 Jul 14 06:42:31 PM PDT 24 336967490000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3261976361 Jul 14 06:09:38 PM PDT 24 Jul 14 06:41:15 PM PDT 24 336417890000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3295323187 Jul 14 06:09:42 PM PDT 24 Jul 14 06:45:47 PM PDT 24 336911850000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1341093963 Jul 14 06:09:46 PM PDT 24 Jul 14 06:42:46 PM PDT 24 337029750000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4243597179 Jul 14 06:09:43 PM PDT 24 Jul 14 06:38:41 PM PDT 24 336588650000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3901458890 Jul 14 06:09:38 PM PDT 24 Jul 14 06:46:22 PM PDT 24 336622710000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3602265349 Jul 14 06:09:40 PM PDT 24 Jul 14 06:46:22 PM PDT 24 336321850000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3938411372 Jul 14 06:09:47 PM PDT 24 Jul 14 06:42:12 PM PDT 24 336543850000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3880412037 Jul 14 06:09:42 PM PDT 24 Jul 14 06:48:28 PM PDT 24 336827610000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.804583287 Jul 14 06:09:37 PM PDT 24 Jul 14 06:40:33 PM PDT 24 336391630000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.753326426 Jul 14 06:09:36 PM PDT 24 Jul 14 06:42:16 PM PDT 24 336986670000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1719680364 Jul 14 06:09:49 PM PDT 24 Jul 14 06:43:31 PM PDT 24 336429730000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4189723194 Jul 14 06:09:39 PM PDT 24 Jul 14 06:41:53 PM PDT 24 336608990000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3288937607 Jul 14 06:09:36 PM PDT 24 Jul 14 06:34:21 PM PDT 24 336836130000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3315374052 Jul 14 06:09:40 PM PDT 24 Jul 14 06:44:18 PM PDT 24 336898790000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1053160514 Jul 14 06:09:39 PM PDT 24 Jul 14 06:37:22 PM PDT 24 337148410000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1133316822 Jul 14 06:09:40 PM PDT 24 Jul 14 06:48:43 PM PDT 24 336953550000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3176330434 Jul 14 06:09:37 PM PDT 24 Jul 14 06:43:07 PM PDT 24 336377250000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3650256465 Jul 14 06:09:38 PM PDT 24 Jul 14 06:49:33 PM PDT 24 337028970000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2912457472 Jul 14 06:09:47 PM PDT 24 Jul 14 06:45:26 PM PDT 24 336383750000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1810390712 Jul 14 06:09:37 PM PDT 24 Jul 14 06:40:46 PM PDT 24 336448370000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2208211356 Jul 14 06:09:39 PM PDT 24 Jul 14 06:49:44 PM PDT 24 336371610000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1148309196 Jul 14 06:09:44 PM PDT 24 Jul 14 06:48:48 PM PDT 24 336368770000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.800648780
Short name T12
Test name
Test status
Simulation time 1328810000 ps
CPU time 4.08 seconds
Started Jul 14 06:00:14 PM PDT 24
Finished Jul 14 06:00:24 PM PDT 24
Peak memory 164784 kb
Host smart-d412e5ef-d65e-4250-b966-17ea43425739
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=800648780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.800648780
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.126601865
Short name T16
Test name
Test status
Simulation time 337123710000 ps
CPU time 895.96 seconds
Started Jul 14 05:59:58 PM PDT 24
Finished Jul 14 06:37:03 PM PDT 24
Peak memory 160768 kb
Host smart-05b7880c-8481-4174-b37b-4b3ed0dbbbdb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=126601865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.126601865
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.2756490694
Short name T27
Test name
Test status
Simulation time 336385690000 ps
CPU time 795.38 seconds
Started Jul 14 06:09:39 PM PDT 24
Finished Jul 14 06:42:06 PM PDT 24
Peak memory 160796 kb
Host smart-7885f483-e2ab-4c66-9acb-61b186a4f8e0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2756490694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.2756490694
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.1635163715
Short name T90
Test name
Test status
Simulation time 336343950000 ps
CPU time 809.01 seconds
Started Jul 14 05:59:53 PM PDT 24
Finished Jul 14 06:33:28 PM PDT 24
Peak memory 160620 kb
Host smart-5e98b39f-ebca-4694-8838-9bbd6671baf5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1635163715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.1635163715
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2549569583
Short name T108
Test name
Test status
Simulation time 336715010000 ps
CPU time 871.65 seconds
Started Jul 14 05:59:56 PM PDT 24
Finished Jul 14 06:36:28 PM PDT 24
Peak memory 160788 kb
Host smart-a09f9d17-daee-4242-929c-9ece6bde3599
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2549569583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2549569583
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3944249225
Short name T15
Test name
Test status
Simulation time 336458490000 ps
CPU time 945.04 seconds
Started Jul 14 05:59:57 PM PDT 24
Finished Jul 14 06:37:56 PM PDT 24
Peak memory 160776 kb
Host smart-0e40ff98-57f4-4499-abf8-f65f45106df7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3944249225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.3944249225
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4138007579
Short name T83
Test name
Test status
Simulation time 336886910000 ps
CPU time 819.47 seconds
Started Jul 14 05:59:57 PM PDT 24
Finished Jul 14 06:33:13 PM PDT 24
Peak memory 160724 kb
Host smart-db13b44f-404d-4436-b823-5b7c658839c7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4138007579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.4138007579
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.311612619
Short name T80
Test name
Test status
Simulation time 336663050000 ps
CPU time 741.41 seconds
Started Jul 14 05:59:59 PM PDT 24
Finished Jul 14 06:30:32 PM PDT 24
Peak memory 160720 kb
Host smart-fd18868f-a3cd-425c-8100-c0f0d4d702e6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=311612619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.311612619
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.600775077
Short name T75
Test name
Test status
Simulation time 336445030000 ps
CPU time 796.63 seconds
Started Jul 14 05:59:59 PM PDT 24
Finished Jul 14 06:31:57 PM PDT 24
Peak memory 160880 kb
Host smart-4cccd171-a63e-452e-8d29-00c0e5b42470
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=600775077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.600775077
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.475402225
Short name T88
Test name
Test status
Simulation time 337054490000 ps
CPU time 973.2 seconds
Started Jul 14 06:00:00 PM PDT 24
Finished Jul 14 06:39:44 PM PDT 24
Peak memory 160784 kb
Host smart-83dc50ea-8c72-4c2c-979d-78b977756aee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=475402225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.475402225
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2585467687
Short name T20
Test name
Test status
Simulation time 336417130000 ps
CPU time 842.47 seconds
Started Jul 14 05:59:59 PM PDT 24
Finished Jul 14 06:34:02 PM PDT 24
Peak memory 160764 kb
Host smart-a21721a7-1d4f-46e1-91ba-3a48366d2d96
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2585467687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2585467687
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2406919898
Short name T107
Test name
Test status
Simulation time 336560550000 ps
CPU time 978.23 seconds
Started Jul 14 05:59:57 PM PDT 24
Finished Jul 14 06:41:02 PM PDT 24
Peak memory 160804 kb
Host smart-b1e55f56-c42b-4ca3-bf8f-a55d984b221d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2406919898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2406919898
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.14020714
Short name T95
Test name
Test status
Simulation time 336720490000 ps
CPU time 865.59 seconds
Started Jul 14 05:59:58 PM PDT 24
Finished Jul 14 06:35:04 PM PDT 24
Peak memory 160776 kb
Host smart-cc5ef305-3444-49ea-86d1-a5780aa4dee5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=14020714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.14020714
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.3478629512
Short name T91
Test name
Test status
Simulation time 336948230000 ps
CPU time 792.47 seconds
Started Jul 14 05:59:58 PM PDT 24
Finished Jul 14 06:32:20 PM PDT 24
Peak memory 160796 kb
Host smart-938bf0fc-65b2-4b9f-a631-6bf346201c27
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3478629512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.3478629512
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1307850418
Short name T14
Test name
Test status
Simulation time 336790030000 ps
CPU time 902.27 seconds
Started Jul 14 05:59:51 PM PDT 24
Finished Jul 14 06:36:54 PM PDT 24
Peak memory 160768 kb
Host smart-e79f453a-72a8-4bde-b4d3-19e24499720a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1307850418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1307850418
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3787141706
Short name T109
Test name
Test status
Simulation time 336590270000 ps
CPU time 832.56 seconds
Started Jul 14 05:59:59 PM PDT 24
Finished Jul 14 06:34:50 PM PDT 24
Peak memory 160816 kb
Host smart-8e98062e-53d3-4900-a2df-d8bc0f3eb6a0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3787141706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3787141706
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.4137725036
Short name T82
Test name
Test status
Simulation time 337048750000 ps
CPU time 789.99 seconds
Started Jul 14 05:59:59 PM PDT 24
Finished Jul 14 06:31:53 PM PDT 24
Peak memory 160792 kb
Host smart-13d35671-965d-4973-89cd-ecc49a5531f1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4137725036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.4137725036
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1705094559
Short name T18
Test name
Test status
Simulation time 336333850000 ps
CPU time 736.06 seconds
Started Jul 14 05:59:59 PM PDT 24
Finished Jul 14 06:29:47 PM PDT 24
Peak memory 160792 kb
Host smart-e2537fa4-022c-4c03-91de-a6944cdb80bc
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1705094559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1705094559
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.1035055512
Short name T6
Test name
Test status
Simulation time 336771030000 ps
CPU time 888.29 seconds
Started Jul 14 06:00:02 PM PDT 24
Finished Jul 14 06:37:12 PM PDT 24
Peak memory 160796 kb
Host smart-fb220ba4-5b87-4618-8dc3-ddfe6d984938
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1035055512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.1035055512
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.3109040822
Short name T74
Test name
Test status
Simulation time 336615610000 ps
CPU time 775.97 seconds
Started Jul 14 06:00:01 PM PDT 24
Finished Jul 14 06:31:46 PM PDT 24
Peak memory 160792 kb
Host smart-4b205bc8-6753-412a-9e31-e3ad508372aa
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3109040822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.3109040822
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2115684510
Short name T84
Test name
Test status
Simulation time 336377130000 ps
CPU time 780.12 seconds
Started Jul 14 05:59:59 PM PDT 24
Finished Jul 14 06:31:34 PM PDT 24
Peak memory 160720 kb
Host smart-ed9cddc9-51e0-4a6c-a18f-142cb6fd84ee
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2115684510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2115684510
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.728981110
Short name T98
Test name
Test status
Simulation time 336876990000 ps
CPU time 832.16 seconds
Started Jul 14 05:59:58 PM PDT 24
Finished Jul 14 06:34:31 PM PDT 24
Peak memory 160788 kb
Host smart-40f6f0e7-c7d3-4f05-a5c9-c9d9dc897409
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=728981110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.728981110
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.1084703893
Short name T4
Test name
Test status
Simulation time 336672690000 ps
CPU time 836.77 seconds
Started Jul 14 06:00:03 PM PDT 24
Finished Jul 14 06:34:14 PM PDT 24
Peak memory 160832 kb
Host smart-f994528e-2dd6-40e6-ac1c-d3efbc5887a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1084703893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.1084703893
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.3169318290
Short name T93
Test name
Test status
Simulation time 337025770000 ps
CPU time 867.33 seconds
Started Jul 14 06:00:07 PM PDT 24
Finished Jul 14 06:35:20 PM PDT 24
Peak memory 160792 kb
Host smart-fde038d9-291c-43da-a519-bacd85409d6c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3169318290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.3169318290
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2354432345
Short name T96
Test name
Test status
Simulation time 336611850000 ps
CPU time 857.11 seconds
Started Jul 14 06:00:06 PM PDT 24
Finished Jul 14 06:35:13 PM PDT 24
Peak memory 160780 kb
Host smart-a90fad26-4acf-422a-8f56-bf0669f9267b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2354432345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2354432345
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3806729215
Short name T110
Test name
Test status
Simulation time 336689610000 ps
CPU time 730.47 seconds
Started Jul 14 05:59:52 PM PDT 24
Finished Jul 14 06:29:35 PM PDT 24
Peak memory 160724 kb
Host smart-1fcb5863-da85-4639-a6fb-65043fe61a80
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3806729215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3806729215
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3650207917
Short name T73
Test name
Test status
Simulation time 336930790000 ps
CPU time 751.56 seconds
Started Jul 14 06:00:06 PM PDT 24
Finished Jul 14 06:30:36 PM PDT 24
Peak memory 160784 kb
Host smart-9331db3b-81b0-473c-ab8e-773328d33201
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3650207917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3650207917
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1132858326
Short name T78
Test name
Test status
Simulation time 336327050000 ps
CPU time 789.45 seconds
Started Jul 14 06:00:05 PM PDT 24
Finished Jul 14 06:32:03 PM PDT 24
Peak memory 160804 kb
Host smart-cfb4ea16-5e34-4ed2-9d30-07303b27a8a4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1132858326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1132858326
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1834484105
Short name T94
Test name
Test status
Simulation time 337042550000 ps
CPU time 828.02 seconds
Started Jul 14 06:00:04 PM PDT 24
Finished Jul 14 06:33:46 PM PDT 24
Peak memory 160724 kb
Host smart-58ea0804-b5e5-42ad-8da3-33e4feb7a88d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1834484105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1834484105
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4236603075
Short name T77
Test name
Test status
Simulation time 336418470000 ps
CPU time 876.09 seconds
Started Jul 14 06:00:05 PM PDT 24
Finished Jul 14 06:35:27 PM PDT 24
Peak memory 160804 kb
Host smart-9c3fb5bb-eff0-4875-91db-4e7c7ec6b3bd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4236603075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.4236603075
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.503788137
Short name T86
Test name
Test status
Simulation time 336867030000 ps
CPU time 728.42 seconds
Started Jul 14 06:00:03 PM PDT 24
Finished Jul 14 06:29:30 PM PDT 24
Peak memory 160792 kb
Host smart-f64e0119-30da-4899-84e8-43dd94be10dd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=503788137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.503788137
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.2317464358
Short name T5
Test name
Test status
Simulation time 336494050000 ps
CPU time 750.83 seconds
Started Jul 14 06:00:07 PM PDT 24
Finished Jul 14 06:30:44 PM PDT 24
Peak memory 160784 kb
Host smart-87c9fd87-d51c-4170-b60a-e353dc55f378
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2317464358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.2317464358
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.377570855
Short name T102
Test name
Test status
Simulation time 336995510000 ps
CPU time 916.89 seconds
Started Jul 14 06:00:04 PM PDT 24
Finished Jul 14 06:37:09 PM PDT 24
Peak memory 160808 kb
Host smart-72dfea6d-5f4d-4fc5-ae00-62e2892286cb
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=377570855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.377570855
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1932348115
Short name T99
Test name
Test status
Simulation time 336543770000 ps
CPU time 742.4 seconds
Started Jul 14 06:00:04 PM PDT 24
Finished Jul 14 06:30:16 PM PDT 24
Peak memory 160764 kb
Host smart-a713b80d-ecde-4ee2-bd23-ec9748934a27
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1932348115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1932348115
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3926344760
Short name T71
Test name
Test status
Simulation time 336441870000 ps
CPU time 765.98 seconds
Started Jul 14 06:00:05 PM PDT 24
Finished Jul 14 06:31:20 PM PDT 24
Peak memory 160716 kb
Host smart-006c26c0-3021-43dd-9b1b-c736f0c0cc0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3926344760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3926344760
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.257994591
Short name T103
Test name
Test status
Simulation time 336979690000 ps
CPU time 880.28 seconds
Started Jul 14 06:00:04 PM PDT 24
Finished Jul 14 06:36:24 PM PDT 24
Peak memory 160788 kb
Host smart-3222b157-4eed-4d74-87bf-f53007be1950
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=257994591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.257994591
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.2820688557
Short name T19
Test name
Test status
Simulation time 336318730000 ps
CPU time 754.27 seconds
Started Jul 14 05:59:52 PM PDT 24
Finished Jul 14 06:30:35 PM PDT 24
Peak memory 160720 kb
Host smart-cade8db6-0790-40d4-b96c-38838ea1dd6a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2820688557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.2820688557
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.4027281021
Short name T17
Test name
Test status
Simulation time 336942870000 ps
CPU time 785.06 seconds
Started Jul 14 06:00:04 PM PDT 24
Finished Jul 14 06:32:18 PM PDT 24
Peak memory 160796 kb
Host smart-8915d46f-ad28-4c0b-804f-09586ce76120
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4027281021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.4027281021
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.245606287
Short name T104
Test name
Test status
Simulation time 336632810000 ps
CPU time 897.18 seconds
Started Jul 14 06:00:12 PM PDT 24
Finished Jul 14 06:35:58 PM PDT 24
Peak memory 160804 kb
Host smart-9fc73e18-57ed-41f9-95bb-388c6f6554a5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=245606287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.245606287
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.354727000
Short name T92
Test name
Test status
Simulation time 336520970000 ps
CPU time 979.1 seconds
Started Jul 14 06:00:11 PM PDT 24
Finished Jul 14 06:41:15 PM PDT 24
Peak memory 160796 kb
Host smart-c7ffa100-adb0-4fdf-954c-614654f33301
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=354727000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.354727000
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.4179818094
Short name T87
Test name
Test status
Simulation time 336552230000 ps
CPU time 820.6 seconds
Started Jul 14 06:00:11 PM PDT 24
Finished Jul 14 06:34:29 PM PDT 24
Peak memory 160816 kb
Host smart-7e50bad6-16f3-447a-afa5-53d4dcb6d13d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4179818094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.4179818094
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.499463154
Short name T100
Test name
Test status
Simulation time 337034610000 ps
CPU time 876.27 seconds
Started Jul 14 06:00:10 PM PDT 24
Finished Jul 14 06:35:56 PM PDT 24
Peak memory 160816 kb
Host smart-467b89f7-295f-467c-8ff3-cf458b6c10fd
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=499463154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.499463154
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3774163386
Short name T79
Test name
Test status
Simulation time 336933430000 ps
CPU time 781 seconds
Started Jul 14 06:00:11 PM PDT 24
Finished Jul 14 06:32:02 PM PDT 24
Peak memory 160716 kb
Host smart-b086e9d6-2dd5-4c16-a309-c7e9db5f37ce
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3774163386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3774163386
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.3355521915
Short name T105
Test name
Test status
Simulation time 336522650000 ps
CPU time 789.3 seconds
Started Jul 14 06:00:11 PM PDT 24
Finished Jul 14 06:32:12 PM PDT 24
Peak memory 160828 kb
Host smart-5757f605-4eba-4a3b-b67d-2f086d75722b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3355521915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.3355521915
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1044758441
Short name T101
Test name
Test status
Simulation time 336679110000 ps
CPU time 969.15 seconds
Started Jul 14 06:00:14 PM PDT 24
Finished Jul 14 06:40:05 PM PDT 24
Peak memory 160792 kb
Host smart-bf1ef507-32c9-4743-8f49-39ab885a6af7
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1044758441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1044758441
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1475274621
Short name T81
Test name
Test status
Simulation time 336588730000 ps
CPU time 793.69 seconds
Started Jul 14 06:00:11 PM PDT 24
Finished Jul 14 06:32:31 PM PDT 24
Peak memory 160828 kb
Host smart-c038e97c-c508-4d7c-9ec9-c1221b314de8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1475274621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.1475274621
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.4075632432
Short name T97
Test name
Test status
Simulation time 336646190000 ps
CPU time 669.54 seconds
Started Jul 14 06:00:12 PM PDT 24
Finished Jul 14 06:27:48 PM PDT 24
Peak memory 160724 kb
Host smart-f8d8f9a6-19c1-4da0-aabe-f788893c303c
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4075632432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.4075632432
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.376433653
Short name T106
Test name
Test status
Simulation time 336546210000 ps
CPU time 874.43 seconds
Started Jul 14 05:59:55 PM PDT 24
Finished Jul 14 06:36:30 PM PDT 24
Peak memory 160780 kb
Host smart-753daa60-5db4-4170-8cc4-1f98446e2571
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=376433653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.376433653
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3265462803
Short name T76
Test name
Test status
Simulation time 336439170000 ps
CPU time 818.63 seconds
Started Jul 14 05:59:49 PM PDT 24
Finished Jul 14 06:34:11 PM PDT 24
Peak memory 160808 kb
Host smart-9981fb81-0995-416d-ace5-4b3e8613d94d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3265462803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3265462803
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.180944264
Short name T85
Test name
Test status
Simulation time 337071090000 ps
CPU time 874.66 seconds
Started Jul 14 05:59:56 PM PDT 24
Finished Jul 14 06:36:36 PM PDT 24
Peak memory 160780 kb
Host smart-ffedd7b1-9bf7-495b-9996-12347d3ae363
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=180944264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.180944264
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.3695317909
Short name T89
Test name
Test status
Simulation time 337138170000 ps
CPU time 920.12 seconds
Started Jul 14 05:59:51 PM PDT 24
Finished Jul 14 06:37:08 PM PDT 24
Peak memory 160808 kb
Host smart-3c246fc5-d31d-4a77-a8a0-b9672fd8118f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3695317909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.3695317909
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1328866314
Short name T72
Test name
Test status
Simulation time 336853530000 ps
CPU time 857.05 seconds
Started Jul 14 05:59:51 PM PDT 24
Finished Jul 14 06:34:30 PM PDT 24
Peak memory 160776 kb
Host smart-25b08eef-93b5-4b8c-a5ec-6421f9b15588
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1328866314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1328866314
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.3261976361
Short name T179
Test name
Test status
Simulation time 336417890000 ps
CPU time 777.74 seconds
Started Jul 14 06:09:38 PM PDT 24
Finished Jul 14 06:41:15 PM PDT 24
Peak memory 160784 kb
Host smart-a055f991-bf55-4066-b6d6-8a00fdd1ce9a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3261976361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.3261976361
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.3602265349
Short name T184
Test name
Test status
Simulation time 336321850000 ps
CPU time 875.92 seconds
Started Jul 14 06:09:40 PM PDT 24
Finished Jul 14 06:46:22 PM PDT 24
Peak memory 160824 kb
Host smart-ee9f8db8-fe74-42e4-9159-6e4f354efde0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3602265349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.3602265349
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.3650256465
Short name T196
Test name
Test status
Simulation time 337028970000 ps
CPU time 956.1 seconds
Started Jul 14 06:09:38 PM PDT 24
Finished Jul 14 06:49:33 PM PDT 24
Peak memory 160808 kb
Host smart-a07d79fe-5bc7-446b-8bbc-2cfc3b43e5bf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3650256465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.3650256465
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.3176330434
Short name T195
Test name
Test status
Simulation time 336377250000 ps
CPU time 822.25 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:43:07 PM PDT 24
Peak memory 160808 kb
Host smart-81a3427d-4a45-4fde-ad61-6f121176b7f4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3176330434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.3176330434
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3750168115
Short name T175
Test name
Test status
Simulation time 336519950000 ps
CPU time 824.13 seconds
Started Jul 14 06:09:35 PM PDT 24
Finished Jul 14 06:43:15 PM PDT 24
Peak memory 160828 kb
Host smart-e67a2b2d-e20d-406f-bf93-a0c9c9ffab62
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3750168115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3750168115
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1350434354
Short name T165
Test name
Test status
Simulation time 336462370000 ps
CPU time 762.15 seconds
Started Jul 14 06:09:35 PM PDT 24
Finished Jul 14 06:40:37 PM PDT 24
Peak memory 160800 kb
Host smart-247dfa02-0075-47d9-9057-626cc23d3140
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1350434354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1350434354
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3024316796
Short name T166
Test name
Test status
Simulation time 336848810000 ps
CPU time 772.08 seconds
Started Jul 14 06:09:38 PM PDT 24
Finished Jul 14 06:41:22 PM PDT 24
Peak memory 160812 kb
Host smart-36c8a41e-9570-4196-9d94-0f5504f67945
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3024316796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.3024316796
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1810390712
Short name T198
Test name
Test status
Simulation time 336448370000 ps
CPU time 769.81 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:40:46 PM PDT 24
Peak memory 160800 kb
Host smart-6548163b-ea9f-4b6e-a469-d8491916f20e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1810390712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1810390712
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.14051320
Short name T169
Test name
Test status
Simulation time 337069730000 ps
CPU time 720.22 seconds
Started Jul 14 06:09:44 PM PDT 24
Finished Jul 14 06:39:24 PM PDT 24
Peak memory 160796 kb
Host smart-bfee2ac3-85ed-4cc1-8fc4-bed6541dda9e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=14051320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.14051320
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3901458890
Short name T183
Test name
Test status
Simulation time 336622710000 ps
CPU time 908.88 seconds
Started Jul 14 06:09:38 PM PDT 24
Finished Jul 14 06:46:22 PM PDT 24
Peak memory 160780 kb
Host smart-59173d5f-3af1-45b7-9b4b-fe4bd1df6b0a
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3901458890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.3901458890
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1037440767
Short name T172
Test name
Test status
Simulation time 336895650000 ps
CPU time 866.05 seconds
Started Jul 14 06:09:45 PM PDT 24
Finished Jul 14 06:46:10 PM PDT 24
Peak memory 160684 kb
Host smart-0a4fd9af-2b4b-47b2-9ea1-8ff8136790d0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1037440767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1037440767
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1489924340
Short name T173
Test name
Test status
Simulation time 336524650000 ps
CPU time 941.83 seconds
Started Jul 14 06:09:42 PM PDT 24
Finished Jul 14 06:48:30 PM PDT 24
Peak memory 160816 kb
Host smart-53bea2a3-85eb-422d-a676-baf710e186ac
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1489924340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1489924340
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3288937607
Short name T191
Test name
Test status
Simulation time 336836130000 ps
CPU time 593.19 seconds
Started Jul 14 06:09:36 PM PDT 24
Finished Jul 14 06:34:21 PM PDT 24
Peak memory 160736 kb
Host smart-251bfc4d-323b-48fd-89c3-aa9ea2be37f9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3288937607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3288937607
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2208211356
Short name T199
Test name
Test status
Simulation time 336371610000 ps
CPU time 954.31 seconds
Started Jul 14 06:09:39 PM PDT 24
Finished Jul 14 06:49:44 PM PDT 24
Peak memory 160808 kb
Host smart-ce2c274f-dd38-4434-8bd6-00f9b3c5ff4e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2208211356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.2208211356
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.919445857
Short name T161
Test name
Test status
Simulation time 336431070000 ps
CPU time 864.47 seconds
Started Jul 14 06:09:42 PM PDT 24
Finished Jul 14 06:46:06 PM PDT 24
Peak memory 160828 kb
Host smart-c1bc62af-a3dc-4ce0-9634-93f36b38e089
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=919445857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.919445857
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.1291986854
Short name T171
Test name
Test status
Simulation time 336676290000 ps
CPU time 857.78 seconds
Started Jul 14 06:09:42 PM PDT 24
Finished Jul 14 06:44:21 PM PDT 24
Peak memory 160720 kb
Host smart-1e55f23f-9fdb-442c-ad3c-aeee485a7071
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1291986854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.1291986854
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.3315374052
Short name T192
Test name
Test status
Simulation time 336898790000 ps
CPU time 842.19 seconds
Started Jul 14 06:09:40 PM PDT 24
Finished Jul 14 06:44:18 PM PDT 24
Peak memory 160792 kb
Host smart-ed3321bb-5882-4921-800f-633453927c7b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3315374052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.3315374052
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1087855806
Short name T25
Test name
Test status
Simulation time 336580510000 ps
CPU time 743.94 seconds
Started Jul 14 06:09:41 PM PDT 24
Finished Jul 14 06:39:56 PM PDT 24
Peak memory 160724 kb
Host smart-b6b7fb0d-2527-4fbc-9ae3-a433a191c87e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1087855806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1087855806
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.576010787
Short name T164
Test name
Test status
Simulation time 336641830000 ps
CPU time 806.15 seconds
Started Jul 14 06:09:41 PM PDT 24
Finished Jul 14 06:42:26 PM PDT 24
Peak memory 160716 kb
Host smart-5b31e79f-47b0-4c1c-bd00-2cc490288302
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=576010787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.576010787
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2983527039
Short name T170
Test name
Test status
Simulation time 336351910000 ps
CPU time 791.64 seconds
Started Jul 14 06:09:43 PM PDT 24
Finished Jul 14 06:42:07 PM PDT 24
Peak memory 160768 kb
Host smart-3407f415-a70b-4c3e-8691-3da53d9e5dee
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2983527039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2983527039
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.1966065689
Short name T22
Test name
Test status
Simulation time 336330810000 ps
CPU time 718.61 seconds
Started Jul 14 06:09:44 PM PDT 24
Finished Jul 14 06:39:10 PM PDT 24
Peak memory 160796 kb
Host smart-5fae3688-f2fe-43a1-89db-2eb1fb4f1b62
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1966065689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.1966065689
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2781919321
Short name T162
Test name
Test status
Simulation time 336363130000 ps
CPU time 705.18 seconds
Started Jul 14 06:09:42 PM PDT 24
Finished Jul 14 06:38:55 PM PDT 24
Peak memory 160720 kb
Host smart-8551a7ab-be84-4956-8af3-44b86efc1128
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2781919321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2781919321
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.804583287
Short name T187
Test name
Test status
Simulation time 336391630000 ps
CPU time 753.1 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:40:33 PM PDT 24
Peak memory 160796 kb
Host smart-4cc1ef4d-1b39-48a4-85c8-e64441ed0d0c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=804583287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.804583287
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1053160514
Short name T193
Test name
Test status
Simulation time 337148410000 ps
CPU time 680.37 seconds
Started Jul 14 06:09:39 PM PDT 24
Finished Jul 14 06:37:22 PM PDT 24
Peak memory 160740 kb
Host smart-9e8f9647-c1ab-4c2e-80fb-285162c4ce4f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1053160514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1053160514
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.3880412037
Short name T186
Test name
Test status
Simulation time 336827610000 ps
CPU time 947.63 seconds
Started Jul 14 06:09:42 PM PDT 24
Finished Jul 14 06:48:28 PM PDT 24
Peak memory 160816 kb
Host smart-67835ff1-d7ab-4b3a-8746-da2134e73199
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3880412037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.3880412037
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.279012612
Short name T168
Test name
Test status
Simulation time 336967850000 ps
CPU time 808.72 seconds
Started Jul 14 06:09:41 PM PDT 24
Finished Jul 14 06:43:24 PM PDT 24
Peak memory 160704 kb
Host smart-567a5856-c050-4f86-8266-b14becc94f4b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=279012612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.279012612
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2912457472
Short name T197
Test name
Test status
Simulation time 336383750000 ps
CPU time 845.24 seconds
Started Jul 14 06:09:47 PM PDT 24
Finished Jul 14 06:45:26 PM PDT 24
Peak memory 160684 kb
Host smart-b43706e2-bd21-4404-8cc3-42b39bb78700
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2912457472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2912457472
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1148309196
Short name T200
Test name
Test status
Simulation time 336368770000 ps
CPU time 950.02 seconds
Started Jul 14 06:09:44 PM PDT 24
Finished Jul 14 06:48:48 PM PDT 24
Peak memory 160796 kb
Host smart-f9ed768d-c8b9-46dd-a8d1-a0e59a1eff77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1148309196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1148309196
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1341093963
Short name T181
Test name
Test status
Simulation time 337029750000 ps
CPU time 803.68 seconds
Started Jul 14 06:09:46 PM PDT 24
Finished Jul 14 06:42:46 PM PDT 24
Peak memory 160788 kb
Host smart-c93101a6-00d1-4055-9b74-3094c4738b72
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1341093963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1341093963
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1765360697
Short name T167
Test name
Test status
Simulation time 337104870000 ps
CPU time 721.96 seconds
Started Jul 14 06:09:41 PM PDT 24
Finished Jul 14 06:39:25 PM PDT 24
Peak memory 160740 kb
Host smart-a3108df9-4751-4dda-9c5d-2fd561ada1fe
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1765360697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1765360697
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.2836583747
Short name T177
Test name
Test status
Simulation time 336824470000 ps
CPU time 776.74 seconds
Started Jul 14 06:09:43 PM PDT 24
Finished Jul 14 06:41:34 PM PDT 24
Peak memory 160796 kb
Host smart-01aee385-e4f4-4944-a405-ed11fdcda97e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2836583747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.2836583747
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.870483160
Short name T23
Test name
Test status
Simulation time 336803850000 ps
CPU time 788.13 seconds
Started Jul 14 06:09:42 PM PDT 24
Finished Jul 14 06:41:50 PM PDT 24
Peak memory 160760 kb
Host smart-4724914e-17b5-42f3-8e27-2b1423178d5c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=870483160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.870483160
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4243597179
Short name T182
Test name
Test status
Simulation time 336588650000 ps
CPU time 708.52 seconds
Started Jul 14 06:09:43 PM PDT 24
Finished Jul 14 06:38:41 PM PDT 24
Peak memory 160792 kb
Host smart-383a8896-48ca-4988-aa82-c113abd97633
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4243597179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.4243597179
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.731933501
Short name T29
Test name
Test status
Simulation time 336613950000 ps
CPU time 776.49 seconds
Started Jul 14 06:09:36 PM PDT 24
Finished Jul 14 06:41:24 PM PDT 24
Peak memory 160804 kb
Host smart-0d21a2bb-b412-41d2-846e-f35edc6079fd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=731933501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.731933501
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2420565670
Short name T178
Test name
Test status
Simulation time 336967490000 ps
CPU time 807.16 seconds
Started Jul 14 06:09:41 PM PDT 24
Finished Jul 14 06:42:31 PM PDT 24
Peak memory 160716 kb
Host smart-a29a7324-07bc-4b13-b731-f0d8261b7edb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2420565670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.2420565670
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.620030550
Short name T26
Test name
Test status
Simulation time 336673430000 ps
CPU time 823.4 seconds
Started Jul 14 06:09:49 PM PDT 24
Finished Jul 14 06:43:31 PM PDT 24
Peak memory 160812 kb
Host smart-cca825ae-d706-43bf-a870-d76c86657179
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=620030550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.620030550
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3747739430
Short name T174
Test name
Test status
Simulation time 336663210000 ps
CPU time 772.46 seconds
Started Jul 14 06:09:43 PM PDT 24
Finished Jul 14 06:41:24 PM PDT 24
Peak memory 160796 kb
Host smart-a1908561-4100-44ff-ada9-d9c59892b2a5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3747739430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3747739430
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3065190181
Short name T163
Test name
Test status
Simulation time 336556810000 ps
CPU time 862.57 seconds
Started Jul 14 06:09:46 PM PDT 24
Finished Jul 14 06:46:05 PM PDT 24
Peak memory 160684 kb
Host smart-485a29f4-64f1-4e5d-812d-c87c37108dcf
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3065190181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3065190181
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3295323187
Short name T180
Test name
Test status
Simulation time 336911850000 ps
CPU time 866.26 seconds
Started Jul 14 06:09:42 PM PDT 24
Finished Jul 14 06:45:47 PM PDT 24
Peak memory 160840 kb
Host smart-e3e232cb-e19c-4621-a1d1-6e6696761853
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3295323187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3295323187
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1923620379
Short name T30
Test name
Test status
Simulation time 336951570000 ps
CPU time 853.55 seconds
Started Jul 14 06:09:45 PM PDT 24
Finished Jul 14 06:45:42 PM PDT 24
Peak memory 160684 kb
Host smart-01238a4d-0856-4918-b725-710b39eaac1f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1923620379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1923620379
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.4189723194
Short name T190
Test name
Test status
Simulation time 336608990000 ps
CPU time 805.4 seconds
Started Jul 14 06:09:39 PM PDT 24
Finished Jul 14 06:41:53 PM PDT 24
Peak memory 160792 kb
Host smart-01779d8e-9eca-4f53-906d-8d0e05017aa2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4189723194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.4189723194
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1719680364
Short name T189
Test name
Test status
Simulation time 336429730000 ps
CPU time 820.63 seconds
Started Jul 14 06:09:49 PM PDT 24
Finished Jul 14 06:43:31 PM PDT 24
Peak memory 160820 kb
Host smart-1c9a0bc1-b83e-4f88-96c5-56cc0c8ec79e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1719680364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1719680364
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.2186953039
Short name T21
Test name
Test status
Simulation time 336556710000 ps
CPU time 798.47 seconds
Started Jul 14 06:09:46 PM PDT 24
Finished Jul 14 06:42:40 PM PDT 24
Peak memory 160812 kb
Host smart-694081cb-0c2b-4ee2-879f-d5e051dc8c56
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2186953039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.2186953039
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3938411372
Short name T185
Test name
Test status
Simulation time 336543850000 ps
CPU time 810.31 seconds
Started Jul 14 06:09:47 PM PDT 24
Finished Jul 14 06:42:12 PM PDT 24
Peak memory 160776 kb
Host smart-4ddb7d56-0a8a-4027-905e-1ff8abc9ad7e
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3938411372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.3938411372
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.1817720692
Short name T28
Test name
Test status
Simulation time 336871130000 ps
CPU time 871.3 seconds
Started Jul 14 06:09:42 PM PDT 24
Finished Jul 14 06:46:26 PM PDT 24
Peak memory 160824 kb
Host smart-3aaf4783-5c18-44fc-b0dc-4cad2c87eaf4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1817720692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.1817720692
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1133316822
Short name T194
Test name
Test status
Simulation time 336953550000 ps
CPU time 951.86 seconds
Started Jul 14 06:09:40 PM PDT 24
Finished Jul 14 06:48:43 PM PDT 24
Peak memory 160808 kb
Host smart-7fcd08a4-e2e2-449f-ab4b-11a6fa88f305
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1133316822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1133316822
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.753326426
Short name T188
Test name
Test status
Simulation time 336986670000 ps
CPU time 803.43 seconds
Started Jul 14 06:09:36 PM PDT 24
Finished Jul 14 06:42:16 PM PDT 24
Peak memory 160820 kb
Host smart-481e13a1-9594-4822-9a7f-d89b53a7da0d
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=753326426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.753326426
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3580283960
Short name T176
Test name
Test status
Simulation time 336601050000 ps
CPU time 956.83 seconds
Started Jul 14 06:09:37 PM PDT 24
Finished Jul 14 06:49:31 PM PDT 24
Peak memory 160800 kb
Host smart-2cfcf82a-66d3-4440-a024-179543eb47b0
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3580283960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3580283960
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1343442863
Short name T24
Test name
Test status
Simulation time 336513710000 ps
CPU time 953.34 seconds
Started Jul 14 06:09:44 PM PDT 24
Finished Jul 14 06:48:49 PM PDT 24
Peak memory 160788 kb
Host smart-b92819a1-11c5-4a53-a074-b92b4ab57f86
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1343442863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1343442863
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4285080345
Short name T138
Test name
Test status
Simulation time 1540170000 ps
CPU time 3.49 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:22:09 PM PDT 24
Peak memory 164796 kb
Host smart-9252a141-c53a-4a69-a431-3e3a94644266
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4285080345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.4285080345
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.4036155206
Short name T158
Test name
Test status
Simulation time 1598710000 ps
CPU time 3.63 seconds
Started Jul 14 04:21:04 PM PDT 24
Finished Jul 14 04:21:12 PM PDT 24
Peak memory 164800 kb
Host smart-02f7197a-aa56-447a-b7f6-841dc3913927
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4036155206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.4036155206
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.1684793505
Short name T152
Test name
Test status
Simulation time 1326170000 ps
CPU time 2.99 seconds
Started Jul 14 04:22:32 PM PDT 24
Finished Jul 14 04:22:41 PM PDT 24
Peak memory 164808 kb
Host smart-7abc7661-d23f-4fd3-9208-d4b3d33d9b14
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1684793505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.1684793505
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1907247594
Short name T126
Test name
Test status
Simulation time 1606610000 ps
CPU time 3.85 seconds
Started Jul 14 04:22:17 PM PDT 24
Finished Jul 14 04:22:27 PM PDT 24
Peak memory 163504 kb
Host smart-0144f918-2a80-43e9-90c2-d008127a2eec
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1907247594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1907247594
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3659813617
Short name T125
Test name
Test status
Simulation time 1282930000 ps
CPU time 4.12 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:22:52 PM PDT 24
Peak memory 164808 kb
Host smart-ad5f8e9b-36c5-4ad8-a102-e27179f7de21
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3659813617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3659813617
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.1191876470
Short name T121
Test name
Test status
Simulation time 1085170000 ps
CPU time 3.02 seconds
Started Jul 14 04:20:42 PM PDT 24
Finished Jul 14 04:20:49 PM PDT 24
Peak memory 164792 kb
Host smart-ada8c018-a884-4a39-a85b-1b868680f088
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1191876470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.1191876470
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3118126908
Short name T159
Test name
Test status
Simulation time 1569590000 ps
CPU time 4.23 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:54 PM PDT 24
Peak memory 164760 kb
Host smart-a23ff1ef-7bab-4771-9f49-18147c2a68a6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3118126908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3118126908
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.113153753
Short name T134
Test name
Test status
Simulation time 1163930000 ps
CPU time 3.38 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:52 PM PDT 24
Peak memory 164796 kb
Host smart-34d96da0-61d2-4acb-a739-c05f148f10d0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=113153753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.113153753
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.3916342176
Short name T137
Test name
Test status
Simulation time 1637650000 ps
CPU time 3.76 seconds
Started Jul 14 04:22:19 PM PDT 24
Finished Jul 14 04:22:28 PM PDT 24
Peak memory 164644 kb
Host smart-b37a4ca3-f466-4b23-85ec-7e561510876e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3916342176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.3916342176
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.4044004668
Short name T115
Test name
Test status
Simulation time 1341270000 ps
CPU time 3.13 seconds
Started Jul 14 04:17:55 PM PDT 24
Finished Jul 14 04:18:02 PM PDT 24
Peak memory 164824 kb
Host smart-9f3d6c0f-7bc0-4315-95d4-035ec96e9f2c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044004668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.4044004668
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.3573501475
Short name T148
Test name
Test status
Simulation time 1551650000 ps
CPU time 3.28 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:22:06 PM PDT 24
Peak memory 164352 kb
Host smart-ce9bcf2c-cfee-4272-8bcb-d300f3a000de
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3573501475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.3573501475
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.3455511536
Short name T122
Test name
Test status
Simulation time 1509790000 ps
CPU time 3.24 seconds
Started Jul 14 04:18:53 PM PDT 24
Finished Jul 14 04:19:01 PM PDT 24
Peak memory 164752 kb
Host smart-62609097-78ea-4c6a-a8ba-94e65545b641
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3455511536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.3455511536
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1082025419
Short name T146
Test name
Test status
Simulation time 1280130000 ps
CPU time 3.18 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:22:38 PM PDT 24
Peak memory 163792 kb
Host smart-54ecc6ad-e8a1-44f5-a7f1-2997b5fbae0e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1082025419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1082025419
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.557265889
Short name T144
Test name
Test status
Simulation time 1497350000 ps
CPU time 3.24 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:43 PM PDT 24
Peak memory 164732 kb
Host smart-56ee13ba-a4e6-4088-8f9c-e4231f16aad8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=557265889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.557265889
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1739978219
Short name T128
Test name
Test status
Simulation time 1556250000 ps
CPU time 3.37 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:45 PM PDT 24
Peak memory 164808 kb
Host smart-82e32cc4-761f-4286-9ae9-dd891eac6490
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1739978219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1739978219
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.3805156084
Short name T156
Test name
Test status
Simulation time 1592130000 ps
CPU time 5.77 seconds
Started Jul 14 04:27:37 PM PDT 24
Finished Jul 14 04:27:51 PM PDT 24
Peak memory 164740 kb
Host smart-077527c9-3345-4f84-a9e0-da43a48cbc31
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3805156084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.3805156084
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.3368122062
Short name T120
Test name
Test status
Simulation time 1534510000 ps
CPU time 4.28 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:45 PM PDT 24
Peak memory 164768 kb
Host smart-f09d3ac5-22b6-4d18-9d6a-8f29d72edbcf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3368122062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.3368122062
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1421799666
Short name T139
Test name
Test status
Simulation time 1647870000 ps
CPU time 3.87 seconds
Started Jul 14 04:27:37 PM PDT 24
Finished Jul 14 04:27:47 PM PDT 24
Peak memory 164852 kb
Host smart-e7073cc2-c766-47d1-9d3f-21b9036770c7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1421799666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1421799666
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.1708588534
Short name T111
Test name
Test status
Simulation time 1509850000 ps
CPU time 4.84 seconds
Started Jul 14 04:27:33 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164788 kb
Host smart-b1cb21a8-f1a6-4fb3-891a-a84d4e2e6d7e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1708588534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.1708588534
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.517201350
Short name T153
Test name
Test status
Simulation time 1536790000 ps
CPU time 3.63 seconds
Started Jul 14 04:27:39 PM PDT 24
Finished Jul 14 04:27:48 PM PDT 24
Peak memory 164720 kb
Host smart-6c43071d-8120-4b33-aa31-b551b3e8042d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=517201350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.517201350
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.813689787
Short name T132
Test name
Test status
Simulation time 1420170000 ps
CPU time 5.15 seconds
Started Jul 14 04:27:34 PM PDT 24
Finished Jul 14 04:27:46 PM PDT 24
Peak memory 164816 kb
Host smart-95d92712-8aab-4052-8f01-f3d442554d1e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=813689787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.813689787
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3688328277
Short name T127
Test name
Test status
Simulation time 1373710000 ps
CPU time 3.02 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:45 PM PDT 24
Peak memory 164748 kb
Host smart-731bcbbb-3c2a-4198-bbc5-b328e31f7bba
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3688328277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3688328277
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.638482118
Short name T113
Test name
Test status
Simulation time 1535190000 ps
CPU time 3.59 seconds
Started Jul 14 04:27:37 PM PDT 24
Finished Jul 14 04:27:46 PM PDT 24
Peak memory 164716 kb
Host smart-8c130a05-e6a0-493b-a974-2f4d97a5b889
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=638482118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.638482118
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.2432256919
Short name T123
Test name
Test status
Simulation time 1517510000 ps
CPU time 3.51 seconds
Started Jul 14 04:18:10 PM PDT 24
Finished Jul 14 04:18:18 PM PDT 24
Peak memory 164760 kb
Host smart-3dab0ebc-d4a7-44b2-876c-001004c92fed
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2432256919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.2432256919
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.345377484
Short name T131
Test name
Test status
Simulation time 1495670000 ps
CPU time 3.85 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:45 PM PDT 24
Peak memory 164768 kb
Host smart-e938f1a0-80ef-4de4-9fe8-6a5d35f1bbf4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=345377484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.345377484
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.2083338488
Short name T129
Test name
Test status
Simulation time 1585470000 ps
CPU time 4.05 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:47 PM PDT 24
Peak memory 164776 kb
Host smart-ca6c4d80-9f64-40c6-a8f2-8d6f26e77795
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2083338488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.2083338488
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.4233345658
Short name T141
Test name
Test status
Simulation time 1488570000 ps
CPU time 3.64 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164648 kb
Host smart-fcc5e8ec-b228-44b8-b2af-97b5bb86e778
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4233345658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.4233345658
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.435184337
Short name T154
Test name
Test status
Simulation time 1482850000 ps
CPU time 5.54 seconds
Started Jul 14 04:27:34 PM PDT 24
Finished Jul 14 04:27:46 PM PDT 24
Peak memory 164784 kb
Host smart-571a52fd-029e-416f-a019-73669988bd0f
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=435184337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.435184337
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.1580819516
Short name T118
Test name
Test status
Simulation time 1341570000 ps
CPU time 3.27 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164880 kb
Host smart-15ee8b22-2d30-4409-8dcf-73a4fda6c2dd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1580819516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.1580819516
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.974405461
Short name T150
Test name
Test status
Simulation time 1527470000 ps
CPU time 3.36 seconds
Started Jul 14 04:27:34 PM PDT 24
Finished Jul 14 04:27:42 PM PDT 24
Peak memory 164832 kb
Host smart-3cd27775-7f84-47dc-b905-29680dbefa85
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974405461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.974405461
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.674258598
Short name T117
Test name
Test status
Simulation time 1463530000 ps
CPU time 3.24 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164804 kb
Host smart-f7462d08-d9b7-4458-b686-a52ec3fb13e9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=674258598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.674258598
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1620436186
Short name T112
Test name
Test status
Simulation time 1388510000 ps
CPU time 3.28 seconds
Started Jul 14 04:27:37 PM PDT 24
Finished Jul 14 04:27:45 PM PDT 24
Peak memory 164772 kb
Host smart-2f700d37-62f7-455b-beba-ef6c705032bf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1620436186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1620436186
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.243179744
Short name T149
Test name
Test status
Simulation time 1472850000 ps
CPU time 2.88 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164832 kb
Host smart-dbde65c5-c3f6-4b95-a474-166e59023bd8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=243179744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.243179744
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3394028445
Short name T145
Test name
Test status
Simulation time 1134470000 ps
CPU time 3.05 seconds
Started Jul 14 04:27:39 PM PDT 24
Finished Jul 14 04:27:46 PM PDT 24
Peak memory 164776 kb
Host smart-fc89b2a5-2d31-4cbd-9c5b-ded38b7bad01
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394028445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3394028445
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.80518325
Short name T119
Test name
Test status
Simulation time 1489150000 ps
CPU time 3.12 seconds
Started Jul 14 04:21:45 PM PDT 24
Finished Jul 14 04:21:53 PM PDT 24
Peak memory 164300 kb
Host smart-9d64ff00-89dc-40df-98cb-b92cd235a9ef
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=80518325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.80518325
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1289216823
Short name T124
Test name
Test status
Simulation time 1492310000 ps
CPU time 4.14 seconds
Started Jul 14 04:27:37 PM PDT 24
Finished Jul 14 04:27:47 PM PDT 24
Peak memory 164800 kb
Host smart-8d7c73a4-aa16-4003-a614-e4347da6a839
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1289216823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1289216823
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.3253798244
Short name T147
Test name
Test status
Simulation time 1499790000 ps
CPU time 6.01 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:48 PM PDT 24
Peak memory 164776 kb
Host smart-6be504d6-111e-4540-8d2c-14023ee4100b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3253798244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.3253798244
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.934168954
Short name T155
Test name
Test status
Simulation time 1445470000 ps
CPU time 3.18 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164804 kb
Host smart-a596f1b8-abc0-46fd-ac41-fd48aabe5179
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=934168954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.934168954
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.2519609330
Short name T142
Test name
Test status
Simulation time 1535330000 ps
CPU time 6.6 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:51 PM PDT 24
Peak memory 164692 kb
Host smart-3e1bc5d3-bb96-4539-beab-21cab9ef7c05
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2519609330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.2519609330
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.1406057529
Short name T140
Test name
Test status
Simulation time 1462130000 ps
CPU time 3.21 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164768 kb
Host smart-6744958a-6f63-439f-8007-750ef28959fc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1406057529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.1406057529
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3583922255
Short name T143
Test name
Test status
Simulation time 1373090000 ps
CPU time 2.83 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164740 kb
Host smart-0262b031-e28b-445c-ac41-7037c2ce9474
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3583922255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3583922255
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1171343853
Short name T136
Test name
Test status
Simulation time 1536030000 ps
CPU time 6.82 seconds
Started Jul 14 04:27:33 PM PDT 24
Finished Jul 14 04:27:48 PM PDT 24
Peak memory 164768 kb
Host smart-bafb1b33-d236-4818-8583-a4bd64abe7a7
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1171343853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1171343853
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3732637978
Short name T130
Test name
Test status
Simulation time 1382870000 ps
CPU time 3.28 seconds
Started Jul 14 04:27:35 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164772 kb
Host smart-5cc2786f-e86d-492b-b5e8-1a7e54e6c576
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3732637978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3732637978
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.2372889984
Short name T135
Test name
Test status
Simulation time 1398210000 ps
CPU time 2.73 seconds
Started Jul 14 04:27:36 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 164836 kb
Host smart-0162d45f-78cf-4727-9de6-bb60079c6920
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372889984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.2372889984
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.2797034586
Short name T151
Test name
Test status
Simulation time 1378470000 ps
CPU time 3.43 seconds
Started Jul 14 04:27:44 PM PDT 24
Finished Jul 14 04:27:52 PM PDT 24
Peak memory 164800 kb
Host smart-77486001-5ee4-4d23-995f-240a1250f95c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2797034586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.2797034586
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.769159775
Short name T160
Test name
Test status
Simulation time 1443650000 ps
CPU time 5.61 seconds
Started Jul 14 04:18:44 PM PDT 24
Finished Jul 14 04:18:56 PM PDT 24
Peak memory 164688 kb
Host smart-e41c6609-0698-4098-8b79-2ee2d92cc94c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=769159775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.769159775
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3728422137
Short name T114
Test name
Test status
Simulation time 1136370000 ps
CPU time 2.55 seconds
Started Jul 14 04:21:45 PM PDT 24
Finished Jul 14 04:21:52 PM PDT 24
Peak memory 164460 kb
Host smart-205a6df9-4486-44ee-96d4-7fe1daf88573
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3728422137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3728422137
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3363059139
Short name T116
Test name
Test status
Simulation time 1263750000 ps
CPU time 3.09 seconds
Started Jul 14 04:17:52 PM PDT 24
Finished Jul 14 04:17:59 PM PDT 24
Peak memory 164840 kb
Host smart-3c72af7d-c69c-40a6-b85b-c1bf99e80bc5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3363059139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.3363059139
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1955153017
Short name T157
Test name
Test status
Simulation time 1447190000 ps
CPU time 3.35 seconds
Started Jul 14 04:21:44 PM PDT 24
Finished Jul 14 04:21:52 PM PDT 24
Peak memory 163264 kb
Host smart-d17382b0-b071-4117-834f-ea558220c5a6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1955153017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1955153017
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2044979965
Short name T133
Test name
Test status
Simulation time 1543430000 ps
CPU time 4.92 seconds
Started Jul 14 04:18:54 PM PDT 24
Finished Jul 14 04:19:05 PM PDT 24
Peak memory 164764 kb
Host smart-d9147e79-77e8-4850-b957-97fbd62166b4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2044979965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2044979965
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.2368304433
Short name T61
Test name
Test status
Simulation time 1328290000 ps
CPU time 5.12 seconds
Started Jul 14 06:00:14 PM PDT 24
Finished Jul 14 06:00:25 PM PDT 24
Peak memory 164916 kb
Host smart-a89d7621-4fbb-4589-89cf-1ff1f4f248d9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2368304433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.2368304433
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1542924883
Short name T68
Test name
Test status
Simulation time 1557450000 ps
CPU time 4.63 seconds
Started Jul 14 06:00:12 PM PDT 24
Finished Jul 14 06:00:23 PM PDT 24
Peak memory 164940 kb
Host smart-8e633c51-013e-4386-9737-950d09549a17
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1542924883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1542924883
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.409634465
Short name T60
Test name
Test status
Simulation time 1416170000 ps
CPU time 3.79 seconds
Started Jul 14 06:00:12 PM PDT 24
Finished Jul 14 06:00:21 PM PDT 24
Peak memory 164856 kb
Host smart-155b40bb-485a-41b0-9d84-4c805a255251
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409634465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.409634465
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.3333803368
Short name T39
Test name
Test status
Simulation time 1208310000 ps
CPU time 4.39 seconds
Started Jul 14 06:00:14 PM PDT 24
Finished Jul 14 06:00:25 PM PDT 24
Peak memory 164788 kb
Host smart-b4b89b17-6012-474b-a670-721629dd52a6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3333803368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.3333803368
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1750377523
Short name T31
Test name
Test status
Simulation time 1536710000 ps
CPU time 5.34 seconds
Started Jul 14 06:00:09 PM PDT 24
Finished Jul 14 06:00:21 PM PDT 24
Peak memory 164848 kb
Host smart-69251169-e5f7-4bb2-82a9-64a86ceea0df
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1750377523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1750377523
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1722355378
Short name T10
Test name
Test status
Simulation time 1359430000 ps
CPU time 4.6 seconds
Started Jul 14 06:00:21 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 164908 kb
Host smart-916ad9d8-bf23-4b61-9856-1ab766f437fc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1722355378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1722355378
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2546692658
Short name T35
Test name
Test status
Simulation time 1528970000 ps
CPU time 6.65 seconds
Started Jul 14 06:00:18 PM PDT 24
Finished Jul 14 06:00:33 PM PDT 24
Peak memory 164812 kb
Host smart-30f87601-c0fc-4ee8-8bb3-d4bc91617e8a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2546692658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2546692658
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1893654112
Short name T48
Test name
Test status
Simulation time 1320270000 ps
CPU time 4.47 seconds
Started Jul 14 06:00:20 PM PDT 24
Finished Jul 14 06:00:30 PM PDT 24
Peak memory 164924 kb
Host smart-b0ebd8dc-17c7-431d-bbfb-cc3da28e1fca
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1893654112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1893654112
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.31620088
Short name T64
Test name
Test status
Simulation time 1464370000 ps
CPU time 4.09 seconds
Started Jul 14 06:00:18 PM PDT 24
Finished Jul 14 06:00:28 PM PDT 24
Peak memory 164964 kb
Host smart-46c8d80b-80c1-4c98-bc4e-019707323481
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=31620088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.31620088
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.2388595130
Short name T32
Test name
Test status
Simulation time 1313470000 ps
CPU time 4.49 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:29 PM PDT 24
Peak memory 164880 kb
Host smart-9eaa79c4-3bb8-47a7-90a6-501c3f9109c5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2388595130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.2388595130
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.452678317
Short name T40
Test name
Test status
Simulation time 1457330000 ps
CPU time 5.4 seconds
Started Jul 14 06:00:20 PM PDT 24
Finished Jul 14 06:00:33 PM PDT 24
Peak memory 164820 kb
Host smart-6748f6b8-21cb-4ab1-990f-102f22619213
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=452678317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.452678317
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.3391943865
Short name T65
Test name
Test status
Simulation time 1402310000 ps
CPU time 4.84 seconds
Started Jul 14 06:00:14 PM PDT 24
Finished Jul 14 06:00:26 PM PDT 24
Peak memory 164788 kb
Host smart-32adef8f-cb82-4c46-9b53-fd462e7d3484
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3391943865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.3391943865
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1978425804
Short name T45
Test name
Test status
Simulation time 1496750000 ps
CPU time 6.19 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:33 PM PDT 24
Peak memory 164920 kb
Host smart-51cea401-248a-499a-b7a0-736e1c7f72f9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1978425804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.1978425804
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.1995174325
Short name T7
Test name
Test status
Simulation time 1521130000 ps
CPU time 5.51 seconds
Started Jul 14 06:00:17 PM PDT 24
Finished Jul 14 06:00:30 PM PDT 24
Peak memory 164908 kb
Host smart-dde52b60-6c55-4ec9-ac63-eefa631e2dad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1995174325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.1995174325
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.962671321
Short name T8
Test name
Test status
Simulation time 1461210000 ps
CPU time 4.35 seconds
Started Jul 14 06:00:17 PM PDT 24
Finished Jul 14 06:00:27 PM PDT 24
Peak memory 164904 kb
Host smart-13254a8f-1268-429f-92f2-dd5e8ef75c11
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=962671321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.962671321
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1617881406
Short name T54
Test name
Test status
Simulation time 1512690000 ps
CPU time 4.86 seconds
Started Jul 14 06:00:18 PM PDT 24
Finished Jul 14 06:00:30 PM PDT 24
Peak memory 164904 kb
Host smart-57675d30-09c8-49b1-951f-da0ba707841f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1617881406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.1617881406
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2721457528
Short name T59
Test name
Test status
Simulation time 1420970000 ps
CPU time 4.6 seconds
Started Jul 14 06:00:17 PM PDT 24
Finished Jul 14 06:00:28 PM PDT 24
Peak memory 164824 kb
Host smart-c437fb7d-0128-4e05-a802-ec592145738a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2721457528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2721457528
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.827407704
Short name T2
Test name
Test status
Simulation time 1585630000 ps
CPU time 4.28 seconds
Started Jul 14 06:00:21 PM PDT 24
Finished Jul 14 06:00:31 PM PDT 24
Peak memory 164812 kb
Host smart-c502b9cd-ebbc-463d-b1f2-bfe470ffcf65
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=827407704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.827407704
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2074482034
Short name T33
Test name
Test status
Simulation time 1460630000 ps
CPU time 5.85 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 164864 kb
Host smart-52450ce3-7a75-4fbf-be08-d25307682a26
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2074482034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2074482034
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.327763658
Short name T46
Test name
Test status
Simulation time 1268450000 ps
CPU time 4.55 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:30 PM PDT 24
Peak memory 164916 kb
Host smart-050c44fa-9f1f-443f-a98b-958a97b0c3cc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=327763658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.327763658
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3788970076
Short name T11
Test name
Test status
Simulation time 1519090000 ps
CPU time 5.47 seconds
Started Jul 14 06:00:21 PM PDT 24
Finished Jul 14 06:00:33 PM PDT 24
Peak memory 164916 kb
Host smart-96558eb8-6689-4b2c-98d0-e996f22bd95e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3788970076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3788970076
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2774296059
Short name T49
Test name
Test status
Simulation time 1442050000 ps
CPU time 5.89 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:33 PM PDT 24
Peak memory 164900 kb
Host smart-4dc0a22c-4940-4bf6-b146-cfca73d20aa9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774296059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2774296059
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2814137876
Short name T69
Test name
Test status
Simulation time 1550450000 ps
CPU time 4.71 seconds
Started Jul 14 06:00:12 PM PDT 24
Finished Jul 14 06:00:23 PM PDT 24
Peak memory 164916 kb
Host smart-71587891-ae75-4cd0-b9a1-49fef5bb152d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2814137876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2814137876
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1565876430
Short name T52
Test name
Test status
Simulation time 1497170000 ps
CPU time 5.8 seconds
Started Jul 14 06:00:18 PM PDT 24
Finished Jul 14 06:00:31 PM PDT 24
Peak memory 164916 kb
Host smart-401dc5fb-f68d-4fd1-87a5-b128af92346f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1565876430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1565876430
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.1456747763
Short name T37
Test name
Test status
Simulation time 1238310000 ps
CPU time 4.22 seconds
Started Jul 14 06:00:20 PM PDT 24
Finished Jul 14 06:00:30 PM PDT 24
Peak memory 164908 kb
Host smart-8531fc41-2322-445e-8b93-bf9c2ecf3ce9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1456747763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.1456747763
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.4207786483
Short name T43
Test name
Test status
Simulation time 1503110000 ps
CPU time 4.89 seconds
Started Jul 14 06:00:20 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 164888 kb
Host smart-5e1e9a26-8cda-4798-86bf-82f43e273b8a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4207786483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.4207786483
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3492891240
Short name T51
Test name
Test status
Simulation time 1487690000 ps
CPU time 5.79 seconds
Started Jul 14 06:00:20 PM PDT 24
Finished Jul 14 06:00:33 PM PDT 24
Peak memory 164776 kb
Host smart-7cbfda1c-43fd-4101-8e41-73f3220aebc5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3492891240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3492891240
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1900938752
Short name T56
Test name
Test status
Simulation time 1569570000 ps
CPU time 4.86 seconds
Started Jul 14 06:00:20 PM PDT 24
Finished Jul 14 06:00:31 PM PDT 24
Peak memory 164864 kb
Host smart-493860e0-2974-4303-a601-01df518b67f2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1900938752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1900938752
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1756151450
Short name T36
Test name
Test status
Simulation time 1670590000 ps
CPU time 5.63 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:33 PM PDT 24
Peak memory 164868 kb
Host smart-2e7b914c-3174-4e82-b39d-529860191635
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1756151450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1756151450
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.947820307
Short name T3
Test name
Test status
Simulation time 1537110000 ps
CPU time 4.95 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:30 PM PDT 24
Peak memory 164916 kb
Host smart-74032d72-0c45-4039-90c6-04982663a8cd
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=947820307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.947820307
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.889762710
Short name T70
Test name
Test status
Simulation time 1489230000 ps
CPU time 5.88 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:32 PM PDT 24
Peak memory 164820 kb
Host smart-8d30a9f2-0028-487c-b75e-de5f792ff5b3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=889762710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.889762710
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.2609520479
Short name T47
Test name
Test status
Simulation time 1628630000 ps
CPU time 6.1 seconds
Started Jul 14 06:00:19 PM PDT 24
Finished Jul 14 06:00:33 PM PDT 24
Peak memory 164836 kb
Host smart-5a1d6fec-d7fd-49f0-9d08-1b4f07947d85
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2609520479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.2609520479
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2486935282
Short name T41
Test name
Test status
Simulation time 1649650000 ps
CPU time 5.65 seconds
Started Jul 14 06:00:20 PM PDT 24
Finished Jul 14 06:00:34 PM PDT 24
Peak memory 164772 kb
Host smart-aa5f7024-df84-4318-ae80-614850af392b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2486935282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2486935282
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3182628964
Short name T50
Test name
Test status
Simulation time 1554410000 ps
CPU time 4.96 seconds
Started Jul 14 06:00:14 PM PDT 24
Finished Jul 14 06:00:25 PM PDT 24
Peak memory 164840 kb
Host smart-81c2ba74-8154-4e6b-be0d-21e28b31f80c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3182628964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.3182628964
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.103581546
Short name T9
Test name
Test status
Simulation time 1308790000 ps
CPU time 3.83 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 164812 kb
Host smart-e199b66e-c97e-4e1a-892a-dcac7e5513f0
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=103581546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.103581546
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.201964612
Short name T63
Test name
Test status
Simulation time 1564590000 ps
CPU time 5.31 seconds
Started Jul 14 06:00:26 PM PDT 24
Finished Jul 14 06:00:39 PM PDT 24
Peak memory 164904 kb
Host smart-f04b2568-3001-4b82-9130-941b6649111d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=201964612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.201964612
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.2041227590
Short name T42
Test name
Test status
Simulation time 1160870000 ps
CPU time 3.79 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 164920 kb
Host smart-2f5d0b26-2857-4246-a924-ef94e534fc9e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041227590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.2041227590
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1517923676
Short name T34
Test name
Test status
Simulation time 1379530000 ps
CPU time 4.67 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:39 PM PDT 24
Peak memory 164940 kb
Host smart-8c68fe7c-8e8b-4186-844d-49301149e275
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1517923676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1517923676
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4236891206
Short name T67
Test name
Test status
Simulation time 1462690000 ps
CPU time 3.83 seconds
Started Jul 14 06:00:29 PM PDT 24
Finished Jul 14 06:00:39 PM PDT 24
Peak memory 164924 kb
Host smart-650fd3c2-5451-4ec3-8cf1-93f62ac5a86a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4236891206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4236891206
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2000097608
Short name T55
Test name
Test status
Simulation time 1468230000 ps
CPU time 6.07 seconds
Started Jul 14 06:00:24 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 164924 kb
Host smart-8e9aa8a2-0568-4389-8038-4f8ea05a1456
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2000097608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2000097608
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2454726851
Short name T62
Test name
Test status
Simulation time 1564910000 ps
CPU time 6.36 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:41 PM PDT 24
Peak memory 164900 kb
Host smart-b534d9d6-dfc1-440a-b6a6-935b8f9ddbd7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454726851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2454726851
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1258708641
Short name T38
Test name
Test status
Simulation time 1281550000 ps
CPU time 4.14 seconds
Started Jul 14 06:00:29 PM PDT 24
Finished Jul 14 06:00:39 PM PDT 24
Peak memory 164804 kb
Host smart-59756171-e439-4f08-89d2-5af25bb97ef4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1258708641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.1258708641
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.419943416
Short name T1
Test name
Test status
Simulation time 1532990000 ps
CPU time 3.91 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:37 PM PDT 24
Peak memory 164788 kb
Host smart-bae2be0d-e459-499d-87e5-50e7e7b44c92
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=419943416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.419943416
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.795147746
Short name T53
Test name
Test status
Simulation time 1486730000 ps
CPU time 4.68 seconds
Started Jul 14 06:00:27 PM PDT 24
Finished Jul 14 06:00:39 PM PDT 24
Peak memory 164848 kb
Host smart-151eb295-2efd-40bf-9d82-33a6dab274e8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=795147746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.795147746
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.1638103446
Short name T13
Test name
Test status
Simulation time 1436230000 ps
CPU time 4.95 seconds
Started Jul 14 06:00:13 PM PDT 24
Finished Jul 14 06:00:24 PM PDT 24
Peak memory 164880 kb
Host smart-4e3f98ba-386c-407b-9b0c-ba5efcc83a4c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1638103446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.1638103446
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.308499028
Short name T66
Test name
Test status
Simulation time 1512430000 ps
CPU time 3.94 seconds
Started Jul 14 06:00:11 PM PDT 24
Finished Jul 14 06:00:21 PM PDT 24
Peak memory 164816 kb
Host smart-e9a14a46-f05c-4328-82e5-b28368102d5e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=308499028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.308499028
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.1265708209
Short name T44
Test name
Test status
Simulation time 1499650000 ps
CPU time 4.56 seconds
Started Jul 14 06:00:15 PM PDT 24
Finished Jul 14 06:00:25 PM PDT 24
Peak memory 164840 kb
Host smart-6a50a63d-39b0-47fc-944d-0c440da0848e
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1265708209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.1265708209
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.548306008
Short name T58
Test name
Test status
Simulation time 1497010000 ps
CPU time 5.04 seconds
Started Jul 14 06:00:13 PM PDT 24
Finished Jul 14 06:00:24 PM PDT 24
Peak memory 164804 kb
Host smart-3980ea02-10ef-4a7a-9f2a-3567784b20f5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=548306008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.548306008
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2177710836
Short name T57
Test name
Test status
Simulation time 1468370000 ps
CPU time 4.03 seconds
Started Jul 14 06:00:12 PM PDT 24
Finished Jul 14 06:00:22 PM PDT 24
Peak memory 164904 kb
Host smart-32ba50ba-047b-429a-99e8-c4c9fc0ef24d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177710836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2177710836
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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