Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1609035564
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4142914242
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.620902637

Tests that do not contribute to grading

Name
/workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1875433597
/workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2443501375
/workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.487597608
/workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2210528410
/workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.222495127
/workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4071477814
/workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2790884834
/workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1828535674
/workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2847963954
/workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3770399843
/workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1454651261
/workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1268731074
/workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2661646384
/workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.77833165
/workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2676541800
/workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.258576537
/workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.401990389
/workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1048923665
/workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2367348324
/workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3492063691
/workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2789565158
/workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2729161112
/workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3800453557
/workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3416906680
/workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1650781315
/workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1587815276
/workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1823062470
/workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1333373942
/workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.88659314
/workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.130665236
/workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3217563072
/workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3799635530
/workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4087773191
/workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1187102650
/workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3169377274
/workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2604878724
/workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3070256770
/workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.91287173
/workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4211588693
/workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3532479109
/workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1537978863
/workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1918999377
/workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.651767958
/workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1730443238
/workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2576931158
/workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1937914064
/workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1915437442
/workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1708345466
/workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2079400562
/workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.504951536
/workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.578529536
/workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2712308362
/workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2229239851
/workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2939212809
/workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1856108216
/workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1755678946
/workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1317689607
/workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.53017609
/workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1712942742
/workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3837264228
/workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3958344096
/workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.590518099
/workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1071542260
/workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2101874644
/workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.290529669
/workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3699023369
/workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3683444271
/workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1104286661
/workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2352066976
/workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3985865669
/workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2398903789
/workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1534795409
/workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2728975776
/workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1813662428
/workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1864242110
/workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3104055015
/workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.697797845
/workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.333559940
/workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1583089009
/workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1295165019
/workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3361113507
/workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2175331061
/workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.83677967
/workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1775527566
/workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1535737873
/workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3202139757
/workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3364168806
/workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3393761236
/workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1225458303
/workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1948180303
/workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2347635926
/workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.307723950
/workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2571490732
/workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3702414064
/workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1350563372
/workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2497606969
/workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1390282443
/workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2084756949
/workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2590864126
/workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.250427961
/workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.368150804
/workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.799317312
/workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1055374058
/workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3631120390
/workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1755891299
/workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2638828417
/workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1602738165
/workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3772115131
/workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.827580494
/workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1212663930
/workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2821064213
/workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2871916146
/workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1610165476
/workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4090955163
/workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1781947236
/workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1856505515
/workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3374281384
/workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3282893431
/workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.719671362
/workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.908435536
/workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2914145971
/workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4051493078
/workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2616076965
/workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3467015541
/workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1856555221
/workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3071632005
/workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3355675822
/workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2181530092
/workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3006031809
/workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1728514013
/workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.617800099
/workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3967780593
/workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2100187462
/workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1168499387
/workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2984093781
/workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3429099379
/workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1540088485
/workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2719203197
/workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3176978650
/workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1223455909
/workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2628577081
/workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4272597370
/workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.765038531
/workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2084404476
/workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3456842921
/workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1309295709
/workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1626511850
/workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2889966730
/workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1732337770
/workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1477611475
/workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2615180470
/workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2336556494
/workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1004532160
/workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3923403769
/workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1676911263
/workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.4110049399
/workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3133052986
/workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2605206536
/workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1861029065
/workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2795657086
/workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2673829739
/workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.691623163
/workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2866847993
/workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.126085839
/workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1044910954
/workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.538516105
/workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3887112159
/workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3567786847
/workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3001938351
/workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1811338879
/workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1780973608
/workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.695502459
/workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2101492424
/workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2105035974
/workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3818033697
/workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.356402063
/workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2347818793
/workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1328978387
/workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1944890957
/workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.898316806
/workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2262199997
/workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2465152155
/workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4164520077
/workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3711825856
/workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.592280269
/workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.872384018
/workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3203490380
/workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2439605501
/workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2359415522
/workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.184443579
/workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1643721047
/workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2703045438
/workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2864689373
/workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.823699962
/workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.442292744
/workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3297098401
/workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2228770989



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1643721047 Jul 24 04:22:04 PM PDT 24 Jul 24 04:22:16 PM PDT 24 1567850000 ps
T2 /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2673829739 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:51 PM PDT 24 1303730000 ps
T3 /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2359415522 Jul 24 04:22:03 PM PDT 24 Jul 24 04:22:12 PM PDT 24 1300110000 ps
T4 /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3711825856 Jul 24 04:21:03 PM PDT 24 Jul 24 04:21:13 PM PDT 24 1500310000 ps
T8 /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.823699962 Jul 24 04:25:45 PM PDT 24 Jul 24 04:25:54 PM PDT 24 1310910000 ps
T9 /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3567786847 Jul 24 04:25:29 PM PDT 24 Jul 24 04:25:37 PM PDT 24 1569350000 ps
T10 /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2864689373 Jul 24 04:25:02 PM PDT 24 Jul 24 04:25:11 PM PDT 24 1293950000 ps
T11 /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1609035564 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:52 PM PDT 24 1459150000 ps
T12 /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.538516105 Jul 24 04:22:27 PM PDT 24 Jul 24 04:22:37 PM PDT 24 1441950000 ps
T13 /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2795657086 Jul 24 04:21:20 PM PDT 24 Jul 24 04:21:28 PM PDT 24 1350190000 ps
T31 /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1732337770 Jul 24 04:22:56 PM PDT 24 Jul 24 04:23:06 PM PDT 24 1314170000 ps
T32 /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.872384018 Jul 24 04:22:03 PM PDT 24 Jul 24 04:22:14 PM PDT 24 1517290000 ps
T33 /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2262199997 Jul 24 04:21:43 PM PDT 24 Jul 24 04:21:53 PM PDT 24 1553410000 ps
T34 /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3133052986 Jul 24 04:24:57 PM PDT 24 Jul 24 04:25:07 PM PDT 24 1342390000 ps
T35 /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3923403769 Jul 24 04:25:46 PM PDT 24 Jul 24 04:25:55 PM PDT 24 1424830000 ps
T36 /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.898316806 Jul 24 04:21:12 PM PDT 24 Jul 24 04:21:20 PM PDT 24 1428270000 ps
T37 /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2866847993 Jul 24 04:25:02 PM PDT 24 Jul 24 04:25:11 PM PDT 24 1537590000 ps
T38 /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3818033697 Jul 24 04:25:06 PM PDT 24 Jul 24 04:25:15 PM PDT 24 1525270000 ps
T39 /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3001938351 Jul 24 04:25:09 PM PDT 24 Jul 24 04:25:19 PM PDT 24 1471750000 ps
T40 /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2439605501 Jul 24 04:21:03 PM PDT 24 Jul 24 04:21:12 PM PDT 24 1556410000 ps
T41 /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1044910954 Jul 24 04:23:50 PM PDT 24 Jul 24 04:23:59 PM PDT 24 1481810000 ps
T42 /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1861029065 Jul 24 04:25:16 PM PDT 24 Jul 24 04:25:25 PM PDT 24 1590930000 ps
T43 /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1477611475 Jul 24 04:25:02 PM PDT 24 Jul 24 04:25:12 PM PDT 24 1384750000 ps
T44 /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3887112159 Jul 24 04:25:47 PM PDT 24 Jul 24 04:25:54 PM PDT 24 1335310000 ps
T45 /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1811338879 Jul 24 04:23:01 PM PDT 24 Jul 24 04:23:10 PM PDT 24 1495790000 ps
T46 /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.184443579 Jul 24 04:25:20 PM PDT 24 Jul 24 04:25:28 PM PDT 24 1557870000 ps
T47 /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1944890957 Jul 24 04:22:35 PM PDT 24 Jul 24 04:22:46 PM PDT 24 1527990000 ps
T48 /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2465152155 Jul 24 04:25:22 PM PDT 24 Jul 24 04:25:31 PM PDT 24 1469650000 ps
T49 /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1676911263 Jul 24 04:24:56 PM PDT 24 Jul 24 04:25:07 PM PDT 24 1483590000 ps
T50 /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2615180470 Jul 24 04:25:09 PM PDT 24 Jul 24 04:25:17 PM PDT 24 1393230000 ps
T51 /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2605206536 Jul 24 04:25:00 PM PDT 24 Jul 24 04:25:09 PM PDT 24 1559530000 ps
T52 /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1004532160 Jul 24 04:24:00 PM PDT 24 Jul 24 04:24:08 PM PDT 24 1380970000 ps
T53 /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2336556494 Jul 24 04:25:10 PM PDT 24 Jul 24 04:25:18 PM PDT 24 1234210000 ps
T54 /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.126085839 Jul 24 04:22:19 PM PDT 24 Jul 24 04:22:28 PM PDT 24 1459130000 ps
T55 /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.442292744 Jul 24 04:25:23 PM PDT 24 Jul 24 04:25:31 PM PDT 24 1511490000 ps
T56 /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3297098401 Jul 24 04:25:22 PM PDT 24 Jul 24 04:25:29 PM PDT 24 1148870000 ps
T57 /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2105035974 Jul 24 04:25:06 PM PDT 24 Jul 24 04:25:15 PM PDT 24 1379430000 ps
T58 /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1328978387 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:28 PM PDT 24 1385550000 ps
T59 /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2101492424 Jul 24 04:22:20 PM PDT 24 Jul 24 04:22:29 PM PDT 24 1451470000 ps
T60 /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4164520077 Jul 24 04:25:23 PM PDT 24 Jul 24 04:25:30 PM PDT 24 1354690000 ps
T61 /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.4110049399 Jul 24 04:23:28 PM PDT 24 Jul 24 04:23:35 PM PDT 24 1293870000 ps
T62 /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.691623163 Jul 24 04:25:26 PM PDT 24 Jul 24 04:25:34 PM PDT 24 1320190000 ps
T63 /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.592280269 Jul 24 04:25:38 PM PDT 24 Jul 24 04:25:46 PM PDT 24 1499990000 ps
T64 /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2347818793 Jul 24 04:20:45 PM PDT 24 Jul 24 04:20:53 PM PDT 24 1508850000 ps
T65 /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2228770989 Jul 24 04:25:09 PM PDT 24 Jul 24 04:25:17 PM PDT 24 1366110000 ps
T66 /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.356402063 Jul 24 04:22:04 PM PDT 24 Jul 24 04:22:15 PM PDT 24 1584910000 ps
T67 /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2703045438 Jul 24 04:22:44 PM PDT 24 Jul 24 04:22:56 PM PDT 24 1529150000 ps
T68 /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.695502459 Jul 24 04:23:10 PM PDT 24 Jul 24 04:23:18 PM PDT 24 1498810000 ps
T69 /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3203490380 Jul 24 04:21:55 PM PDT 24 Jul 24 04:22:03 PM PDT 24 1434850000 ps
T70 /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1780973608 Jul 24 04:22:34 PM PDT 24 Jul 24 04:22:43 PM PDT 24 1423650000 ps
T5 /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1268731074 Jul 24 04:21:53 PM PDT 24 Jul 24 04:56:31 PM PDT 24 336577930000 ps
T6 /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3070256770 Jul 24 04:25:02 PM PDT 24 Jul 24 04:56:06 PM PDT 24 336323170000 ps
T7 /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4071477814 Jul 24 04:25:41 PM PDT 24 Jul 24 04:55:15 PM PDT 24 336945030000 ps
T14 /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.222495127 Jul 24 04:25:56 PM PDT 24 Jul 24 04:54:46 PM PDT 24 336506550000 ps
T15 /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4142914242 Jul 24 04:22:05 PM PDT 24 Jul 24 04:55:44 PM PDT 24 336929450000 ps
T16 /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1537978863 Jul 24 04:25:39 PM PDT 24 Jul 24 04:53:11 PM PDT 24 337065150000 ps
T17 /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1454651261 Jul 24 04:25:17 PM PDT 24 Jul 24 04:56:09 PM PDT 24 336752370000 ps
T18 /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3217563072 Jul 24 04:25:09 PM PDT 24 Jul 24 04:58:51 PM PDT 24 337135610000 ps
T19 /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1918999377 Jul 24 04:21:12 PM PDT 24 Jul 24 04:57:07 PM PDT 24 337015950000 ps
T20 /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1828535674 Jul 24 04:23:21 PM PDT 24 Jul 24 04:55:38 PM PDT 24 336343950000 ps
T71 /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.487597608 Jul 24 04:23:12 PM PDT 24 Jul 24 04:55:53 PM PDT 24 336670350000 ps
T72 /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.258576537 Jul 24 04:22:16 PM PDT 24 Jul 24 04:48:37 PM PDT 24 336789430000 ps
T73 /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2676541800 Jul 24 04:20:47 PM PDT 24 Jul 24 04:51:25 PM PDT 24 336931370000 ps
T74 /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1730443238 Jul 24 04:23:31 PM PDT 24 Jul 24 04:57:15 PM PDT 24 336849070000 ps
T75 /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2729161112 Jul 24 04:25:55 PM PDT 24 Jul 24 04:55:21 PM PDT 24 336935250000 ps
T76 /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1650781315 Jul 24 04:22:20 PM PDT 24 Jul 24 04:53:08 PM PDT 24 336990990000 ps
T77 /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3532479109 Jul 24 04:22:04 PM PDT 24 Jul 24 04:58:27 PM PDT 24 336968650000 ps
T78 /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2079400562 Jul 24 04:25:01 PM PDT 24 Jul 24 04:55:04 PM PDT 24 337144650000 ps
T79 /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2576931158 Jul 24 04:21:14 PM PDT 24 Jul 24 04:58:29 PM PDT 24 336574230000 ps
T80 /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2604878724 Jul 24 04:22:04 PM PDT 24 Jul 24 04:54:32 PM PDT 24 336473770000 ps
T81 /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2847963954 Jul 24 04:21:58 PM PDT 24 Jul 24 04:59:21 PM PDT 24 336565970000 ps
T82 /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2789565158 Jul 24 04:23:02 PM PDT 24 Jul 24 04:51:40 PM PDT 24 336382210000 ps
T83 /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.401990389 Jul 24 04:25:11 PM PDT 24 Jul 24 04:59:26 PM PDT 24 336980130000 ps
T84 /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1187102650 Jul 24 04:25:46 PM PDT 24 Jul 24 04:54:41 PM PDT 24 336837350000 ps
T85 /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3770399843 Jul 24 04:25:47 PM PDT 24 Jul 24 04:51:54 PM PDT 24 336586690000 ps
T86 /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4211588693 Jul 24 04:25:48 PM PDT 24 Jul 24 04:55:46 PM PDT 24 336585270000 ps
T87 /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.130665236 Jul 24 04:22:45 PM PDT 24 Jul 24 04:53:01 PM PDT 24 336616450000 ps
T88 /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1048923665 Jul 24 04:22:47 PM PDT 24 Jul 24 04:49:50 PM PDT 24 337057270000 ps
T89 /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.651767958 Jul 24 04:25:10 PM PDT 24 Jul 24 04:55:42 PM PDT 24 336907730000 ps
T90 /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2210528410 Jul 24 04:23:49 PM PDT 24 Jul 24 04:59:21 PM PDT 24 337106730000 ps
T91 /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2443501375 Jul 24 04:24:41 PM PDT 24 Jul 24 04:54:59 PM PDT 24 336899250000 ps
T92 /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1333373942 Jul 24 04:25:23 PM PDT 24 Jul 24 04:51:47 PM PDT 24 336949050000 ps
T93 /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2661646384 Jul 24 04:21:03 PM PDT 24 Jul 24 04:53:15 PM PDT 24 336477750000 ps
T94 /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4087773191 Jul 24 04:23:16 PM PDT 24 Jul 24 04:58:25 PM PDT 24 336563870000 ps
T95 /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1708345466 Jul 24 04:22:15 PM PDT 24 Jul 24 05:01:41 PM PDT 24 336663810000 ps
T96 /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.91287173 Jul 24 04:25:14 PM PDT 24 Jul 24 04:58:00 PM PDT 24 336785930000 ps
T97 /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3416906680 Jul 24 04:25:49 PM PDT 24 Jul 24 04:51:27 PM PDT 24 336762430000 ps
T98 /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3169377274 Jul 24 04:25:06 PM PDT 24 Jul 24 04:50:26 PM PDT 24 336308450000 ps
T99 /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2790884834 Jul 24 04:22:41 PM PDT 24 Jul 24 04:58:12 PM PDT 24 337063710000 ps
T100 /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1823062470 Jul 24 04:25:40 PM PDT 24 Jul 24 04:57:55 PM PDT 24 336875730000 ps
T101 /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1937914064 Jul 24 04:25:53 PM PDT 24 Jul 24 04:52:12 PM PDT 24 336439470000 ps
T102 /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.88659314 Jul 24 04:25:09 PM PDT 24 Jul 24 04:58:53 PM PDT 24 337017710000 ps
T103 /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3800453557 Jul 24 04:21:44 PM PDT 24 Jul 24 05:00:22 PM PDT 24 336769550000 ps
T104 /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2367348324 Jul 24 04:25:09 PM PDT 24 Jul 24 04:58:58 PM PDT 24 336293730000 ps
T105 /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.77833165 Jul 24 04:25:47 PM PDT 24 Jul 24 04:52:11 PM PDT 24 336601830000 ps
T106 /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1587815276 Jul 24 04:25:10 PM PDT 24 Jul 24 04:57:07 PM PDT 24 336432910000 ps
T107 /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1875433597 Jul 24 04:25:47 PM PDT 24 Jul 24 04:54:49 PM PDT 24 336431730000 ps
T108 /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1915437442 Jul 24 04:25:26 PM PDT 24 Jul 24 04:51:08 PM PDT 24 336741690000 ps
T109 /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3799635530 Jul 24 04:23:37 PM PDT 24 Jul 24 04:55:08 PM PDT 24 336487670000 ps
T110 /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3492063691 Jul 24 04:20:49 PM PDT 24 Jul 24 05:00:29 PM PDT 24 336638010000 ps
T111 /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2181530092 Jul 24 04:25:57 PM PDT 24 Jul 24 04:26:05 PM PDT 24 1622330000 ps
T112 /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3772115131 Jul 24 04:21:35 PM PDT 24 Jul 24 04:21:44 PM PDT 24 1446330000 ps
T113 /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.719671362 Jul 24 04:21:49 PM PDT 24 Jul 24 04:21:57 PM PDT 24 1436170000 ps
T114 /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2889966730 Jul 24 04:25:11 PM PDT 24 Jul 24 04:25:20 PM PDT 24 1427990000 ps
T115 /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1223455909 Jul 24 04:31:23 PM PDT 24 Jul 24 04:31:31 PM PDT 24 1338070000 ps
T116 /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1856555221 Jul 24 04:22:57 PM PDT 24 Jul 24 04:23:07 PM PDT 24 1538990000 ps
T117 /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3456842921 Jul 24 04:24:27 PM PDT 24 Jul 24 04:24:36 PM PDT 24 1240850000 ps
T118 /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.250427961 Jul 24 04:25:44 PM PDT 24 Jul 24 04:25:51 PM PDT 24 1532530000 ps
T119 /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4090955163 Jul 24 04:21:14 PM PDT 24 Jul 24 04:21:23 PM PDT 24 1417050000 ps
T120 /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1781947236 Jul 24 04:25:22 PM PDT 24 Jul 24 04:25:32 PM PDT 24 1519730000 ps
T121 /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3374281384 Jul 24 04:22:25 PM PDT 24 Jul 24 04:22:34 PM PDT 24 1454010000 ps
T122 /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1540088485 Jul 24 04:31:24 PM PDT 24 Jul 24 04:31:31 PM PDT 24 1296730000 ps
T123 /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.827580494 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:28 PM PDT 24 1368270000 ps
T124 /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2871916146 Jul 24 04:25:57 PM PDT 24 Jul 24 04:26:05 PM PDT 24 1317530000 ps
T125 /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.799317312 Jul 24 04:20:57 PM PDT 24 Jul 24 04:21:05 PM PDT 24 1370350000 ps
T126 /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3355675822 Jul 24 04:21:05 PM PDT 24 Jul 24 04:21:13 PM PDT 24 1593990000 ps
T127 /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1626511850 Jul 24 04:25:53 PM PDT 24 Jul 24 04:26:00 PM PDT 24 1521370000 ps
T128 /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1610165476 Jul 24 04:25:10 PM PDT 24 Jul 24 04:25:20 PM PDT 24 1500130000 ps
T129 /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1212663930 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:31 PM PDT 24 1401650000 ps
T130 /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2628577081 Jul 24 04:31:30 PM PDT 24 Jul 24 04:31:37 PM PDT 24 1157990000 ps
T131 /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3176978650 Jul 24 04:31:25 PM PDT 24 Jul 24 04:31:36 PM PDT 24 1609170000 ps
T132 /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3071632005 Jul 24 04:25:58 PM PDT 24 Jul 24 04:26:07 PM PDT 24 1458910000 ps
T133 /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2821064213 Jul 24 04:22:27 PM PDT 24 Jul 24 04:22:37 PM PDT 24 1555050000 ps
T134 /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.765038531 Jul 24 04:31:31 PM PDT 24 Jul 24 04:31:40 PM PDT 24 1340590000 ps
T135 /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2984093781 Jul 24 04:31:25 PM PDT 24 Jul 24 04:31:34 PM PDT 24 1349730000 ps
T136 /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2616076965 Jul 24 04:23:06 PM PDT 24 Jul 24 04:23:14 PM PDT 24 1363790000 ps
T137 /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4272597370 Jul 24 04:31:30 PM PDT 24 Jul 24 04:31:39 PM PDT 24 1406850000 ps
T138 /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1602738165 Jul 24 04:20:51 PM PDT 24 Jul 24 04:21:02 PM PDT 24 1484730000 ps
T139 /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3967780593 Jul 24 04:25:45 PM PDT 24 Jul 24 04:25:53 PM PDT 24 1178570000 ps
T140 /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2914145971 Jul 24 04:20:51 PM PDT 24 Jul 24 04:21:03 PM PDT 24 1552290000 ps
T141 /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.908435536 Jul 24 04:23:20 PM PDT 24 Jul 24 04:23:29 PM PDT 24 1414190000 ps
T142 /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.617800099 Jul 24 04:25:53 PM PDT 24 Jul 24 04:26:01 PM PDT 24 1318010000 ps
T143 /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3282893431 Jul 24 04:25:23 PM PDT 24 Jul 24 04:25:32 PM PDT 24 1350850000 ps
T144 /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3006031809 Jul 24 04:25:37 PM PDT 24 Jul 24 04:25:44 PM PDT 24 1012150000 ps
T145 /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2100187462 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:52 PM PDT 24 1538650000 ps
T146 /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1728514013 Jul 24 04:25:46 PM PDT 24 Jul 24 04:25:55 PM PDT 24 1576150000 ps
T147 /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3631120390 Jul 24 04:21:35 PM PDT 24 Jul 24 04:21:46 PM PDT 24 1603330000 ps
T148 /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3467015541 Jul 24 04:25:06 PM PDT 24 Jul 24 04:25:16 PM PDT 24 1607950000 ps
T149 /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1168499387 Jul 24 04:31:24 PM PDT 24 Jul 24 04:31:31 PM PDT 24 1385170000 ps
T150 /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4051493078 Jul 24 04:25:41 PM PDT 24 Jul 24 04:25:52 PM PDT 24 1489670000 ps
T151 /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2084404476 Jul 24 04:25:50 PM PDT 24 Jul 24 04:25:55 PM PDT 24 1123310000 ps
T152 /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2638828417 Jul 24 04:25:00 PM PDT 24 Jul 24 04:25:08 PM PDT 24 1380150000 ps
T153 /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1309295709 Jul 24 04:25:37 PM PDT 24 Jul 24 04:25:45 PM PDT 24 1328890000 ps
T154 /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3429099379 Jul 24 04:31:23 PM PDT 24 Jul 24 04:31:33 PM PDT 24 1552070000 ps
T155 /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2719203197 Jul 24 04:31:25 PM PDT 24 Jul 24 04:31:32 PM PDT 24 1380510000 ps
T156 /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1055374058 Jul 24 04:25:16 PM PDT 24 Jul 24 04:25:26 PM PDT 24 1641510000 ps
T157 /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1856505515 Jul 24 04:25:21 PM PDT 24 Jul 24 04:25:31 PM PDT 24 1496570000 ps
T158 /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1755891299 Jul 24 04:22:20 PM PDT 24 Jul 24 04:22:28 PM PDT 24 1460350000 ps
T159 /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.368150804 Jul 24 04:21:39 PM PDT 24 Jul 24 04:21:48 PM PDT 24 1364250000 ps
T160 /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2590864126 Jul 24 04:21:48 PM PDT 24 Jul 24 04:21:57 PM PDT 24 1366590000 ps
T21 /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.307723950 Jul 24 04:31:38 PM PDT 24 Jul 24 05:01:02 PM PDT 24 336353150000 ps
T22 /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2084756949 Jul 24 04:25:25 PM PDT 24 Jul 24 04:52:51 PM PDT 24 336539430000 ps
T23 /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3202139757 Jul 24 04:31:29 PM PDT 24 Jul 24 05:03:45 PM PDT 24 336599110000 ps
T24 /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2728975776 Jul 24 04:25:52 PM PDT 24 Jul 24 04:50:15 PM PDT 24 336511830000 ps
T25 /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.620902637 Jul 24 04:20:58 PM PDT 24 Jul 24 04:51:58 PM PDT 24 336858990000 ps
T26 /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.290529669 Jul 24 04:21:47 PM PDT 24 Jul 24 04:53:46 PM PDT 24 336764570000 ps
T27 /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3837264228 Jul 24 04:25:10 PM PDT 24 Jul 24 04:59:24 PM PDT 24 336600190000 ps
T28 /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3393761236 Jul 24 04:31:29 PM PDT 24 Jul 24 04:59:50 PM PDT 24 336334790000 ps
T29 /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2497606969 Jul 24 04:25:14 PM PDT 24 Jul 24 04:55:31 PM PDT 24 336479290000 ps
T30 /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1104286661 Jul 24 04:21:58 PM PDT 24 Jul 24 04:59:18 PM PDT 24 336601290000 ps
T161 /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1534795409 Jul 24 04:21:44 PM PDT 24 Jul 24 04:59:59 PM PDT 24 336872890000 ps
T162 /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2175331061 Jul 24 04:31:30 PM PDT 24 Jul 24 05:00:53 PM PDT 24 336762590000 ps
T163 /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.697797845 Jul 24 04:21:09 PM PDT 24 Jul 24 04:57:17 PM PDT 24 336374170000 ps
T164 /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2939212809 Jul 24 04:21:11 PM PDT 24 Jul 24 04:55:42 PM PDT 24 336957330000 ps
T165 /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3104055015 Jul 24 04:25:49 PM PDT 24 Jul 24 04:56:38 PM PDT 24 336358390000 ps
T166 /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.53017609 Jul 24 04:22:27 PM PDT 24 Jul 24 04:57:18 PM PDT 24 336344410000 ps
T167 /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3985865669 Jul 24 04:25:39 PM PDT 24 Jul 24 04:56:36 PM PDT 24 336739990000 ps
T168 /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2571490732 Jul 24 04:31:38 PM PDT 24 Jul 24 05:02:47 PM PDT 24 336960590000 ps
T169 /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1864242110 Jul 24 04:22:19 PM PDT 24 Jul 24 04:48:29 PM PDT 24 336389530000 ps
T170 /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2398903789 Jul 24 04:20:36 PM PDT 24 Jul 24 05:00:21 PM PDT 24 337007910000 ps
T171 /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1317689607 Jul 24 04:25:41 PM PDT 24 Jul 24 04:54:52 PM PDT 24 336490510000 ps
T172 /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2352066976 Jul 24 04:21:18 PM PDT 24 Jul 24 04:57:03 PM PDT 24 336876490000 ps
T173 /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.333559940 Jul 24 04:25:48 PM PDT 24 Jul 24 04:57:01 PM PDT 24 337083110000 ps
T174 /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1856108216 Jul 24 04:22:18 PM PDT 24 Jul 24 04:53:58 PM PDT 24 336723430000 ps
T175 /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.83677967 Jul 24 04:21:52 PM PDT 24 Jul 24 04:56:33 PM PDT 24 336814270000 ps
T176 /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1775527566 Jul 24 04:31:30 PM PDT 24 Jul 24 04:57:48 PM PDT 24 336612850000 ps
T177 /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.590518099 Jul 24 04:25:10 PM PDT 24 Jul 24 04:58:27 PM PDT 24 336954670000 ps
T178 /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1813662428 Jul 24 04:25:28 PM PDT 24 Jul 24 04:50:50 PM PDT 24 336643150000 ps
T179 /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1583089009 Jul 24 04:31:29 PM PDT 24 Jul 24 04:58:18 PM PDT 24 336350670000 ps
T180 /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2101874644 Jul 24 04:25:09 PM PDT 24 Jul 24 04:59:03 PM PDT 24 337011110000 ps
T181 /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1071542260 Jul 24 04:23:53 PM PDT 24 Jul 24 04:56:27 PM PDT 24 337079510000 ps
T182 /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.504951536 Jul 24 04:26:00 PM PDT 24 Jul 24 04:59:08 PM PDT 24 337006630000 ps
T183 /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1755678946 Jul 24 04:25:54 PM PDT 24 Jul 24 04:52:31 PM PDT 24 336896030000 ps
T184 /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2347635926 Jul 24 04:31:36 PM PDT 24 Jul 24 05:02:49 PM PDT 24 336550370000 ps
T185 /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1390282443 Jul 24 04:22:17 PM PDT 24 Jul 24 04:56:26 PM PDT 24 336711370000 ps
T186 /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3699023369 Jul 24 04:21:35 PM PDT 24 Jul 24 04:55:54 PM PDT 24 336880150000 ps
T187 /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1225458303 Jul 24 04:31:36 PM PDT 24 Jul 24 05:01:32 PM PDT 24 336355990000 ps
T188 /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1350563372 Jul 24 04:21:52 PM PDT 24 Jul 24 04:56:14 PM PDT 24 336322010000 ps
T189 /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3361113507 Jul 24 04:31:29 PM PDT 24 Jul 24 04:58:32 PM PDT 24 336902370000 ps
T190 /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2712308362 Jul 24 04:24:57 PM PDT 24 Jul 24 04:55:36 PM PDT 24 336694270000 ps
T191 /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3958344096 Jul 24 04:26:01 PM PDT 24 Jul 24 04:58:51 PM PDT 24 337059310000 ps
T192 /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2229239851 Jul 24 04:25:16 PM PDT 24 Jul 24 04:56:33 PM PDT 24 336637850000 ps
T193 /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.578529536 Jul 24 04:21:17 PM PDT 24 Jul 24 04:52:57 PM PDT 24 336413970000 ps
T194 /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1535737873 Jul 24 04:31:28 PM PDT 24 Jul 24 05:00:55 PM PDT 24 336790470000 ps
T195 /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3702414064 Jul 24 04:26:00 PM PDT 24 Jul 24 04:59:14 PM PDT 24 336373870000 ps
T196 /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1712942742 Jul 24 04:25:11 PM PDT 24 Jul 24 04:56:57 PM PDT 24 336337050000 ps
T197 /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1295165019 Jul 24 04:31:31 PM PDT 24 Jul 24 05:05:45 PM PDT 24 336437210000 ps
T198 /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3683444271 Jul 24 04:25:27 PM PDT 24 Jul 24 04:55:43 PM PDT 24 336675430000 ps
T199 /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3364168806 Jul 24 04:31:29 PM PDT 24 Jul 24 04:58:23 PM PDT 24 336896370000 ps
T200 /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1948180303 Jul 24 04:31:38 PM PDT 24 Jul 24 05:03:19 PM PDT 24 336485890000 ps

Test location /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1609035564
Short name T11
Test name
Test status
Simulation time 1459150000 ps
CPU time 4.51 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:52 PM PDT 24
Peak memory 164696 kb
Host smart-c58850d1-c316-4864-a142-9319c1ca4fc8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1609035564 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1609035564
Directory /workspace/19.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.4142914242
Short name T15
Test name
Test status
Simulation time 336929450000 ps
CPU time 824.94 seconds
Started Jul 24 04:22:05 PM PDT 24
Finished Jul 24 04:55:44 PM PDT 24
Peak memory 160692 kb
Host smart-33879a4c-63ec-49d7-8658-bb645ed41a54
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4142914242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.4142914242
Directory /workspace/0.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.620902637
Short name T25
Test name
Test status
Simulation time 336858990000 ps
CPU time 756.6 seconds
Started Jul 24 04:20:58 PM PDT 24
Finished Jul 24 04:51:58 PM PDT 24
Peak memory 160684 kb
Host smart-ba18e277-1288-43ae-ab3a-09674cf5cb20
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=620902637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.620902637
Directory /workspace/13.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.1875433597
Short name T107
Test name
Test status
Simulation time 336431730000 ps
CPU time 708.77 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:54:49 PM PDT 24
Peak memory 160420 kb
Host smart-f7f23628-4484-402d-8b1f-e1a236da2a8a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1875433597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.1875433597
Directory /workspace/1.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2443501375
Short name T91
Test name
Test status
Simulation time 336899250000 ps
CPU time 729.74 seconds
Started Jul 24 04:24:41 PM PDT 24
Finished Jul 24 04:54:59 PM PDT 24
Peak memory 159168 kb
Host smart-132722bd-b657-4b50-bb44-bdbb3453aecf
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2443501375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.2443501375
Directory /workspace/10.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.487597608
Short name T71
Test name
Test status
Simulation time 336670350000 ps
CPU time 803.79 seconds
Started Jul 24 04:23:12 PM PDT 24
Finished Jul 24 04:55:53 PM PDT 24
Peak memory 160628 kb
Host smart-5839c68a-aa5a-4b0f-ab3e-983631e06a91
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=487597608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.487597608
Directory /workspace/11.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.2210528410
Short name T90
Test name
Test status
Simulation time 337106730000 ps
CPU time 850.11 seconds
Started Jul 24 04:23:49 PM PDT 24
Finished Jul 24 04:59:21 PM PDT 24
Peak memory 160656 kb
Host smart-e68bf849-9574-41a4-8b3c-b470b413b205
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2210528410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.2210528410
Directory /workspace/12.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.222495127
Short name T14
Test name
Test status
Simulation time 336506550000 ps
CPU time 699.27 seconds
Started Jul 24 04:25:56 PM PDT 24
Finished Jul 24 04:54:46 PM PDT 24
Peak memory 160604 kb
Host smart-b5e46482-5fe8-4b72-b2b5-eb14b61dc70a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=222495127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.222495127
Directory /workspace/13.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.4071477814
Short name T7
Test name
Test status
Simulation time 336945030000 ps
CPU time 718.3 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:55:15 PM PDT 24
Peak memory 160608 kb
Host smart-be72d32d-4ec5-48cc-8a7b-cc7b1b207d3f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4071477814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.4071477814
Directory /workspace/14.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2790884834
Short name T99
Test name
Test status
Simulation time 337063710000 ps
CPU time 853.89 seconds
Started Jul 24 04:22:41 PM PDT 24
Finished Jul 24 04:58:12 PM PDT 24
Peak memory 160764 kb
Host smart-b83ccfdb-ff2e-4f13-87b5-74b5704d709d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2790884834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2790884834
Directory /workspace/15.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1828535674
Short name T20
Test name
Test status
Simulation time 336343950000 ps
CPU time 784.4 seconds
Started Jul 24 04:23:21 PM PDT 24
Finished Jul 24 04:55:38 PM PDT 24
Peak memory 160688 kb
Host smart-7e0ba1c3-ca32-4075-be8f-645243e9af68
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1828535674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1828535674
Directory /workspace/16.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2847963954
Short name T81
Test name
Test status
Simulation time 336565970000 ps
CPU time 896.86 seconds
Started Jul 24 04:21:58 PM PDT 24
Finished Jul 24 04:59:21 PM PDT 24
Peak memory 160880 kb
Host smart-ae64d9f0-7185-4c72-926e-8e61bafb4b9f
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2847963954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2847963954
Directory /workspace/17.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.3770399843
Short name T85
Test name
Test status
Simulation time 336586690000 ps
CPU time 630.39 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:51:54 PM PDT 24
Peak memory 160588 kb
Host smart-4664580c-6b3d-4ef7-be7e-f2ed545663a8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3770399843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.3770399843
Directory /workspace/18.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.1454651261
Short name T17
Test name
Test status
Simulation time 336752370000 ps
CPU time 736.16 seconds
Started Jul 24 04:25:17 PM PDT 24
Finished Jul 24 04:56:09 PM PDT 24
Peak memory 160632 kb
Host smart-c6008015-3cb6-4f55-a4a3-d2bf034221e5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1454651261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.1454651261
Directory /workspace/19.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1268731074
Short name T5
Test name
Test status
Simulation time 336577930000 ps
CPU time 837.27 seconds
Started Jul 24 04:21:53 PM PDT 24
Finished Jul 24 04:56:31 PM PDT 24
Peak memory 160672 kb
Host smart-83831c72-3ed8-4e05-81f3-208edb436417
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1268731074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1268731074
Directory /workspace/2.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2661646384
Short name T93
Test name
Test status
Simulation time 336477750000 ps
CPU time 776.39 seconds
Started Jul 24 04:21:03 PM PDT 24
Finished Jul 24 04:53:15 PM PDT 24
Peak memory 160644 kb
Host smart-7bfbb29d-07f7-4a9a-8e49-af19a6897c15
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2661646384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.2661646384
Directory /workspace/20.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.77833165
Short name T105
Test name
Test status
Simulation time 336601830000 ps
CPU time 635.41 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:52:11 PM PDT 24
Peak memory 160580 kb
Host smart-67fa0767-c516-4384-a61d-53d35c8eaf7e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=77833165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.77833165
Directory /workspace/21.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2676541800
Short name T73
Test name
Test status
Simulation time 336931370000 ps
CPU time 745.87 seconds
Started Jul 24 04:20:47 PM PDT 24
Finished Jul 24 04:51:25 PM PDT 24
Peak memory 160668 kb
Host smart-6a31e26b-6475-40d3-b03e-a09253d85d14
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2676541800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2676541800
Directory /workspace/22.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.258576537
Short name T72
Test name
Test status
Simulation time 336789430000 ps
CPU time 653 seconds
Started Jul 24 04:22:16 PM PDT 24
Finished Jul 24 04:48:37 PM PDT 24
Peak memory 160564 kb
Host smart-71e12a82-c9f3-4af2-9de0-2fc79afba8c5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=258576537 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.258576537
Directory /workspace/23.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.401990389
Short name T83
Test name
Test status
Simulation time 336980130000 ps
CPU time 813.52 seconds
Started Jul 24 04:25:11 PM PDT 24
Finished Jul 24 04:59:26 PM PDT 24
Peak memory 160404 kb
Host smart-289db1f1-b447-4840-b53d-d8c9e0a123ca
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=401990389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.401990389
Directory /workspace/24.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.1048923665
Short name T88
Test name
Test status
Simulation time 337057270000 ps
CPU time 659.02 seconds
Started Jul 24 04:22:47 PM PDT 24
Finished Jul 24 04:49:50 PM PDT 24
Peak memory 160640 kb
Host smart-fb022081-670a-43eb-8250-ceb955707fc6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1048923665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.1048923665
Directory /workspace/25.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2367348324
Short name T104
Test name
Test status
Simulation time 336293730000 ps
CPU time 812.12 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:58:58 PM PDT 24
Peak memory 159296 kb
Host smart-331c03b1-4002-4155-9e0c-d72a1e018361
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2367348324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2367348324
Directory /workspace/26.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3492063691
Short name T110
Test name
Test status
Simulation time 336638010000 ps
CPU time 940.63 seconds
Started Jul 24 04:20:49 PM PDT 24
Finished Jul 24 05:00:29 PM PDT 24
Peak memory 160560 kb
Host smart-8928736b-82d4-4b0e-8976-eb967e6a2d33
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3492063691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.3492063691
Directory /workspace/27.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2789565158
Short name T82
Test name
Test status
Simulation time 336382210000 ps
CPU time 697.5 seconds
Started Jul 24 04:23:02 PM PDT 24
Finished Jul 24 04:51:40 PM PDT 24
Peak memory 160636 kb
Host smart-c56d25dd-a74b-46de-8eae-9b586935ad0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2789565158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2789565158
Directory /workspace/28.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2729161112
Short name T75
Test name
Test status
Simulation time 336935250000 ps
CPU time 718.39 seconds
Started Jul 24 04:25:55 PM PDT 24
Finished Jul 24 04:55:21 PM PDT 24
Peak memory 160612 kb
Host smart-db4a3c2f-9046-4a13-b3a8-5eac9025caf6
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2729161112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2729161112
Directory /workspace/29.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3800453557
Short name T103
Test name
Test status
Simulation time 336769550000 ps
CPU time 905.38 seconds
Started Jul 24 04:21:44 PM PDT 24
Finished Jul 24 05:00:22 PM PDT 24
Peak memory 160648 kb
Host smart-3c7729da-903d-41ea-865f-209edc29ff0d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3800453557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3800453557
Directory /workspace/3.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3416906680
Short name T97
Test name
Test status
Simulation time 336762430000 ps
CPU time 618.38 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:51:27 PM PDT 24
Peak memory 160416 kb
Host smart-5160b4bf-52ea-4408-89a0-daecd89e774d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3416906680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.3416906680
Directory /workspace/30.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1650781315
Short name T76
Test name
Test status
Simulation time 336990990000 ps
CPU time 753.94 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:53:08 PM PDT 24
Peak memory 160636 kb
Host smart-7bf237ad-06e0-4d50-872f-f5986e788872
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1650781315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.1650781315
Directory /workspace/31.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1587815276
Short name T106
Test name
Test status
Simulation time 336432910000 ps
CPU time 759.35 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:57:07 PM PDT 24
Peak memory 160420 kb
Host smart-29a5c67d-9eec-472d-95c8-f22d3536c978
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1587815276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.1587815276
Directory /workspace/32.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.1823062470
Short name T100
Test name
Test status
Simulation time 336875730000 ps
CPU time 783.2 seconds
Started Jul 24 04:25:40 PM PDT 24
Finished Jul 24 04:57:55 PM PDT 24
Peak memory 160540 kb
Host smart-9e198e39-a64a-4cdc-a514-86d8bc6b7480
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1823062470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.1823062470
Directory /workspace/33.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1333373942
Short name T92
Test name
Test status
Simulation time 336949050000 ps
CPU time 644.6 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:51:47 PM PDT 24
Peak memory 160324 kb
Host smart-b993e8f0-12f2-48fb-ac8a-a4403898c14e
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1333373942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.1333373942
Directory /workspace/34.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.88659314
Short name T102
Test name
Test status
Simulation time 337017710000 ps
CPU time 806.66 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:58:53 PM PDT 24
Peak memory 160296 kb
Host smart-78e1f944-f397-4c6e-9abb-d7a56d40dbf9
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=88659314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.88659314
Directory /workspace/35.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.130665236
Short name T87
Test name
Test status
Simulation time 336616450000 ps
CPU time 737.03 seconds
Started Jul 24 04:22:45 PM PDT 24
Finished Jul 24 04:53:01 PM PDT 24
Peak memory 160660 kb
Host smart-4af73c83-3433-473e-b8ec-30ba0ec095d5
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=130665236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.130665236
Directory /workspace/36.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.3217563072
Short name T18
Test name
Test status
Simulation time 337135610000 ps
CPU time 801.81 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:58:51 PM PDT 24
Peak memory 159292 kb
Host smart-dc60c033-ebe6-4e81-9a1a-be33268444d4
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3217563072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.3217563072
Directory /workspace/37.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.3799635530
Short name T109
Test name
Test status
Simulation time 336487670000 ps
CPU time 766.93 seconds
Started Jul 24 04:23:37 PM PDT 24
Finished Jul 24 04:55:08 PM PDT 24
Peak memory 160688 kb
Host smart-c6059afe-2bf7-4a05-b03e-6846cf751050
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3799635530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.3799635530
Directory /workspace/38.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4087773191
Short name T94
Test name
Test status
Simulation time 336563870000 ps
CPU time 842.98 seconds
Started Jul 24 04:23:16 PM PDT 24
Finished Jul 24 04:58:25 PM PDT 24
Peak memory 160764 kb
Host smart-16d9adb5-51f5-42a2-b60c-93fa97179a84
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4087773191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4087773191
Directory /workspace/39.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1187102650
Short name T84
Test name
Test status
Simulation time 336837350000 ps
CPU time 701.33 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:54:41 PM PDT 24
Peak memory 160300 kb
Host smart-2884d0fb-c11a-4ec8-ab44-656cd4cc5ef0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1187102650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.1187102650
Directory /workspace/4.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.3169377274
Short name T98
Test name
Test status
Simulation time 336308450000 ps
CPU time 613.68 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:50:26 PM PDT 24
Peak memory 159664 kb
Host smart-486c5bcd-4958-4613-bd8b-2681ec1e7b1a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3169377274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.3169377274
Directory /workspace/40.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.2604878724
Short name T80
Test name
Test status
Simulation time 336473770000 ps
CPU time 780.91 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:54:32 PM PDT 24
Peak memory 160504 kb
Host smart-03551585-8cd5-4690-922c-312f39c49393
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2604878724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.2604878724
Directory /workspace/41.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.3070256770
Short name T6
Test name
Test status
Simulation time 336323170000 ps
CPU time 756.83 seconds
Started Jul 24 04:25:02 PM PDT 24
Finished Jul 24 04:56:06 PM PDT 24
Peak memory 159416 kb
Host smart-095aa5ff-d336-4a46-8ac1-d8fc458f90a8
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3070256770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.3070256770
Directory /workspace/42.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.91287173
Short name T96
Test name
Test status
Simulation time 336785930000 ps
CPU time 794.36 seconds
Started Jul 24 04:25:14 PM PDT 24
Finished Jul 24 04:58:00 PM PDT 24
Peak memory 160556 kb
Host smart-d08cc279-8c61-4027-b000-45119cf18c11
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=91287173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.91287173
Directory /workspace/43.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.4211588693
Short name T86
Test name
Test status
Simulation time 336585270000 ps
CPU time 728.51 seconds
Started Jul 24 04:25:48 PM PDT 24
Finished Jul 24 04:55:46 PM PDT 24
Peak memory 160604 kb
Host smart-acd020aa-a258-4d88-b77d-dfe5d970bda0
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4211588693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.4211588693
Directory /workspace/44.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.3532479109
Short name T77
Test name
Test status
Simulation time 336968650000 ps
CPU time 879.06 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:58:27 PM PDT 24
Peak memory 160652 kb
Host smart-bd2490d2-8047-4b09-827e-e3aebc89999b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3532479109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.3532479109
Directory /workspace/45.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1537978863
Short name T16
Test name
Test status
Simulation time 337065150000 ps
CPU time 672.17 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:53:11 PM PDT 24
Peak memory 160564 kb
Host smart-ede17a58-5d18-40f7-ac07-1fd63dd80f64
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1537978863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.1537978863
Directory /workspace/46.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.1918999377
Short name T19
Test name
Test status
Simulation time 337015950000 ps
CPU time 867.51 seconds
Started Jul 24 04:21:12 PM PDT 24
Finished Jul 24 04:57:07 PM PDT 24
Peak memory 160760 kb
Host smart-46325615-038b-4cba-afb7-c3aea3b4160d
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1918999377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.1918999377
Directory /workspace/47.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.651767958
Short name T89
Test name
Test status
Simulation time 336907730000 ps
CPU time 758.75 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:55:42 PM PDT 24
Peak memory 160460 kb
Host smart-9cb1c78f-5c02-444d-9456-320d98ccdc52
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=651767958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.651767958
Directory /workspace/48.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1730443238
Short name T74
Test name
Test status
Simulation time 336849070000 ps
CPU time 828.08 seconds
Started Jul 24 04:23:31 PM PDT 24
Finished Jul 24 04:57:15 PM PDT 24
Peak memory 160692 kb
Host smart-319d4cd9-cacb-4b98-8bab-d507c28724c1
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1730443238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.1730443238
Directory /workspace/49.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2576931158
Short name T79
Test name
Test status
Simulation time 336574230000 ps
CPU time 908.74 seconds
Started Jul 24 04:21:14 PM PDT 24
Finished Jul 24 04:58:29 PM PDT 24
Peak memory 160880 kb
Host smart-e54157c2-60b6-4399-af99-85e99343a33a
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2576931158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2576931158
Directory /workspace/5.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.1937914064
Short name T101
Test name
Test status
Simulation time 336439470000 ps
CPU time 636.86 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:52:12 PM PDT 24
Peak memory 160612 kb
Host smart-e6cae961-5541-4909-bdba-f13a879973b3
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1937914064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.1937914064
Directory /workspace/6.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.1915437442
Short name T108
Test name
Test status
Simulation time 336741690000 ps
CPU time 624.51 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:51:08 PM PDT 24
Peak memory 159240 kb
Host smart-e1946252-3f95-4505-8c87-83e4e75a948b
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1915437442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.1915437442
Directory /workspace/7.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1708345466
Short name T95
Test name
Test status
Simulation time 336663810000 ps
CPU time 952.47 seconds
Started Jul 24 04:22:15 PM PDT 24
Finished Jul 24 05:01:41 PM PDT 24
Peak memory 160648 kb
Host smart-d5926ba2-4e49-491f-a376-e4b715076955
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1708345466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1708345466
Directory /workspace/8.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.2079400562
Short name T78
Test name
Test status
Simulation time 337144650000 ps
CPU time 714.72 seconds
Started Jul 24 04:25:01 PM PDT 24
Finished Jul 24 04:55:04 PM PDT 24
Peak memory 160276 kb
Host smart-4cf06e23-8e70-481d-b583-884e3fb4cc92
User root
Command /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2079400562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.2079400562
Directory /workspace/9.prim_lfsr_fib_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.504951536
Short name T182
Test name
Test status
Simulation time 337006630000 ps
CPU time 796.57 seconds
Started Jul 24 04:26:00 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 160572 kb
Host smart-2c59bcaf-e3a9-46ee-b71d-175f6d8cfc9b
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=504951536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.504951536
Directory /workspace/0.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.578529536
Short name T193
Test name
Test status
Simulation time 336413970000 ps
CPU time 781.81 seconds
Started Jul 24 04:21:17 PM PDT 24
Finished Jul 24 04:52:57 PM PDT 24
Peak memory 160624 kb
Host smart-1e3fbe43-37a2-4c0f-bb2a-6e579d68e75c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=578529536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.578529536
Directory /workspace/1.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.2712308362
Short name T190
Test name
Test status
Simulation time 336694270000 ps
CPU time 744.03 seconds
Started Jul 24 04:24:57 PM PDT 24
Finished Jul 24 04:55:36 PM PDT 24
Peak memory 160600 kb
Host smart-8bc31112-2e27-4a33-ad07-0934fa156abb
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2712308362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.2712308362
Directory /workspace/10.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2229239851
Short name T192
Test name
Test status
Simulation time 336637850000 ps
CPU time 756.72 seconds
Started Jul 24 04:25:16 PM PDT 24
Finished Jul 24 04:56:33 PM PDT 24
Peak memory 160564 kb
Host smart-bbafd0de-2e5e-43fa-bfc4-7fdb21bec2d7
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2229239851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2229239851
Directory /workspace/11.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.2939212809
Short name T164
Test name
Test status
Simulation time 336957330000 ps
CPU time 836.58 seconds
Started Jul 24 04:21:11 PM PDT 24
Finished Jul 24 04:55:42 PM PDT 24
Peak memory 160656 kb
Host smart-96d63913-0ecf-42ea-a06a-b399b40b06be
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2939212809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.2939212809
Directory /workspace/12.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1856108216
Short name T174
Test name
Test status
Simulation time 336723430000 ps
CPU time 760.45 seconds
Started Jul 24 04:22:18 PM PDT 24
Finished Jul 24 04:53:58 PM PDT 24
Peak memory 160664 kb
Host smart-6f159c1d-7ee7-4f3b-8159-97d0ee0100fc
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1856108216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1856108216
Directory /workspace/14.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.1755678946
Short name T183
Test name
Test status
Simulation time 336896030000 ps
CPU time 642.15 seconds
Started Jul 24 04:25:54 PM PDT 24
Finished Jul 24 04:52:31 PM PDT 24
Peak memory 160620 kb
Host smart-467ee534-f048-45be-92f5-5db97acdd630
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1755678946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.1755678946
Directory /workspace/15.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.1317689607
Short name T171
Test name
Test status
Simulation time 336490510000 ps
CPU time 710.24 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:54:52 PM PDT 24
Peak memory 160612 kb
Host smart-c67b5cbb-1f7f-4cb6-8334-c6924f464282
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1317689607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.1317689607
Directory /workspace/16.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.53017609
Short name T166
Test name
Test status
Simulation time 336344410000 ps
CPU time 834.63 seconds
Started Jul 24 04:22:27 PM PDT 24
Finished Jul 24 04:57:18 PM PDT 24
Peak memory 160732 kb
Host smart-5cb54e73-c439-4196-b37e-8ea9bbe12c49
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=53017609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.53017609
Directory /workspace/17.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1712942742
Short name T196
Test name
Test status
Simulation time 336337050000 ps
CPU time 751.22 seconds
Started Jul 24 04:25:11 PM PDT 24
Finished Jul 24 04:56:57 PM PDT 24
Peak memory 160452 kb
Host smart-7c1a5994-e857-4986-a715-016e587cd229
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1712942742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.1712942742
Directory /workspace/18.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.3837264228
Short name T27
Test name
Test status
Simulation time 336600190000 ps
CPU time 818.06 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:59:24 PM PDT 24
Peak memory 160240 kb
Host smart-4665a740-e79d-4958-8069-d8bb41be8837
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3837264228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.3837264228
Directory /workspace/19.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3958344096
Short name T191
Test name
Test status
Simulation time 337059310000 ps
CPU time 788.55 seconds
Started Jul 24 04:26:01 PM PDT 24
Finished Jul 24 04:58:51 PM PDT 24
Peak memory 160580 kb
Host smart-a1d491e9-c4db-452f-884b-3ffc95cb3c34
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3958344096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3958344096
Directory /workspace/2.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.590518099
Short name T177
Test name
Test status
Simulation time 336954670000 ps
CPU time 797.88 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:58:27 PM PDT 24
Peak memory 160400 kb
Host smart-a339383d-57ca-4954-b7d7-994f99804934
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=590518099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.590518099
Directory /workspace/20.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1071542260
Short name T181
Test name
Test status
Simulation time 337079510000 ps
CPU time 808.45 seconds
Started Jul 24 04:23:53 PM PDT 24
Finished Jul 24 04:56:27 PM PDT 24
Peak memory 160644 kb
Host smart-7fd54149-2211-4caf-ab72-45daca8fcf47
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1071542260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1071542260
Directory /workspace/21.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2101874644
Short name T180
Test name
Test status
Simulation time 337011110000 ps
CPU time 813.13 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 160336 kb
Host smart-6a4dd354-13f1-4ce3-8c49-3af30e8797bd
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2101874644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2101874644
Directory /workspace/22.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.290529669
Short name T26
Test name
Test status
Simulation time 336764570000 ps
CPU time 779.78 seconds
Started Jul 24 04:21:47 PM PDT 24
Finished Jul 24 04:53:46 PM PDT 24
Peak memory 160628 kb
Host smart-6ee72209-9860-480a-9f5f-a2e7f68efd06
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=290529669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.290529669
Directory /workspace/23.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3699023369
Short name T186
Test name
Test status
Simulation time 336880150000 ps
CPU time 839.51 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:55:54 PM PDT 24
Peak memory 160696 kb
Host smart-155c87e4-44a3-4fb7-ac8f-f2e1beeb6a1c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3699023369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3699023369
Directory /workspace/24.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3683444271
Short name T198
Test name
Test status
Simulation time 336675430000 ps
CPU time 724.86 seconds
Started Jul 24 04:25:27 PM PDT 24
Finished Jul 24 04:55:43 PM PDT 24
Peak memory 159764 kb
Host smart-8466db03-6afd-42c1-bbc9-514a1574b031
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3683444271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3683444271
Directory /workspace/25.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1104286661
Short name T30
Test name
Test status
Simulation time 336601290000 ps
CPU time 896.34 seconds
Started Jul 24 04:21:58 PM PDT 24
Finished Jul 24 04:59:18 PM PDT 24
Peak memory 160884 kb
Host smart-e0be5ee0-bfe5-4099-ae32-cb4501acb30f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1104286661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.1104286661
Directory /workspace/26.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2352066976
Short name T172
Test name
Test status
Simulation time 336876490000 ps
CPU time 856.05 seconds
Started Jul 24 04:21:18 PM PDT 24
Finished Jul 24 04:57:03 PM PDT 24
Peak memory 160764 kb
Host smart-31030413-fc68-465f-902e-34bf2d0d0242
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2352066976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.2352066976
Directory /workspace/27.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3985865669
Short name T167
Test name
Test status
Simulation time 336739990000 ps
CPU time 739.56 seconds
Started Jul 24 04:25:39 PM PDT 24
Finished Jul 24 04:56:36 PM PDT 24
Peak memory 159460 kb
Host smart-1e7f0789-21bf-48d3-8d58-0b0460e25d86
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3985865669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3985865669
Directory /workspace/28.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2398903789
Short name T170
Test name
Test status
Simulation time 337007910000 ps
CPU time 948.44 seconds
Started Jul 24 04:20:36 PM PDT 24
Finished Jul 24 05:00:21 PM PDT 24
Peak memory 160520 kb
Host smart-1f6272bc-895f-4363-aaa3-9ea8ceaec438
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2398903789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2398903789
Directory /workspace/29.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.1534795409
Short name T161
Test name
Test status
Simulation time 336872890000 ps
CPU time 900.23 seconds
Started Jul 24 04:21:44 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 160652 kb
Host smart-dac0656b-a8ef-4a89-ab76-75cde3cec8c3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1534795409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.1534795409
Directory /workspace/3.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.2728975776
Short name T24
Test name
Test status
Simulation time 336511830000 ps
CPU time 589.57 seconds
Started Jul 24 04:25:52 PM PDT 24
Finished Jul 24 04:50:15 PM PDT 24
Peak memory 160604 kb
Host smart-64748cb1-5360-4e7e-8816-1bf495dde1f5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2728975776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.2728975776
Directory /workspace/30.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.1813662428
Short name T178
Test name
Test status
Simulation time 336643150000 ps
CPU time 620.69 seconds
Started Jul 24 04:25:28 PM PDT 24
Finished Jul 24 04:50:50 PM PDT 24
Peak memory 160324 kb
Host smart-51869b73-8dfa-4935-809c-c326d9cdd6ba
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1813662428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.1813662428
Directory /workspace/31.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1864242110
Short name T169
Test name
Test status
Simulation time 336389530000 ps
CPU time 642.82 seconds
Started Jul 24 04:22:19 PM PDT 24
Finished Jul 24 04:48:29 PM PDT 24
Peak memory 160436 kb
Host smart-ceedbf20-0c85-4e47-a6c1-be45de360e34
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1864242110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.1864242110
Directory /workspace/32.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.3104055015
Short name T165
Test name
Test status
Simulation time 336358390000 ps
CPU time 730.04 seconds
Started Jul 24 04:25:49 PM PDT 24
Finished Jul 24 04:56:38 PM PDT 24
Peak memory 160424 kb
Host smart-cd9203e3-d541-46a7-bf88-65806fa57128
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3104055015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.3104055015
Directory /workspace/33.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.697797845
Short name T163
Test name
Test status
Simulation time 336374170000 ps
CPU time 877.65 seconds
Started Jul 24 04:21:09 PM PDT 24
Finished Jul 24 04:57:17 PM PDT 24
Peak memory 160656 kb
Host smart-41af24a6-ebda-4f37-94a3-171bc1b71686
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=697797845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.697797845
Directory /workspace/34.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.333559940
Short name T173
Test name
Test status
Simulation time 337083110000 ps
CPU time 738.46 seconds
Started Jul 24 04:25:48 PM PDT 24
Finished Jul 24 04:57:01 PM PDT 24
Peak memory 160412 kb
Host smart-6c90be42-6e7e-4b77-8c0d-fefa4f736923
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=333559940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.333559940
Directory /workspace/35.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.1583089009
Short name T179
Test name
Test status
Simulation time 336350670000 ps
CPU time 656.38 seconds
Started Jul 24 04:31:29 PM PDT 24
Finished Jul 24 04:58:18 PM PDT 24
Peak memory 160752 kb
Host smart-bebdd104-494c-43c8-95d4-490ca57cdd77
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1583089009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.1583089009
Directory /workspace/36.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1295165019
Short name T197
Test name
Test status
Simulation time 336437210000 ps
CPU time 820.05 seconds
Started Jul 24 04:31:31 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 160896 kb
Host smart-056d989b-464a-4988-9737-b61f40de36b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1295165019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1295165019
Directory /workspace/37.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3361113507
Short name T189
Test name
Test status
Simulation time 336902370000 ps
CPU time 656.38 seconds
Started Jul 24 04:31:29 PM PDT 24
Finished Jul 24 04:58:32 PM PDT 24
Peak memory 160644 kb
Host smart-2e311880-59a1-4b3b-9727-0187d8877605
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3361113507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3361113507
Directory /workspace/38.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2175331061
Short name T162
Test name
Test status
Simulation time 336762590000 ps
CPU time 721.47 seconds
Started Jul 24 04:31:30 PM PDT 24
Finished Jul 24 05:00:53 PM PDT 24
Peak memory 160604 kb
Host smart-24da5c1a-acb6-412e-b217-404c08ace2a9
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2175331061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2175331061
Directory /workspace/39.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.83677967
Short name T175
Test name
Test status
Simulation time 336814270000 ps
CPU time 841.15 seconds
Started Jul 24 04:21:52 PM PDT 24
Finished Jul 24 04:56:33 PM PDT 24
Peak memory 160696 kb
Host smart-0caaef2d-11e1-4026-9d8a-6d72e6fea859
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=83677967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.83677967
Directory /workspace/4.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1775527566
Short name T176
Test name
Test status
Simulation time 336612850000 ps
CPU time 639.58 seconds
Started Jul 24 04:31:30 PM PDT 24
Finished Jul 24 04:57:48 PM PDT 24
Peak memory 160672 kb
Host smart-6876b1f6-3277-4304-b713-722ec5d84d13
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1775527566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1775527566
Directory /workspace/40.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.1535737873
Short name T194
Test name
Test status
Simulation time 336790470000 ps
CPU time 708.52 seconds
Started Jul 24 04:31:28 PM PDT 24
Finished Jul 24 05:00:55 PM PDT 24
Peak memory 160544 kb
Host smart-cdf435e2-dd87-4a17-803d-fa29c2e962e3
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1535737873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.1535737873
Directory /workspace/41.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3202139757
Short name T23
Test name
Test status
Simulation time 336599110000 ps
CPU time 765.09 seconds
Started Jul 24 04:31:29 PM PDT 24
Finished Jul 24 05:03:45 PM PDT 24
Peak memory 160652 kb
Host smart-09e89e44-adc3-4ba6-af33-e112de55ce55
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3202139757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.3202139757
Directory /workspace/42.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.3364168806
Short name T199
Test name
Test status
Simulation time 336896370000 ps
CPU time 658.89 seconds
Started Jul 24 04:31:29 PM PDT 24
Finished Jul 24 04:58:23 PM PDT 24
Peak memory 160644 kb
Host smart-91fab35f-14a2-452b-a117-d6ce7ab8ec8f
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3364168806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.3364168806
Directory /workspace/43.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3393761236
Short name T28
Test name
Test status
Simulation time 336334790000 ps
CPU time 693.03 seconds
Started Jul 24 04:31:29 PM PDT 24
Finished Jul 24 04:59:50 PM PDT 24
Peak memory 160624 kb
Host smart-3b3a8bb2-2556-4305-8411-b6a93a5cee42
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3393761236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3393761236
Directory /workspace/44.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.1225458303
Short name T187
Test name
Test status
Simulation time 336355990000 ps
CPU time 725.72 seconds
Started Jul 24 04:31:36 PM PDT 24
Finished Jul 24 05:01:32 PM PDT 24
Peak memory 160712 kb
Host smart-690ab0df-cdd0-45bf-828e-3f4e04ae42d2
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1225458303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.1225458303
Directory /workspace/45.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.1948180303
Short name T200
Test name
Test status
Simulation time 336485890000 ps
CPU time 776.55 seconds
Started Jul 24 04:31:38 PM PDT 24
Finished Jul 24 05:03:19 PM PDT 24
Peak memory 160620 kb
Host smart-6b715588-f919-4ad3-9d36-31091654ea18
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1948180303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.1948180303
Directory /workspace/46.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2347635926
Short name T184
Test name
Test status
Simulation time 336550370000 ps
CPU time 762.46 seconds
Started Jul 24 04:31:36 PM PDT 24
Finished Jul 24 05:02:49 PM PDT 24
Peak memory 160708 kb
Host smart-773a70f4-7733-4fad-af40-78ad59a49b63
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2347635926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2347635926
Directory /workspace/47.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.307723950
Short name T21
Test name
Test status
Simulation time 336353150000 ps
CPU time 718.36 seconds
Started Jul 24 04:31:38 PM PDT 24
Finished Jul 24 05:01:02 PM PDT 24
Peak memory 160644 kb
Host smart-0024f2a6-f8f1-4de2-bc2c-d8fd72ab1af5
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=307723950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.307723950
Directory /workspace/48.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2571490732
Short name T168
Test name
Test status
Simulation time 336960590000 ps
CPU time 757.46 seconds
Started Jul 24 04:31:38 PM PDT 24
Finished Jul 24 05:02:47 PM PDT 24
Peak memory 160620 kb
Host smart-49693242-c07c-4937-abc1-4ede64d270b4
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2571490732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2571490732
Directory /workspace/49.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.3702414064
Short name T195
Test name
Test status
Simulation time 336373870000 ps
CPU time 802.32 seconds
Started Jul 24 04:26:00 PM PDT 24
Finished Jul 24 04:59:14 PM PDT 24
Peak memory 160572 kb
Host smart-e95061fb-9505-410d-9c1f-1b1a10a5964c
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3702414064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.3702414064
Directory /workspace/5.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1350563372
Short name T188
Test name
Test status
Simulation time 336322010000 ps
CPU time 825.85 seconds
Started Jul 24 04:21:52 PM PDT 24
Finished Jul 24 04:56:14 PM PDT 24
Peak memory 160672 kb
Host smart-7a34d3e3-fd1a-48f2-a003-ec53aca8d735
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1350563372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1350563372
Directory /workspace/6.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2497606969
Short name T29
Test name
Test status
Simulation time 336479290000 ps
CPU time 725.26 seconds
Started Jul 24 04:25:14 PM PDT 24
Finished Jul 24 04:55:31 PM PDT 24
Peak memory 160560 kb
Host smart-32cb95cd-8868-4703-9851-eff37069e934
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2497606969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.2497606969
Directory /workspace/7.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1390282443
Short name T185
Test name
Test status
Simulation time 336711370000 ps
CPU time 820.84 seconds
Started Jul 24 04:22:17 PM PDT 24
Finished Jul 24 04:56:26 PM PDT 24
Peak memory 160676 kb
Host smart-55ab6050-9f36-42a4-8da5-df4ae4da7891
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1390282443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1390282443
Directory /workspace/8.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2084756949
Short name T22
Test name
Test status
Simulation time 336539430000 ps
CPU time 667.57 seconds
Started Jul 24 04:25:25 PM PDT 24
Finished Jul 24 04:52:51 PM PDT 24
Peak memory 159632 kb
Host smart-8bcab7e9-6605-4d2a-b07f-66ffb710dd14
User root
Command /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2084756949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2084756949
Directory /workspace/9.prim_lfsr_gal_test/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.2590864126
Short name T160
Test name
Test status
Simulation time 1366590000 ps
CPU time 4.09 seconds
Started Jul 24 04:21:48 PM PDT 24
Finished Jul 24 04:21:57 PM PDT 24
Peak memory 164824 kb
Host smart-2e32f852-09f6-4537-939f-5b2dee0611c8
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590864126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2590864126
Directory /workspace/0.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.250427961
Short name T118
Test name
Test status
Simulation time 1532530000 ps
CPU time 3.08 seconds
Started Jul 24 04:25:44 PM PDT 24
Finished Jul 24 04:25:51 PM PDT 24
Peak memory 164408 kb
Host smart-68bf0318-b11c-41ad-a898-f3ecb2b76ced
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=250427961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.250427961
Directory /workspace/1.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.368150804
Short name T159
Test name
Test status
Simulation time 1364250000 ps
CPU time 4.04 seconds
Started Jul 24 04:21:39 PM PDT 24
Finished Jul 24 04:21:48 PM PDT 24
Peak memory 164768 kb
Host smart-c9783cdc-1bc6-443c-9ba0-41966e2f80c5
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=368150804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.368150804
Directory /workspace/10.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.799317312
Short name T125
Test name
Test status
Simulation time 1370350000 ps
CPU time 3.61 seconds
Started Jul 24 04:20:57 PM PDT 24
Finished Jul 24 04:21:05 PM PDT 24
Peak memory 164808 kb
Host smart-3d475a2b-7262-4708-b964-f0330ee08064
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=799317312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.799317312
Directory /workspace/11.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.1055374058
Short name T156
Test name
Test status
Simulation time 1641510000 ps
CPU time 4.74 seconds
Started Jul 24 04:25:16 PM PDT 24
Finished Jul 24 04:25:26 PM PDT 24
Peak memory 164720 kb
Host smart-59c65843-c42e-4695-91c1-8a4bb48b146d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1055374058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.1055374058
Directory /workspace/12.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3631120390
Short name T147
Test name
Test status
Simulation time 1603330000 ps
CPU time 4.69 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:21:46 PM PDT 24
Peak memory 164820 kb
Host smart-a77f3abe-aada-4e0f-a8bb-4ce260898a53
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3631120390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.3631120390
Directory /workspace/13.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.1755891299
Short name T158
Test name
Test status
Simulation time 1460350000 ps
CPU time 3.41 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:22:28 PM PDT 24
Peak memory 164780 kb
Host smart-40155b06-d907-4a3b-927b-1d50a585b3f1
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1755891299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.1755891299
Directory /workspace/14.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.2638828417
Short name T152
Test name
Test status
Simulation time 1380150000 ps
CPU time 3.45 seconds
Started Jul 24 04:25:00 PM PDT 24
Finished Jul 24 04:25:08 PM PDT 24
Peak memory 163816 kb
Host smart-c438b647-b73e-4338-a3ca-cd37d9a92630
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2638828417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.2638828417
Directory /workspace/15.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1602738165
Short name T138
Test name
Test status
Simulation time 1484730000 ps
CPU time 5.2 seconds
Started Jul 24 04:20:51 PM PDT 24
Finished Jul 24 04:21:02 PM PDT 24
Peak memory 164600 kb
Host smart-8c50a349-cd34-4226-8a50-20cbcfb4c2cc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1602738165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1602738165
Directory /workspace/16.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3772115131
Short name T112
Test name
Test status
Simulation time 1446330000 ps
CPU time 3.99 seconds
Started Jul 24 04:21:35 PM PDT 24
Finished Jul 24 04:21:44 PM PDT 24
Peak memory 164780 kb
Host smart-c0fb48e4-6ae6-455c-8a5c-d60305cb69d6
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3772115131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3772115131
Directory /workspace/17.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.827580494
Short name T123
Test name
Test status
Simulation time 1368270000 ps
CPU time 3.18 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:28 PM PDT 24
Peak memory 164472 kb
Host smart-10bd1b03-cb7e-4880-8928-ced834df753c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=827580494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.827580494
Directory /workspace/18.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1212663930
Short name T129
Test name
Test status
Simulation time 1401650000 ps
CPU time 4.14 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:31 PM PDT 24
Peak memory 164756 kb
Host smart-b482c104-8f67-47e9-bc3e-abdecf5b1ac4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1212663930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.1212663930
Directory /workspace/19.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.2821064213
Short name T133
Test name
Test status
Simulation time 1555050000 ps
CPU time 4.26 seconds
Started Jul 24 04:22:27 PM PDT 24
Finished Jul 24 04:22:37 PM PDT 24
Peak memory 164720 kb
Host smart-e2fd3663-ed8b-4dd6-ab50-6dca6e020d7c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2821064213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.2821064213
Directory /workspace/2.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.2871916146
Short name T124
Test name
Test status
Simulation time 1317530000 ps
CPU time 3.46 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:26:05 PM PDT 24
Peak memory 164720 kb
Host smart-395da13a-21fb-4265-821e-1a5b6306e55b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2871916146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.2871916146
Directory /workspace/20.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.1610165476
Short name T128
Test name
Test status
Simulation time 1500130000 ps
CPU time 4.7 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:20 PM PDT 24
Peak memory 164428 kb
Host smart-88782302-773b-4e77-abc2-e4a7bb9ed13d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1610165476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.1610165476
Directory /workspace/21.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.4090955163
Short name T119
Test name
Test status
Simulation time 1417050000 ps
CPU time 3.91 seconds
Started Jul 24 04:21:14 PM PDT 24
Finished Jul 24 04:21:23 PM PDT 24
Peak memory 165028 kb
Host smart-10b63dec-c3f9-4f38-a9c4-c9b7a5e5f4f4
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4090955163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.4090955163
Directory /workspace/22.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1781947236
Short name T120
Test name
Test status
Simulation time 1519730000 ps
CPU time 4.5 seconds
Started Jul 24 04:25:22 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 164764 kb
Host smart-4124bef0-1696-428f-bd3c-33f57a1a90ab
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781947236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1781947236
Directory /workspace/23.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1856505515
Short name T157
Test name
Test status
Simulation time 1496570000 ps
CPU time 4 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:31 PM PDT 24
Peak memory 164764 kb
Host smart-e05fd334-e229-4cb5-99bd-5d9cd2a87958
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1856505515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1856505515
Directory /workspace/24.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.3374281384
Short name T121
Test name
Test status
Simulation time 1454010000 ps
CPU time 3.69 seconds
Started Jul 24 04:22:25 PM PDT 24
Finished Jul 24 04:22:34 PM PDT 24
Peak memory 164808 kb
Host smart-d1b27152-8e5b-45e5-83f8-01b45b36813a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3374281384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.3374281384
Directory /workspace/25.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3282893431
Short name T143
Test name
Test status
Simulation time 1350850000 ps
CPU time 3.78 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:25:32 PM PDT 24
Peak memory 164528 kb
Host smart-0272429a-f7a2-4301-8a8f-58fe1d3642e0
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3282893431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3282893431
Directory /workspace/26.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.719671362
Short name T113
Test name
Test status
Simulation time 1436170000 ps
CPU time 3.75 seconds
Started Jul 24 04:21:49 PM PDT 24
Finished Jul 24 04:21:57 PM PDT 24
Peak memory 164880 kb
Host smart-6695de9e-4ba2-4712-a026-dc00e0f0fd35
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=719671362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.719671362
Directory /workspace/27.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.908435536
Short name T141
Test name
Test status
Simulation time 1414190000 ps
CPU time 4.07 seconds
Started Jul 24 04:23:20 PM PDT 24
Finished Jul 24 04:23:29 PM PDT 24
Peak memory 164776 kb
Host smart-0e6184ab-a473-44ab-b0c9-0306ddfc9617
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=908435536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.908435536
Directory /workspace/28.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2914145971
Short name T140
Test name
Test status
Simulation time 1552290000 ps
CPU time 5.29 seconds
Started Jul 24 04:20:51 PM PDT 24
Finished Jul 24 04:21:03 PM PDT 24
Peak memory 164600 kb
Host smart-14855476-ad64-4318-82c2-d359e9841f74
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2914145971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2914145971
Directory /workspace/29.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.4051493078
Short name T150
Test name
Test status
Simulation time 1489670000 ps
CPU time 4.58 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:52 PM PDT 24
Peak memory 164640 kb
Host smart-f1db8561-80fc-4c31-aaef-928f6d7947f9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051493078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.4051493078
Directory /workspace/3.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.2616076965
Short name T136
Test name
Test status
Simulation time 1363790000 ps
CPU time 3.53 seconds
Started Jul 24 04:23:06 PM PDT 24
Finished Jul 24 04:23:14 PM PDT 24
Peak memory 164784 kb
Host smart-85f26936-3b05-4d90-b3a2-361b6935fe6b
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2616076965 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.2616076965
Directory /workspace/30.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3467015541
Short name T148
Test name
Test status
Simulation time 1607950000 ps
CPU time 4.01 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:16 PM PDT 24
Peak memory 164032 kb
Host smart-545c7b8e-37b2-40d5-97ed-3077af4cb160
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467015541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3467015541
Directory /workspace/31.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1856555221
Short name T116
Test name
Test status
Simulation time 1538990000 ps
CPU time 4.25 seconds
Started Jul 24 04:22:57 PM PDT 24
Finished Jul 24 04:23:07 PM PDT 24
Peak memory 164788 kb
Host smart-0e4d10b9-f772-420e-ba70-7859ea419874
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1856555221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.1856555221
Directory /workspace/32.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3071632005
Short name T132
Test name
Test status
Simulation time 1458910000 ps
CPU time 4.47 seconds
Started Jul 24 04:25:58 PM PDT 24
Finished Jul 24 04:26:07 PM PDT 24
Peak memory 164672 kb
Host smart-5a6ca022-d30c-46ad-99b1-2d67aa4aa9fe
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3071632005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3071632005
Directory /workspace/33.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3355675822
Short name T126
Test name
Test status
Simulation time 1593990000 ps
CPU time 3.56 seconds
Started Jul 24 04:21:05 PM PDT 24
Finished Jul 24 04:21:13 PM PDT 24
Peak memory 164752 kb
Host smart-18f26905-be81-4379-8480-f480f9d4a695
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3355675822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3355675822
Directory /workspace/34.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.2181530092
Short name T111
Test name
Test status
Simulation time 1622330000 ps
CPU time 3.58 seconds
Started Jul 24 04:25:57 PM PDT 24
Finished Jul 24 04:26:05 PM PDT 24
Peak memory 164668 kb
Host smart-92cd009e-2ed1-4cb7-8bed-08da715eb131
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2181530092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.2181530092
Directory /workspace/35.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3006031809
Short name T144
Test name
Test status
Simulation time 1012150000 ps
CPU time 2.84 seconds
Started Jul 24 04:25:37 PM PDT 24
Finished Jul 24 04:25:44 PM PDT 24
Peak memory 164700 kb
Host smart-c2cd7346-69ee-4922-8fe2-5d443112bc6d
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3006031809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3006031809
Directory /workspace/36.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.1728514013
Short name T146
Test name
Test status
Simulation time 1576150000 ps
CPU time 3.77 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 163504 kb
Host smart-cfd74ae9-83bd-46d8-a309-48312f7223dd
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1728514013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.1728514013
Directory /workspace/37.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.617800099
Short name T142
Test name
Test status
Simulation time 1318010000 ps
CPU time 3.38 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:26:01 PM PDT 24
Peak memory 164672 kb
Host smart-3a5fabd9-4252-40ea-b9ed-6a3b7b28825e
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=617800099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.617800099
Directory /workspace/38.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3967780593
Short name T139
Test name
Test status
Simulation time 1178570000 ps
CPU time 3.29 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:53 PM PDT 24
Peak memory 163360 kb
Host smart-6bf110dc-24f2-4ded-820d-cc5047edfbc9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967780593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.3967780593
Directory /workspace/39.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.2100187462
Short name T145
Test name
Test status
Simulation time 1538650000 ps
CPU time 4.61 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:52 PM PDT 24
Peak memory 164644 kb
Host smart-ace712c1-e036-4d05-929c-7a4f7a7a9bd3
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2100187462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.2100187462
Directory /workspace/4.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1168499387
Short name T149
Test name
Test status
Simulation time 1385170000 ps
CPU time 2.99 seconds
Started Jul 24 04:31:24 PM PDT 24
Finished Jul 24 04:31:31 PM PDT 24
Peak memory 164708 kb
Host smart-b9a5c940-60f8-4419-80b9-9c96f7260a05
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1168499387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1168499387
Directory /workspace/40.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.2984093781
Short name T135
Test name
Test status
Simulation time 1349730000 ps
CPU time 3.79 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:31:34 PM PDT 24
Peak memory 164804 kb
Host smart-b373b888-1559-4705-8605-cb639c7a055c
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2984093781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.2984093781
Directory /workspace/41.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3429099379
Short name T154
Test name
Test status
Simulation time 1552070000 ps
CPU time 4.3 seconds
Started Jul 24 04:31:23 PM PDT 24
Finished Jul 24 04:31:33 PM PDT 24
Peak memory 164640 kb
Host smart-a2758aea-0dd6-4041-aee4-e0dfc0285806
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3429099379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3429099379
Directory /workspace/42.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1540088485
Short name T122
Test name
Test status
Simulation time 1296730000 ps
CPU time 2.97 seconds
Started Jul 24 04:31:24 PM PDT 24
Finished Jul 24 04:31:31 PM PDT 24
Peak memory 164816 kb
Host smart-a0c58cf4-f81e-4f6f-a16c-b30bc00578ce
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1540088485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1540088485
Directory /workspace/43.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2719203197
Short name T155
Test name
Test status
Simulation time 1380510000 ps
CPU time 3.11 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:31:32 PM PDT 24
Peak memory 164640 kb
Host smart-ef1cf48d-f1ee-469c-b32e-c41ff6aef098
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2719203197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2719203197
Directory /workspace/44.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3176978650
Short name T131
Test name
Test status
Simulation time 1609170000 ps
CPU time 5.39 seconds
Started Jul 24 04:31:25 PM PDT 24
Finished Jul 24 04:31:36 PM PDT 24
Peak memory 164696 kb
Host smart-eaeaf4b9-7428-4b60-a89a-12b391cc28f2
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3176978650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3176978650
Directory /workspace/45.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.1223455909
Short name T115
Test name
Test status
Simulation time 1338070000 ps
CPU time 3.49 seconds
Started Jul 24 04:31:23 PM PDT 24
Finished Jul 24 04:31:31 PM PDT 24
Peak memory 164836 kb
Host smart-34e14718-65e5-4ebc-8e7f-01dcf63dfbf9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1223455909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.1223455909
Directory /workspace/46.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.2628577081
Short name T130
Test name
Test status
Simulation time 1157990000 ps
CPU time 3.27 seconds
Started Jul 24 04:31:30 PM PDT 24
Finished Jul 24 04:31:37 PM PDT 24
Peak memory 164640 kb
Host smart-d1cbd058-6616-47e3-a91b-ae85517c2d95
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2628577081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.2628577081
Directory /workspace/47.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.4272597370
Short name T137
Test name
Test status
Simulation time 1406850000 ps
CPU time 4.06 seconds
Started Jul 24 04:31:30 PM PDT 24
Finished Jul 24 04:31:39 PM PDT 24
Peak memory 164744 kb
Host smart-efd2c690-a2e7-49d3-afa5-c4c30a06f32a
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4272597370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.4272597370
Directory /workspace/48.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.765038531
Short name T134
Test name
Test status
Simulation time 1340590000 ps
CPU time 4.13 seconds
Started Jul 24 04:31:31 PM PDT 24
Finished Jul 24 04:31:40 PM PDT 24
Peak memory 164756 kb
Host smart-2f8588d1-9e07-46e3-b0b9-9bec1f502a38
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=765038531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.765038531
Directory /workspace/49.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2084404476
Short name T151
Test name
Test status
Simulation time 1123310000 ps
CPU time 2.39 seconds
Started Jul 24 04:25:50 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 164680 kb
Host smart-791a235e-f072-4942-8b9d-a72edfadb592
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2084404476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2084404476
Directory /workspace/5.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.3456842921
Short name T117
Test name
Test status
Simulation time 1240850000 ps
CPU time 3.88 seconds
Started Jul 24 04:24:27 PM PDT 24
Finished Jul 24 04:24:36 PM PDT 24
Peak memory 164788 kb
Host smart-f6363555-7ae2-4407-9653-390d7c6104bc
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3456842921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.3456842921
Directory /workspace/6.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.1309295709
Short name T153
Test name
Test status
Simulation time 1328890000 ps
CPU time 3.85 seconds
Started Jul 24 04:25:37 PM PDT 24
Finished Jul 24 04:25:45 PM PDT 24
Peak memory 164624 kb
Host smart-46446812-d717-4828-a347-1fde399a97b9
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1309295709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.1309295709
Directory /workspace/7.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1626511850
Short name T127
Test name
Test status
Simulation time 1521370000 ps
CPU time 3.25 seconds
Started Jul 24 04:25:53 PM PDT 24
Finished Jul 24 04:26:00 PM PDT 24
Peak memory 164520 kb
Host smart-e1a1c9df-eb06-4293-abcb-a25bc896a5db
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1626511850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1626511850
Directory /workspace/8.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2889966730
Short name T114
Test name
Test status
Simulation time 1427990000 ps
CPU time 3.97 seconds
Started Jul 24 04:25:11 PM PDT 24
Finished Jul 24 04:25:20 PM PDT 24
Peak memory 164484 kb
Host smart-eac8a964-4d63-4a37-8aab-4d239fd0decf
User root
Command /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2889966730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2889966730
Directory /workspace/9.prim_lfsr_fib_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1732337770
Short name T31
Test name
Test status
Simulation time 1314170000 ps
CPU time 4.43 seconds
Started Jul 24 04:22:56 PM PDT 24
Finished Jul 24 04:23:06 PM PDT 24
Peak memory 164788 kb
Host smart-210519b9-b809-4936-8237-5af9c7d38073
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1732337770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.1732337770
Directory /workspace/0.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1477611475
Short name T43
Test name
Test status
Simulation time 1384750000 ps
CPU time 4.59 seconds
Started Jul 24 04:25:02 PM PDT 24
Finished Jul 24 04:25:12 PM PDT 24
Peak memory 162988 kb
Host smart-1ebd45dc-c6de-484a-845e-5790964ff520
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1477611475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1477611475
Directory /workspace/1.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2615180470
Short name T50
Test name
Test status
Simulation time 1393230000 ps
CPU time 3.49 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:25:17 PM PDT 24
Peak memory 164476 kb
Host smart-4d1ea78a-48e7-4fd6-93b2-aff9ed939331
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2615180470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2615180470
Directory /workspace/10.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2336556494
Short name T53
Test name
Test status
Simulation time 1234210000 ps
CPU time 3.4 seconds
Started Jul 24 04:25:10 PM PDT 24
Finished Jul 24 04:25:18 PM PDT 24
Peak memory 164556 kb
Host smart-43786405-6831-4add-ab0a-d54adaef9549
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2336556494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2336556494
Directory /workspace/11.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1004532160
Short name T52
Test name
Test status
Simulation time 1380970000 ps
CPU time 3.8 seconds
Started Jul 24 04:24:00 PM PDT 24
Finished Jul 24 04:24:08 PM PDT 24
Peak memory 164812 kb
Host smart-9da2cf02-695b-48e5-8da9-bba0000baade
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1004532160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.1004532160
Directory /workspace/12.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.3923403769
Short name T35
Test name
Test status
Simulation time 1424830000 ps
CPU time 3.44 seconds
Started Jul 24 04:25:46 PM PDT 24
Finished Jul 24 04:25:55 PM PDT 24
Peak memory 163448 kb
Host smart-1265df0c-2c1f-4263-9d47-0e2519563181
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3923403769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.3923403769
Directory /workspace/13.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.1676911263
Short name T49
Test name
Test status
Simulation time 1483590000 ps
CPU time 4.54 seconds
Started Jul 24 04:24:56 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 164688 kb
Host smart-836d432a-f852-4196-9de7-7627ac20f81a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1676911263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.1676911263
Directory /workspace/14.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.4110049399
Short name T61
Test name
Test status
Simulation time 1293870000 ps
CPU time 3.12 seconds
Started Jul 24 04:23:28 PM PDT 24
Finished Jul 24 04:23:35 PM PDT 24
Peak memory 164996 kb
Host smart-5f04c53c-b928-4cca-b9dd-704a7d9a86aa
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4110049399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.4110049399
Directory /workspace/15.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.3133052986
Short name T34
Test name
Test status
Simulation time 1342390000 ps
CPU time 4.31 seconds
Started Jul 24 04:24:57 PM PDT 24
Finished Jul 24 04:25:07 PM PDT 24
Peak memory 164628 kb
Host smart-5b1f25aa-4fe3-4869-a89d-0dd16576e2d8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3133052986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.3133052986
Directory /workspace/16.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.2605206536
Short name T51
Test name
Test status
Simulation time 1559530000 ps
CPU time 3.78 seconds
Started Jul 24 04:25:00 PM PDT 24
Finished Jul 24 04:25:09 PM PDT 24
Peak memory 163360 kb
Host smart-d0cac522-0a96-4fb7-a2dd-c32a30446463
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2605206536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.2605206536
Directory /workspace/17.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.1861029065
Short name T42
Test name
Test status
Simulation time 1590930000 ps
CPU time 4.01 seconds
Started Jul 24 04:25:16 PM PDT 24
Finished Jul 24 04:25:25 PM PDT 24
Peak memory 164660 kb
Host smart-576d9759-79ee-4484-9c25-22854b96b925
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1861029065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.1861029065
Directory /workspace/18.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.2795657086
Short name T13
Test name
Test status
Simulation time 1350190000 ps
CPU time 3.71 seconds
Started Jul 24 04:21:20 PM PDT 24
Finished Jul 24 04:21:28 PM PDT 24
Peak memory 164792 kb
Host smart-fe8d7d44-6c4b-47a0-a833-45adb11c929a
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2795657086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.2795657086
Directory /workspace/2.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2673829739
Short name T2
Test name
Test status
Simulation time 1303730000 ps
CPU time 4.31 seconds
Started Jul 24 04:25:41 PM PDT 24
Finished Jul 24 04:25:51 PM PDT 24
Peak memory 164696 kb
Host smart-f32e1f0e-3616-43ec-8e0e-fda0b6ee8159
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2673829739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2673829739
Directory /workspace/20.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.691623163
Short name T62
Test name
Test status
Simulation time 1320190000 ps
CPU time 3.56 seconds
Started Jul 24 04:25:26 PM PDT 24
Finished Jul 24 04:25:34 PM PDT 24
Peak memory 163192 kb
Host smart-951533eb-184f-4d6b-8639-db2b791a04a9
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=691623163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.691623163
Directory /workspace/21.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.2866847993
Short name T37
Test name
Test status
Simulation time 1537590000 ps
CPU time 3.94 seconds
Started Jul 24 04:25:02 PM PDT 24
Finished Jul 24 04:25:11 PM PDT 24
Peak memory 163676 kb
Host smart-ef4a1e02-c392-480e-8c61-513812bdad51
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2866847993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.2866847993
Directory /workspace/22.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.126085839
Short name T54
Test name
Test status
Simulation time 1459130000 ps
CPU time 3.69 seconds
Started Jul 24 04:22:19 PM PDT 24
Finished Jul 24 04:22:28 PM PDT 24
Peak memory 164812 kb
Host smart-2a723f7f-26ec-4d9d-bce7-1d3904e05321
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=126085839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.126085839
Directory /workspace/23.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.1044910954
Short name T41
Test name
Test status
Simulation time 1481810000 ps
CPU time 3.87 seconds
Started Jul 24 04:23:50 PM PDT 24
Finished Jul 24 04:23:59 PM PDT 24
Peak memory 164812 kb
Host smart-4d445aa6-4617-4436-8f94-13c9b94dc638
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1044910954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.1044910954
Directory /workspace/24.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.538516105
Short name T12
Test name
Test status
Simulation time 1441950000 ps
CPU time 4.86 seconds
Started Jul 24 04:22:27 PM PDT 24
Finished Jul 24 04:22:37 PM PDT 24
Peak memory 165032 kb
Host smart-810ed2fd-bf98-4ed5-8f96-adf5da5ccb16
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=538516105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.538516105
Directory /workspace/25.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3887112159
Short name T44
Test name
Test status
Simulation time 1335310000 ps
CPU time 3.43 seconds
Started Jul 24 04:25:47 PM PDT 24
Finished Jul 24 04:25:54 PM PDT 24
Peak memory 164704 kb
Host smart-d07ed06f-f033-4137-92ee-f348ebef44a7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3887112159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.3887112159
Directory /workspace/26.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3567786847
Short name T9
Test name
Test status
Simulation time 1569350000 ps
CPU time 3.32 seconds
Started Jul 24 04:25:29 PM PDT 24
Finished Jul 24 04:25:37 PM PDT 24
Peak memory 163628 kb
Host smart-649f09af-b101-4875-9fe1-573808127198
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3567786847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3567786847
Directory /workspace/27.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3001938351
Short name T39
Test name
Test status
Simulation time 1471750000 ps
CPU time 4.79 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:25:19 PM PDT 24
Peak memory 163192 kb
Host smart-fff4cace-d7af-4777-9cf8-aaa3eeeccf3f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3001938351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3001938351
Directory /workspace/28.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1811338879
Short name T45
Test name
Test status
Simulation time 1495790000 ps
CPU time 3.91 seconds
Started Jul 24 04:23:01 PM PDT 24
Finished Jul 24 04:23:10 PM PDT 24
Peak memory 164812 kb
Host smart-d4c0ffec-3b46-4f46-9923-3e6c2727ca9b
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1811338879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.1811338879
Directory /workspace/29.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1780973608
Short name T70
Test name
Test status
Simulation time 1423650000 ps
CPU time 4.27 seconds
Started Jul 24 04:22:34 PM PDT 24
Finished Jul 24 04:22:43 PM PDT 24
Peak memory 164796 kb
Host smart-f2d573c6-2b53-4539-a152-8067a4b3d2d3
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1780973608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1780973608
Directory /workspace/3.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.695502459
Short name T68
Test name
Test status
Simulation time 1498810000 ps
CPU time 3.3 seconds
Started Jul 24 04:23:10 PM PDT 24
Finished Jul 24 04:23:18 PM PDT 24
Peak memory 164776 kb
Host smart-63e49bba-acf5-44ad-accc-8597ac8159bb
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=695502459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.695502459
Directory /workspace/30.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.2101492424
Short name T59
Test name
Test status
Simulation time 1451470000 ps
CPU time 4.22 seconds
Started Jul 24 04:22:20 PM PDT 24
Finished Jul 24 04:22:29 PM PDT 24
Peak memory 164784 kb
Host smart-2f98256d-4e3b-490f-b352-7f0a911eadad
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2101492424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.2101492424
Directory /workspace/31.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2105035974
Short name T57
Test name
Test status
Simulation time 1379430000 ps
CPU time 3.51 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:15 PM PDT 24
Peak memory 164220 kb
Host smart-185084d9-e944-4a84-96c3-4d60651b3055
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2105035974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.2105035974
Directory /workspace/32.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3818033697
Short name T38
Test name
Test status
Simulation time 1525270000 ps
CPU time 3.88 seconds
Started Jul 24 04:25:06 PM PDT 24
Finished Jul 24 04:25:15 PM PDT 24
Peak memory 163920 kb
Host smart-a071e639-3c93-44ae-b4c7-68198bef3b2d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3818033697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3818033697
Directory /workspace/33.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.356402063
Short name T66
Test name
Test status
Simulation time 1584910000 ps
CPU time 4.64 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:22:15 PM PDT 24
Peak memory 164792 kb
Host smart-6c23d66b-8d7e-469f-900f-00b08a93e193
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=356402063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.356402063
Directory /workspace/34.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.2347818793
Short name T64
Test name
Test status
Simulation time 1508850000 ps
CPU time 3.55 seconds
Started Jul 24 04:20:45 PM PDT 24
Finished Jul 24 04:20:53 PM PDT 24
Peak memory 164724 kb
Host smart-bbfd4f36-f180-46bc-ad80-2d0daf84d4d6
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2347818793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.2347818793
Directory /workspace/35.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1328978387
Short name T58
Test name
Test status
Simulation time 1385550000 ps
CPU time 3.2 seconds
Started Jul 24 04:25:21 PM PDT 24
Finished Jul 24 04:25:28 PM PDT 24
Peak memory 164468 kb
Host smart-b5642129-0258-4233-86fb-d8d477fdd8e7
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1328978387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1328978387
Directory /workspace/36.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.1944890957
Short name T47
Test name
Test status
Simulation time 1527990000 ps
CPU time 5.05 seconds
Started Jul 24 04:22:35 PM PDT 24
Finished Jul 24 04:22:46 PM PDT 24
Peak memory 164752 kb
Host smart-49b6b86f-c4d7-4f30-8752-c7acd898b62f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1944890957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.1944890957
Directory /workspace/37.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.898316806
Short name T36
Test name
Test status
Simulation time 1428270000 ps
CPU time 3.49 seconds
Started Jul 24 04:21:12 PM PDT 24
Finished Jul 24 04:21:20 PM PDT 24
Peak memory 164880 kb
Host smart-717fb8b1-fec4-4059-862a-cc426d9e52bc
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=898316806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.898316806
Directory /workspace/38.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.2262199997
Short name T33
Test name
Test status
Simulation time 1553410000 ps
CPU time 4.79 seconds
Started Jul 24 04:21:43 PM PDT 24
Finished Jul 24 04:21:53 PM PDT 24
Peak memory 164784 kb
Host smart-2b15186f-45c4-4986-910e-f903eff044b8
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262199997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.2262199997
Directory /workspace/39.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.2465152155
Short name T48
Test name
Test status
Simulation time 1469650000 ps
CPU time 3.77 seconds
Started Jul 24 04:25:22 PM PDT 24
Finished Jul 24 04:25:31 PM PDT 24
Peak memory 163596 kb
Host smart-5639717d-bba5-4793-86de-f842079464af
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2465152155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.2465152155
Directory /workspace/4.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.4164520077
Short name T60
Test name
Test status
Simulation time 1354690000 ps
CPU time 2.78 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:25:30 PM PDT 24
Peak memory 163432 kb
Host smart-71380363-1247-45ed-ad24-4d0729d890db
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4164520077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.4164520077
Directory /workspace/40.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3711825856
Short name T4
Test name
Test status
Simulation time 1500310000 ps
CPU time 4.16 seconds
Started Jul 24 04:21:03 PM PDT 24
Finished Jul 24 04:21:13 PM PDT 24
Peak memory 164752 kb
Host smart-7d4bbedd-ecec-49ce-8ba3-60a033e49bf5
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3711825856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3711825856
Directory /workspace/41.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.592280269
Short name T63
Test name
Test status
Simulation time 1499990000 ps
CPU time 3.26 seconds
Started Jul 24 04:25:38 PM PDT 24
Finished Jul 24 04:25:46 PM PDT 24
Peak memory 163584 kb
Host smart-c803bddd-28c9-4682-997d-a0fc23262347
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=592280269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.592280269
Directory /workspace/42.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.872384018
Short name T32
Test name
Test status
Simulation time 1517290000 ps
CPU time 4.7 seconds
Started Jul 24 04:22:03 PM PDT 24
Finished Jul 24 04:22:14 PM PDT 24
Peak memory 164788 kb
Host smart-29d8a639-0b88-4a50-b719-2146d5ba3834
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=872384018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.872384018
Directory /workspace/43.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3203490380
Short name T69
Test name
Test status
Simulation time 1434850000 ps
CPU time 3.85 seconds
Started Jul 24 04:21:55 PM PDT 24
Finished Jul 24 04:22:03 PM PDT 24
Peak memory 164832 kb
Host smart-afb6f699-bd88-4692-b51a-5320788745b2
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3203490380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3203490380
Directory /workspace/44.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.2439605501
Short name T40
Test name
Test status
Simulation time 1556410000 ps
CPU time 4.31 seconds
Started Jul 24 04:21:03 PM PDT 24
Finished Jul 24 04:21:12 PM PDT 24
Peak memory 164752 kb
Host smart-0516a009-c56b-4ba4-a2a5-5cf0317ca089
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2439605501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.2439605501
Directory /workspace/45.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2359415522
Short name T3
Test name
Test status
Simulation time 1300110000 ps
CPU time 3.97 seconds
Started Jul 24 04:22:03 PM PDT 24
Finished Jul 24 04:22:12 PM PDT 24
Peak memory 164820 kb
Host smart-7e821282-e8ad-4538-92a3-26cd0f0f087d
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2359415522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2359415522
Directory /workspace/46.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.184443579
Short name T46
Test name
Test status
Simulation time 1557870000 ps
CPU time 3.18 seconds
Started Jul 24 04:25:20 PM PDT 24
Finished Jul 24 04:25:28 PM PDT 24
Peak memory 163172 kb
Host smart-7c115951-ef92-46a4-9dc7-99cbaf2d996f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=184443579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.184443579
Directory /workspace/47.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1643721047
Short name T1
Test name
Test status
Simulation time 1567850000 ps
CPU time 5.07 seconds
Started Jul 24 04:22:04 PM PDT 24
Finished Jul 24 04:22:16 PM PDT 24
Peak memory 164640 kb
Host smart-fbf2fdc3-33b6-426a-81aa-0205dc98ed1f
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1643721047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.1643721047
Directory /workspace/48.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2703045438
Short name T67
Test name
Test status
Simulation time 1529150000 ps
CPU time 5.08 seconds
Started Jul 24 04:22:44 PM PDT 24
Finished Jul 24 04:22:56 PM PDT 24
Peak memory 164784 kb
Host smart-df8fc258-2383-4517-a9e7-e482007764c4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703045438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2703045438
Directory /workspace/49.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2864689373
Short name T10
Test name
Test status
Simulation time 1293950000 ps
CPU time 3.97 seconds
Started Jul 24 04:25:02 PM PDT 24
Finished Jul 24 04:25:11 PM PDT 24
Peak memory 164288 kb
Host smart-43bb7d7a-9143-4aaa-90e4-6793a38d711c
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2864689373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.2864689373
Directory /workspace/5.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.823699962
Short name T8
Test name
Test status
Simulation time 1310910000 ps
CPU time 3.87 seconds
Started Jul 24 04:25:45 PM PDT 24
Finished Jul 24 04:25:54 PM PDT 24
Peak memory 163536 kb
Host smart-7f475c81-2caa-48ba-90b2-abf33d05a580
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=823699962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.823699962
Directory /workspace/6.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.442292744
Short name T55
Test name
Test status
Simulation time 1511490000 ps
CPU time 3.64 seconds
Started Jul 24 04:25:23 PM PDT 24
Finished Jul 24 04:25:31 PM PDT 24
Peak memory 164440 kb
Host smart-e86064f0-67c8-43bb-98a0-c859a25d0d26
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=442292744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.442292744
Directory /workspace/7.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3297098401
Short name T56
Test name
Test status
Simulation time 1148870000 ps
CPU time 2.94 seconds
Started Jul 24 04:25:22 PM PDT 24
Finished Jul 24 04:25:29 PM PDT 24
Peak memory 164636 kb
Host smart-1dd86d96-eabd-4e85-87b1-6f677c5de4e4
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3297098401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.3297098401
Directory /workspace/8.prim_lfsr_gal_smoke/latest

Test location /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.2228770989
Short name T65
Test name
Test status
Simulation time 1366110000 ps
CPU time 3.66 seconds
Started Jul 24 04:25:09 PM PDT 24
Finished Jul 24 04:25:17 PM PDT 24
Peak memory 164484 kb
Host smart-6aea4091-f8d0-49e5-a8b3-a46253823e41
User root
Command /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2228770989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.2228770989
Directory /workspace/9.prim_lfsr_gal_smoke/latest
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