Unified Coverage Report :: Module :: prim_lfsr

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.31	100.00	96.55	100.00		100.00	95.00

Source File(s) :
/workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_lfsr_tb.gen_duts[8].i_prim_lfsr	98.31	100.00	96.55	100.00		100.00	95.00

---

Module Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.31	100.00	96.55	100.00		100.00	95.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.31	100.00	96.55	100.00		100.00	95.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_lfsr_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_lfsr

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
ALWAYS	487	3	3	100.00
ROUTINE	510	10	10	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
ALWAYS	618	5	5	100.00

WARNING: The source file '/workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' or '../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
296	1	1
299	1	1
345	1	1
465	1	1
472	8	8
487	1	1
488	1	1
490	1	1
510	1	1
513	1	1
514	1	1
515	1	1
517	1	1
518	1	1
519	2	2
			MISSING_ELSE
520	1	1
523		unreachable
524		unreachable
525		unreachable
527		unreachable
528		unreachable
529		unreachable
530		unreachable
533		unreachable
536	1	1
610	1	1
615	1	1
618	1	1
619	1	1
620	1	1
622	1	1
623	1	1

---

Cond Coverage for Module : prim_lfsr

	Total	Covered	Percent
Conditions	29	28	96.55
Logical	29	28	96.55
Non-Logical	0	0
Event	0	0

 LINE       345
 EXPRESSION (seed_en_i ? seed_i : ((lfsr_en_i && lockup) ? DefaultSeedLocal : (lfsr_en_i ? next_lfsr_state : lfsr_q)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       345
 SUB-EXPRESSION ((lfsr_en_i && lockup) ? DefaultSeedLocal : (lfsr_en_i ? next_lfsr_state : lfsr_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       345
 SUB-EXPRESSION (lfsr_en_i && lockup)
                 ----1----    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       345
 SUB-EXPRESSION (lfsr_en_i ? next_lfsr_state : lfsr_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       514
 EXPRESSION (next_state == 8'b0)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 EXPRESSION 
 Number  Term
      1  (lfsr_en_i && lockup) ? '0 : ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)) ? '0 : (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i && lockup)
                 ----1----    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)) ? '0 : (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q))
                 --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val))
                 ----1----    -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)
                -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       615
 EXPRESSION (gen_max_len_sva.perturbed_q | ((|entropy_i)) | seed_en_i)
             -------------1-------------   -------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	56	56	100.00
Total Bits 0->1	28	28	100.00
Total Bits 1->0	28	28	100.00

Ports	7	7	100.00
Port Bits	56	56	100.00
Port Bits 0->1	28	28	100.00
Port Bits 1->0	28	28	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
state_o[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

Branch Coverage for Module : prim_lfsr

	Line No.	Total	Covered	Percent
Branches		15	15	100.00
TERNARY	345	4	4	100.00
TERNARY	610	4	4	100.00
IF	487	2	2	100.00
IF	618	2	2	100.00
IF	513	3	3	100.00

WARNING: The source file /workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' or '../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	345	(seed_en_i) ? 
-2-:	345	((lfsr_en_i && lockup)) ? 
-3-:	345	(lfsr_en_i) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	610	((lfsr_en_i && lockup)) ? 
-2-:	610	((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val))) ? 
-3-:	610	(lfsr_en_i) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	618	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	if ((64'(LfsrType) == 64'("GAL_XOR")))
-2-:	514	if ((next_state == 8'b0))
-3-:	519	if (state0)
-4-:	523	if ((64'(LfsrType) == "FIB_XNOR"))
-5-:	524	if ((&next_state))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	1	-	-	-	Covered	T1,T2,T3
1	0	1	-	-	Covered	T1,T2,T3
1	0	0	-	-	Covered	T1,T2,T3
0	-	-	1	1	Unreachable	T5,T6,T7
0	-	-	1	0	Unreachable	T5,T6,T7
0	-	-	0	-	Unreachable

---

Assert Coverage for Module : prim_lfsr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	20	19	95.00	19	95.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	20	19	95.00	19	95.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CoeffCheck_A	1695326181	1680019341	0	0
DataKnownO_A	1695326181	1680019341	0	0
InputWidth_A	300	300	0	0
NextStateCheck_A	1695326181	1678233717	0	300
NoLockups_A	1695326181	1677774112	0	0
OutputKnown_A	1695326181	1680019341	0	0
OutputWidth_A	300	300	0	0
gen_ext_seed_sva.ExtDefaultSeedInputCheck_A	1695326181	1014827	0	0
gen_fib_xnor.DefaultSeedNzCheck_A	150	150	0	0
gen_fib_xnor.gen_lut.MaxLfsrWidth_A	150	150	0	0
gen_fib_xnor.gen_lut.MinLfsrWidth_A	150	150	0	0
gen_gal_xor.DefaultSeedNzCheck_A	150	150	0	0
gen_gal_xor.gen_lut.MaxLfsrWidth_A	150	150	0	0
gen_gal_xor.gen_lut.MinLfsrWidth_A	150	150	0	0
gen_lockup_mechanism_sva.LfsrLockupCheck_A	1695326181	1438	0	0
gen_max_len_sva.MaximalLengthCheck0_A	1695326181	6900	0	0
gen_max_len_sva.MaximalLengthCheck1_A	1695326181	1677772200	0	0
gen_perm_check.p_perm_check.PermutationCheck_A	300	300	0	0
p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A	300	300	0	0
p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A	0	0	0	0

CoeffCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	1680019341	0	0
T1	40300	5447	0	0
T2	53838	7553	0	0
T3	77644	10257	0	0
T4	70089	9399	0	0
T8	45440	6049	0	0
T9	56653	7214	0	0
T10	76263	10017	0	0
T11	70108	9197	0	0
T12	47253	6043	0	0
T13	50209	6875	0	0
T14	168266	167835	0	0
T15	168212	167825	0	0
T16	168224	167828	0	0
T17	168167	167825	0	0
T18	168298	167842	0	0
T19	168459	167862	0	0
T20	168315	167845	0	0
T21	168496	167866	0	0
T22	168332	167846	0	0
T23	168180	167826	0	0

DataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	1680019341	0	0
T1	40300	5447	0	0
T2	53838	7553	0	0
T3	77644	10257	0	0
T4	70089	9399	0	0
T8	45440	6049	0	0
T9	56653	7214	0	0
T10	76263	10017	0	0
T11	70108	9197	0	0
T12	47253	6043	0	0
T13	50209	6875	0	0
T14	168266	167835	0	0
T15	168212	167825	0	0
T16	168224	167828	0	0
T17	168167	167825	0	0
T18	168298	167842	0	0
T19	168459	167862	0	0
T20	168315	167845	0	0
T21	168496	167866	0	0
T22	168332	167846	0	0
T23	168180	167826	0	0

InputWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300	300	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

NextStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	1678233717	0	300
T1	40300	1330	0	1
T2	53838	1771	0	1
T3	77644	2341	0	1
T4	70089	2200	0	1
T8	45440	1464	0	1
T9	56653	1747	0	1
T10	76263	2249	0	1
T11	70108	2060	0	1
T12	47253	1425	0	1
T13	50209	1636	0	1
T14	168266	167784	0	1
T15	168212	167783	0	1
T16	168224	167783	0	1
T17	168167	167782	0	1
T18	168298	167786	0	1
T19	168459	167790	0	1
T20	168315	167787	0	1
T21	168496	167791	0	1
T22	168332	167787	0	1
T23	168180	167783	0	1

NoLockups_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	1677774112	0	0
T1	40300	260	0	0
T2	53838	263	0	0
T3	77644	268	0	0
T4	70089	266	0	0
T8	45440	261	0	0
T9	56653	262	0	0
T10	76263	262	0	0
T11	70108	266	0	0
T12	47253	261	0	0
T13	50209	260	0	0
T14	168266	167772	0	0
T15	168212	167772	0	0
T16	168224	167772	0	0
T17	168167	167772	0	0
T18	168298	167772	0	0
T19	168459	167772	0	0
T20	168315	167772	0	0
T21	168496	167772	0	0
T22	168332	167772	0	0
T23	168180	167772	0	0

OutputKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	1680019341	0	0
T1	40300	5447	0	0
T2	53838	7553	0	0
T3	77644	10257	0	0
T4	70089	9399	0	0
T8	45440	6049	0	0
T9	56653	7214	0	0
T10	76263	10017	0	0
T11	70108	9197	0	0
T12	47253	6043	0	0
T13	50209	6875	0	0
T14	168266	167835	0	0
T15	168212	167825	0	0
T16	168224	167828	0	0
T17	168167	167825	0	0
T18	168298	167842	0	0
T19	168459	167862	0	0
T20	168315	167845	0	0
T21	168496	167866	0	0
T22	168332	167846	0	0
T23	168180	167826	0	0

OutputWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300	300	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

gen_ext_seed_sva.ExtDefaultSeedInputCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	1014827	0	0
T1	40300	2306	0	0
T2	53838	3307	0	0
T3	77644	4433	0	0
T4	70089	4138	0	0
T8	45440	2562	0	0
T9	56653	3093	0	0
T10	76263	4367	0	0
T11	70108	4043	0	0
T12	47253	2579	0	0
T13	50209	2965	0	0
T14	168266	2894	0	0
T15	168212	2345	0	0
T16	168224	2503	0	0
T17	168167	2436	0	0
T18	168298	3173	0	0
T19	168459	4066	0	0
T20	168315	3236	0	0
T21	168496	4313	0	0
T22	168332	3391	0	0
T23	168180	2486	0	0

gen_fib_xnor.DefaultSeedNzCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150	150	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T24	2	2	0	0
T25	2	2	0	0
T26	2	2	0	0
T27	2	2	0	0
T28	2	2	0	0
T29	2	2	0	0
T30	2	2	0	0

gen_fib_xnor.gen_lut.MaxLfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150	150	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T24	2	2	0	0
T25	2	2	0	0
T26	2	2	0	0
T27	2	2	0	0
T28	2	2	0	0
T29	2	2	0	0
T30	2	2	0	0

gen_fib_xnor.gen_lut.MinLfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150	150	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T24	2	2	0	0
T25	2	2	0	0
T26	2	2	0	0
T27	2	2	0	0
T28	2	2	0	0
T29	2	2	0	0
T30	2	2	0	0

gen_gal_xor.DefaultSeedNzCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150	150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

gen_gal_xor.gen_lut.MaxLfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150	150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

gen_gal_xor.gen_lut.MinLfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150	150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

gen_lockup_mechanism_sva.LfsrLockupCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	1438	0	0
T1	40300	6	0	0
T2	53838	7	0	0
T3	77644	7	0	0
T4	70089	12	0	0
T8	45440	8	0	0
T9	56653	3	0	0
T10	76263	8	0	0
T11	70108	9	0	0
T12	47253	4	0	0
T13	50209	3	0	0
T14	168266	1	0	0
T15	168212	1	0	0
T16	168224	1	0	0
T17	168167	1	0	0
T18	168298	1	0	0
T19	168459	1	0	0
T20	168315	1	0	0
T21	168496	1	0	0
T22	168332	1	0	0
T23	168180	1	0	0

gen_max_len_sva.MaximalLengthCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	6900	0	0
T1	40300	15	0	0
T2	53838	30	0	0
T3	77644	18	0	0
T4	70089	20	0	0
T8	45440	26	0	0
T9	56653	23	0	0
T10	76263	21	0	0
T11	70108	17	0	0
T12	47253	19	0	0
T13	50209	28	0	0
T14	168266	26	0	0
T15	168212	13	0	0
T16	168224	27	0	0
T17	168167	16	0	0
T18	168298	21	0	0
T19	168459	25	0	0
T20	168315	31	0	0
T21	168496	13	0	0
T22	168332	17	0	0
T23	168180	16	0	0

gen_max_len_sva.MaximalLengthCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1695326181	1677772200	0	0
T1	40300	254	0	0
T2	53838	254	0	0
T3	77644	254	0	0
T4	70089	254	0	0
T8	45440	254	0	0
T9	56653	254	0	0
T10	76263	254	0	0
T11	70108	254	0	0
T12	47253	254	0	0
T13	50209	254	0	0
T14	168266	167772	0	0
T15	168212	167772	0	0
T16	168224	167772	0	0
T17	168167	167772	0	0
T18	168298	167772	0	0
T19	168459	167772	0	0
T20	168315	167772	0	0
T21	168496	167772	0	0
T22	168332	167772	0	0
T23	168180	167772	0	0

gen_perm_check.p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300	300	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300	300	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

Line Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
ALWAYS	487	3	3	100.00
ROUTINE	510	10	10	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
ALWAYS	618	5	5	100.00

WARNING: The source file '/workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' or '../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
296	1	1
299	1	1
345	1	1
465	1	1
472	8	8
487	1	1
488	1	1
490	1	1
510	1	1
513	1	1
514	1	1
515	1	1
517	1	1
518	1	1
519	2	2
			MISSING_ELSE
520	1	1
523		unreachable
524		unreachable
525		unreachable
527		unreachable
528		unreachable
529		unreachable
530		unreachable
533		unreachable
536	1	1
610	1	1
615	1	1
618	1	1
619	1	1
620	1	1
622	1	1
623	1	1

---

Cond Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr

	Total	Covered	Percent
Conditions	29	28	96.55
Logical	29	28	96.55
Non-Logical	0	0
Event	0	0

 LINE       345
 EXPRESSION (seed_en_i ? seed_i : ((lfsr_en_i && lockup) ? DefaultSeedLocal : (lfsr_en_i ? next_lfsr_state : lfsr_q)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       345
 SUB-EXPRESSION ((lfsr_en_i && lockup) ? DefaultSeedLocal : (lfsr_en_i ? next_lfsr_state : lfsr_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       345
 SUB-EXPRESSION (lfsr_en_i && lockup)
                 ----1----    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       345
 SUB-EXPRESSION (lfsr_en_i ? next_lfsr_state : lfsr_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       514
 EXPRESSION (next_state == 8'b0)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 EXPRESSION 
 Number  Term
      1  (lfsr_en_i && lockup) ? '0 : ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)) ? '0 : (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i && lockup)
                 ----1----    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION ((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)) ? '0 : (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q))
                 --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val))
                 ----1----    -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val)
                -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       610
 SUB-EXPRESSION (lfsr_en_i ? ((gen_max_len_sva.cnt_q + 1'b1)) : gen_max_len_sva.cnt_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       615
 EXPRESSION (gen_max_len_sva.perturbed_q | ((|entropy_i)) | seed_en_i)
             -------------1-------------   -------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

---

Toggle Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	56	56	100.00
Total Bits 0->1	28	28	100.00
Total Bits 1->0	28	28	100.00

Ports	7	7	100.00
Port Bits	56	56	100.00
Port Bits 0->1	28	28	100.00
Port Bits 1->0	28	28	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
state_o[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

Branch Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr

	Line No.	Total	Covered	Percent
Branches		15	15	100.00
TERNARY	345	4	4	100.00
TERNARY	610	4	4	100.00
IF	487	2	2	100.00
IF	618	2	2	100.00
IF	513	3	3	100.00

WARNING: The source file /workspace/prim_lfsr_dw_8_gal/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv' or '../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	345	(seed_en_i) ? 
-2-:	345	((lfsr_en_i && lockup)) ? 
-3-:	345	(lfsr_en_i) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	610	((lfsr_en_i && lockup)) ? 
-2-:	610	((lfsr_en_i && (gen_max_len_sva.cnt_q == gen_max_len_sva.cmp_val))) ? 
-3-:	610	(lfsr_en_i) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	618	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	if ((64'(LfsrType) == 64'("GAL_XOR")))
-2-:	514	if ((next_state == 8'b0))
-3-:	519	if (state0)
-4-:	523	if ((64'(LfsrType) == "FIB_XNOR"))
-5-:	524	if ((&next_state))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	1	-	-	-	Covered	T1,T2,T3
1	0	1	-	-	Covered	T1,T2,T3
1	0	0	-	-	Covered	T1,T2,T3
0	-	-	1	1	Unreachable	T5,T6,T7
0	-	-	1	0	Unreachable	T5,T6,T7
0	-	-	0	-	Unreachable

---

Assert Coverage for Instance : prim_lfsr_tb.gen_duts[8].i_prim_lfsr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	20	19	95.00	19	95.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	20	19	95.00	19	95.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CoeffCheck_A	11639292	1534279	0	0
DataKnownO_A	11639292	1534279	0	0
InputWidth_A	200	200	0	0
NextStateCheck_A	11639292	355511	0	200
NoLockups_A	11639292	52512	0	0
OutputKnown_A	11639292	1534279	0	0
OutputWidth_A	200	200	0	0
gen_ext_seed_sva.ExtDefaultSeedInputCheck_A	11639292	669876	0	0
gen_fib_xnor.DefaultSeedNzCheck_A	100	100	0	0
gen_fib_xnor.gen_lut.MaxLfsrWidth_A	100	100	0	0
gen_fib_xnor.gen_lut.MinLfsrWidth_A	100	100	0	0
gen_gal_xor.DefaultSeedNzCheck_A	100	100	0	0
gen_gal_xor.gen_lut.MaxLfsrWidth_A	100	100	0	0
gen_gal_xor.gen_lut.MinLfsrWidth_A	100	100	0	0
gen_lockup_mechanism_sva.LfsrLockupCheck_A	11639292	1338	0	0
gen_max_len_sva.MaximalLengthCheck0_A	11639292	4651	0	0
gen_max_len_sva.MaximalLengthCheck1_A	11639292	50800	0	0
gen_perm_check.p_perm_check.PermutationCheck_A	200	200	0	0
p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A	200	200	0	0
p_randomize_default_seed.UseDefaultSeedRandomizeCheck_A	0	0	0	0

CoeffCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	1534279	0	0
T1	40300	5447	0	0
T2	53838	7553	0	0
T3	77644	10257	0	0
T4	70089	9399	0	0
T8	45440	6049	0	0
T9	56653	7214	0	0
T10	76263	10017	0	0
T11	70108	9197	0	0
T12	47253	6043	0	0
T13	50209	6875	0	0

DataKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	1534279	0	0
T1	40300	5447	0	0
T2	53838	7553	0	0
T3	77644	10257	0	0
T4	70089	9399	0	0
T8	45440	6049	0	0
T9	56653	7214	0	0
T10	76263	10017	0	0
T11	70108	9197	0	0
T12	47253	6043	0	0
T13	50209	6875	0	0

InputWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200	200	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

NextStateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	355511	0	200
T1	40300	1330	0	1
T2	53838	1771	0	1
T3	77644	2341	0	1
T4	70089	2200	0	1
T8	45440	1464	0	1
T9	56653	1747	0	1
T10	76263	2249	0	1
T11	70108	2060	0	1
T12	47253	1425	0	1
T13	50209	1636	0	1

NoLockups_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	52512	0	0
T1	40300	260	0	0
T2	53838	263	0	0
T3	77644	268	0	0
T4	70089	266	0	0
T8	45440	261	0	0
T9	56653	262	0	0
T10	76263	262	0	0
T11	70108	266	0	0
T12	47253	261	0	0
T13	50209	260	0	0

OutputKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	1534279	0	0
T1	40300	5447	0	0
T2	53838	7553	0	0
T3	77644	10257	0	0
T4	70089	9399	0	0
T8	45440	6049	0	0
T9	56653	7214	0	0
T10	76263	10017	0	0
T11	70108	9197	0	0
T12	47253	6043	0	0
T13	50209	6875	0	0

OutputWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200	200	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_ext_seed_sva.ExtDefaultSeedInputCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	669876	0	0
T1	40300	2306	0	0
T2	53838	3307	0	0
T3	77644	4433	0	0
T4	70089	4138	0	0
T8	45440	2562	0	0
T9	56653	3093	0	0
T10	76263	4367	0	0
T11	70108	4043	0	0
T12	47253	2579	0	0
T13	50209	2965	0	0

gen_fib_xnor.DefaultSeedNzCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100	100	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

gen_fib_xnor.gen_lut.MaxLfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100	100	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

gen_fib_xnor.gen_lut.MinLfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100	100	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0

gen_gal_xor.DefaultSeedNzCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100	100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_gal_xor.gen_lut.MaxLfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100	100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_gal_xor.gen_lut.MinLfsrWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100	100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_lockup_mechanism_sva.LfsrLockupCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	1338	0	0
T1	40300	6	0	0
T2	53838	7	0	0
T3	77644	7	0	0
T4	70089	12	0	0
T8	45440	8	0	0
T9	56653	3	0	0
T10	76263	8	0	0
T11	70108	9	0	0
T12	47253	4	0	0
T13	50209	3	0	0

gen_max_len_sva.MaximalLengthCheck0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	4651	0	0
T1	40300	15	0	0
T2	53838	30	0	0
T3	77644	18	0	0
T4	70089	20	0	0
T8	45440	26	0	0
T9	56653	23	0	0
T10	76263	21	0	0
T11	70108	17	0	0
T12	47253	19	0	0
T13	50209	28	0	0

gen_max_len_sva.MaximalLengthCheck1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11639292	50800	0	0
T1	40300	254	0	0
T2	53838	254	0	0
T3	77644	254	0	0
T4	70089	254	0	0
T8	45440	254	0	0
T9	56653	254	0	0
T10	76263	254	0	0
T11	70108	254	0	0
T12	47253	254	0	0
T13	50209	254	0	0

gen_perm_check.p_perm_check.PermutationCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200	200	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

p_randomize_default_seed.DefaultSeedLocalRandomizeCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200	200	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0