Unified Coverage Report :: Module :: prim_present

Module : prim_present

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.98	94.88	100.00	100.00		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut	95.39	79.50	100.00	97.46		100.00	100.00
prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut	99.49	100.00	100.00	97.46		100.00	100.00
prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut	100.00	100.00	100.00	100.00		100.00	100.00
prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut	100.00	100.00	100.00	100.00		100.00	100.00

---

Module Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.39	79.50	100.00	97.46		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.39	79.50	100.00	97.46		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_present_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	100.00	97.46		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	100.00	97.46		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_present_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_present_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							prim_present_tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	1	1
106	1	1
109	1	1
111	1	1
123	1	1
139	1	1
144	1	1
145	1	1

---

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=31,Decrypt=0 )
Line Coverage for Module self-instances :

SCORE	LINE
95.39	79.50

prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut

	Line No.	Total	Covered	Percent
TOTAL		161	128	79.50
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	0	1
69	31	31
106	0	31
109	31	31
111	31	31
123	31	31
139	1	1
144	1	1
145	0	1

---

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	1	1
74	1	1
77	1	1
79	1	1
91	1	1
139	1	1
144	1	1
145	1	1

---

Line Coverage for Module : prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=31,Decrypt=1 )
Line Coverage for Module self-instances :

SCORE	LINE
99.49	100.00

prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut

	Line No.	Total	Covered	Percent
TOTAL		161	161	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	31	31
74	31	31
77	31	31
79	31	31
91	31	31
139	1	1
144	1	1
145	1	1

---

Cond Coverage for Module : prim_present

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_present

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	788	788	100.00
Total Bits 0->1	394	394	100.00
Total Bits 1->0	394	394	100.00

Ports	6	6	100.00
Port Bits	788	788	100.00
Port Bits 0->1	394	394	100.00
Port Bits 1->0	394	394	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
idx_i[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
key_o[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idx_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

Branch Coverage for Module : prim_present

	Line No.	Total	Covered	Percent
Branches		1	1	100.00
TERNARY	139	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

---

Assert Coverage for Module : prim_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumPhysRounds0_A	168	168	0	0
SupportedNumPhysRounds1_A	168	168	0	0
SupportedNumRounds_A	168	168	0	0
SupportedWidths_A	168	168	0	0

SupportedNumPhysRounds0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168	168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

SupportedNumPhysRounds1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168	168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168	168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168	168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0

Line Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut

	Line No.	Total	Covered	Percent
TOTAL		161	128	79.50
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	0	0.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	0	1
69	31	31
106	0	31
109	31	31
111	31	31
123	31	31
139	1	1
144	1	1
145	0	1

---

Cond Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut

	Total	Covered	Percent
Totals	6	4	66.67
Total Bits	788	768	97.46
Total Bits 0->1	394	384	97.46
Total Bits 1->0	394	384	97.46

Ports	6	4	66.67
Port Bits	788	768	97.46
Port Bits 0->1	394	384	97.46
Port Bits 1->0	394	384	97.46

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
idx_i[4:0]	No	No		No		INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
key_o[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idx_o[4:0]	No	No		No		OUTPUT

---

Branch Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut

	Line No.	Total	Covered	Percent
Branches		1	1	100.00
TERNARY	139	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

---

Assert Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumPhysRounds0_A	42	42	0	0
SupportedNumPhysRounds1_A	42	42	0	0
SupportedNumRounds_A	42	42	0	0
SupportedWidths_A	42	42	0	0

SupportedNumPhysRounds0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumPhysRounds1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut

	Line No.	Total	Covered	Percent
TOTAL		161	161	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	31	31
74	31	31
77	31	31
79	31	31
91	31	31
139	1	1
144	1	1
145	1	1

---

Cond Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut

	Total	Covered	Percent
Totals	6	4	66.67
Total Bits	788	768	97.46
Total Bits 0->1	394	384	97.46
Total Bits 1->0	394	384	97.46

Ports	6	4	66.67
Port Bits	788	768	97.46
Port Bits 0->1	394	384	97.46
Port Bits 1->0	394	384	97.46

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
idx_i[4:0]	No	No		No		INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
key_o[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idx_o[4:0]	No	No		No		OUTPUT

---

Branch Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut

	Line No.	Total	Covered	Percent
Branches		1	1	100.00
TERNARY	139	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

---

Assert Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumPhysRounds0_A	42	42	0	0
SupportedNumPhysRounds1_A	42	42	0	0
SupportedNumRounds_A	42	42	0	0
SupportedWidths_A	42	42	0	0

SupportedNumPhysRounds0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumPhysRounds1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	1	1
106	1	1
109	1	1
111	1	1
123	1	1
139	1	1
144	1	1
145	1	1

---

Cond Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	788	788	100.00
Total Bits 0->1	394	394	100.00
Total Bits 1->0	394	394	100.00

Ports	6	6	100.00
Port Bits	788	788	100.00
Port Bits 0->1	394	394	100.00
Port Bits 1->0	394	394	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
idx_i[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
key_o[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idx_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

Branch Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut

	Line No.	Total	Covered	Percent
Branches		1	1	100.00
TERNARY	139	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

---

Assert Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumPhysRounds0_A	42	42	0	0
SupportedNumPhysRounds1_A	42	42	0	0
SupportedNumRounds_A	42	42	0	0
SupportedWidths_A	42	42	0	0

SupportedNumPhysRounds0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumPhysRounds1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
63	1	1
64	1	1
69	1	1
74	1	1
77	1	1
79	1	1
91	1	1
139	1	1
144	1	1
145	1	1

---

Cond Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       139
 EXPRESSION 
 Number  Term
      1  (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
                --------------1--------------

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	788	788	100.00
Total Bits 0->1	394	394	100.00
Total Bits 1->0	394	394	100.00

Ports	6	6	100.00
Port Bits	788	788	100.00
Port Bits 0->1	394	394	100.00
Port Bits 1->0	394	394	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
idx_i[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
key_o[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
idx_o[4:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

Branch Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut

	Line No.	Total	Covered	Percent
Branches		1	1	100.00
TERNARY	139	1	1	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_present.sv' or '../src/lowrisc_prim_cipher_0/rtl/prim_present.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((int'(idx_o) == LastRoundIdx)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

---

Assert Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SupportedNumPhysRounds0_A	42	42	0	0
SupportedNumPhysRounds1_A	42	42	0	0
SupportedNumRounds_A	42	42	0	0
SupportedWidths_A	42	42	0	0

SupportedNumPhysRounds0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumPhysRounds1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedNumRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SupportedWidths_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42	42	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0