Line Coverage for Module :
prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 11 | 11 | 100.00 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
61 // initialize
62 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
63 1/1 assign round_key[0] = key_i;
Tests: T1 T2 T3
64 1/1 assign round_idx[0] = idx_i;
Tests: T1 T2 T3
65
66 for (genvar k = 0; k < NumPhysRounds; k++) begin : gen_round
67 logic [DataWidth-1:0] data_state_xor, data_state_sbox;
68 // cipher layers
69 1/1 assign data_state_xor = data_state[k] ^ round_key[k][KeyWidth-1 : KeyWidth-DataWidth];
Tests: T1 T2 T3
70 ////////////////////////////////
71 // decryption pass, performs inverse permutation, sbox and keyschedule
72 if (Decrypt) begin : gen_dec
73 // Decrement round count.
74 assign round_idx[k+1] = round_idx[k] - 1'b1;
75 // original 64bit variant
76 if (DataWidth == 64) begin : gen_d64
77 assign data_state_sbox = prim_cipher_pkg::perm_64bit(data_state_xor,
78 prim_cipher_pkg::PRESENT_PERM64_INV);
79 assign data_state[k+1] = prim_cipher_pkg::sbox4_64bit(data_state_sbox,
80 prim_cipher_pkg::PRESENT_SBOX4_INV);
81 // reduced 32bit variant
82 end else begin : gen_d32
83 assign data_state_sbox = prim_cipher_pkg::perm_32bit(data_state_xor,
84 prim_cipher_pkg::PRESENT_PERM32_INV);
85 assign data_state[k+1] = prim_cipher_pkg::sbox4_32bit(data_state_sbox,
86 prim_cipher_pkg::PRESENT_SBOX4_INV);
87 end
88 // update round key, count goes from 1 to 31 (max)
89 // original 128bit key variant
90 if (KeyWidth == 128) begin : gen_k128
91 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key128(round_key[k],
92 round_idx[k]);
93 // original 80bit key variant
94 end else if (KeyWidth == 80) begin : gen_k80
95 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key80(round_key[k],
96 round_idx[k]);
97 // reduced 64bit key variant
98 end else begin : gen_k64
99 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key64(round_key[k],
100 round_idx[k]);
101 end
102 ////////////////////////////////
103 // encryption pass
104 end else begin : gen_enc
105 // Increment round count.
106 1/1 assign round_idx[k+1] = round_idx[k] + 1'b1;
Tests: T1 T2 T3
107 // original 64bit variant
108 if (DataWidth == 64) begin : gen_d64
109 1/1 assign data_state_sbox = prim_cipher_pkg::sbox4_64bit(data_state_xor,
Tests: T1 T2 T3
110 prim_cipher_pkg::PRESENT_SBOX4);
111 1/1 assign data_state[k+1] = prim_cipher_pkg::perm_64bit(data_state_sbox,
Tests: T1 T2 T3
112 prim_cipher_pkg::PRESENT_PERM64);
113 // reduced 32bit variant
114 end else begin : gen_d32
115 assign data_state_sbox = prim_cipher_pkg::sbox4_32bit(data_state_xor,
116 prim_cipher_pkg::PRESENT_SBOX4);
117 assign data_state[k+1] = prim_cipher_pkg::perm_32bit(data_state_sbox,
118 prim_cipher_pkg::PRESENT_PERM32);
119 end
120 // update round key, count goes from 1 to 31 (max)
121 // original 128bit key variant
122 if (KeyWidth == 128) begin : gen_k128
123 1/1 assign round_key[k+1] = prim_cipher_pkg::present_update_key128(round_key[k], round_idx[k]);
Tests: T1 T2 T3
124 // original 80bit key variant
125 end else if (KeyWidth == 80) begin : gen_k80
126 assign round_key[k+1] = prim_cipher_pkg::present_update_key80(round_key[k], round_idx[k]);
127 // reduced 64bit key variant
128 end else begin : gen_k64
129 assign round_key[k+1] = prim_cipher_pkg::present_update_key64(round_key[k], round_idx[k]);
130 end
131 end // gen_enc
132 ////////////////////////////////
133 end // gen_round
134
135 // This only needs to be applied after the last round.
136 // Note that for a full-round implementation the output index
137 // will be 0 for enc/dec for the last round (either due to wraparound or subtraction).
138 localparam int LastRoundIdx = (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1;
139 1/1 assign data_o = (int'(idx_o) == LastRoundIdx) ?
Tests: T1 T2 T3
140 data_state[NumPhysRounds] ^
141 round_key[NumPhysRounds][KeyWidth-1 : KeyWidth-DataWidth] :
142 data_state[NumPhysRounds];
143
144 1/1 assign key_o = round_key[NumPhysRounds];
Tests: T1 T2 T3
145 1/1 assign idx_o = round_idx[NumPhysRounds];
Tests: T1 T2 T3
Line Coverage for Module :
prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=31,Decrypt=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 161 | 128 | 79.50 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
61 // initialize
62 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
63 1/1 assign round_key[0] = key_i;
Tests: T1 T2 T3
64 0/1 ==> assign round_idx[0] = idx_i;
65
66 for (genvar k = 0; k < NumPhysRounds; k++) begin : gen_round
67 logic [DataWidth-1:0] data_state_xor, data_state_sbox;
68 // cipher layers
69 31/31 assign data_state_xor = data_state[k] ^ round_key[k][KeyWidth-1 : KeyWidth-DataWidth];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
70 ////////////////////////////////
71 // decryption pass, performs inverse permutation, sbox and keyschedule
72 if (Decrypt) begin : gen_dec
73 // Decrement round count.
74 assign round_idx[k+1] = round_idx[k] - 1'b1;
75 // original 64bit variant
76 if (DataWidth == 64) begin : gen_d64
77 assign data_state_sbox = prim_cipher_pkg::perm_64bit(data_state_xor,
78 prim_cipher_pkg::PRESENT_PERM64_INV);
79 assign data_state[k+1] = prim_cipher_pkg::sbox4_64bit(data_state_sbox,
80 prim_cipher_pkg::PRESENT_SBOX4_INV);
81 // reduced 32bit variant
82 end else begin : gen_d32
83 assign data_state_sbox = prim_cipher_pkg::perm_32bit(data_state_xor,
84 prim_cipher_pkg::PRESENT_PERM32_INV);
85 assign data_state[k+1] = prim_cipher_pkg::sbox4_32bit(data_state_sbox,
86 prim_cipher_pkg::PRESENT_SBOX4_INV);
87 end
88 // update round key, count goes from 1 to 31 (max)
89 // original 128bit key variant
90 if (KeyWidth == 128) begin : gen_k128
91 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key128(round_key[k],
92 round_idx[k]);
93 // original 80bit key variant
94 end else if (KeyWidth == 80) begin : gen_k80
95 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key80(round_key[k],
96 round_idx[k]);
97 // reduced 64bit key variant
98 end else begin : gen_k64
99 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key64(round_key[k],
100 round_idx[k]);
101 end
102 ////////////////////////////////
103 // encryption pass
104 end else begin : gen_enc
105 // Increment round count.
106 0/31 ==> assign round_idx[k+1] = round_idx[k] + 1'b1;
107 // original 64bit variant
108 if (DataWidth == 64) begin : gen_d64
109 31/31 assign data_state_sbox = prim_cipher_pkg::sbox4_64bit(data_state_xor,
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
110 prim_cipher_pkg::PRESENT_SBOX4);
111 31/31 assign data_state[k+1] = prim_cipher_pkg::perm_64bit(data_state_sbox,
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
112 prim_cipher_pkg::PRESENT_PERM64);
113 // reduced 32bit variant
114 end else begin : gen_d32
115 assign data_state_sbox = prim_cipher_pkg::sbox4_32bit(data_state_xor,
116 prim_cipher_pkg::PRESENT_SBOX4);
117 assign data_state[k+1] = prim_cipher_pkg::perm_32bit(data_state_sbox,
118 prim_cipher_pkg::PRESENT_PERM32);
119 end
120 // update round key, count goes from 1 to 31 (max)
121 // original 128bit key variant
122 if (KeyWidth == 128) begin : gen_k128
123 31/31 assign round_key[k+1] = prim_cipher_pkg::present_update_key128(round_key[k], round_idx[k]);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
124 // original 80bit key variant
125 end else if (KeyWidth == 80) begin : gen_k80
126 assign round_key[k+1] = prim_cipher_pkg::present_update_key80(round_key[k], round_idx[k]);
127 // reduced 64bit key variant
128 end else begin : gen_k64
129 assign round_key[k+1] = prim_cipher_pkg::present_update_key64(round_key[k], round_idx[k]);
130 end
131 end // gen_enc
132 ////////////////////////////////
133 end // gen_round
134
135 // This only needs to be applied after the last round.
136 // Note that for a full-round implementation the output index
137 // will be 0 for enc/dec for the last round (either due to wraparound or subtraction).
138 localparam int LastRoundIdx = (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1;
139 1/1 assign data_o = (int'(idx_o) == LastRoundIdx) ?
Tests: T1 T2 T3
140 data_state[NumPhysRounds] ^
141 round_key[NumPhysRounds][KeyWidth-1 : KeyWidth-DataWidth] :
142 data_state[NumPhysRounds];
143
144 1/1 assign key_o = round_key[NumPhysRounds];
Tests: T1 T2 T3
145 0/1 ==> assign idx_o = round_idx[NumPhysRounds];
Line Coverage for Module :
prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=1,Decrypt=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 11 | 11 | 100.00 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
61 // initialize
62 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
63 1/1 assign round_key[0] = key_i;
Tests: T1 T2 T3
64 1/1 assign round_idx[0] = idx_i;
Tests: T1 T2 T3
65
66 for (genvar k = 0; k < NumPhysRounds; k++) begin : gen_round
67 logic [DataWidth-1:0] data_state_xor, data_state_sbox;
68 // cipher layers
69 1/1 assign data_state_xor = data_state[k] ^ round_key[k][KeyWidth-1 : KeyWidth-DataWidth];
Tests: T1 T2 T3
70 ////////////////////////////////
71 // decryption pass, performs inverse permutation, sbox and keyschedule
72 if (Decrypt) begin : gen_dec
73 // Decrement round count.
74 1/1 assign round_idx[k+1] = round_idx[k] - 1'b1;
Tests: T1 T2 T3
75 // original 64bit variant
76 if (DataWidth == 64) begin : gen_d64
77 1/1 assign data_state_sbox = prim_cipher_pkg::perm_64bit(data_state_xor,
Tests: T1 T2 T3
78 prim_cipher_pkg::PRESENT_PERM64_INV);
79 1/1 assign data_state[k+1] = prim_cipher_pkg::sbox4_64bit(data_state_sbox,
Tests: T1 T2 T3
80 prim_cipher_pkg::PRESENT_SBOX4_INV);
81 // reduced 32bit variant
82 end else begin : gen_d32
83 assign data_state_sbox = prim_cipher_pkg::perm_32bit(data_state_xor,
84 prim_cipher_pkg::PRESENT_PERM32_INV);
85 assign data_state[k+1] = prim_cipher_pkg::sbox4_32bit(data_state_sbox,
86 prim_cipher_pkg::PRESENT_SBOX4_INV);
87 end
88 // update round key, count goes from 1 to 31 (max)
89 // original 128bit key variant
90 if (KeyWidth == 128) begin : gen_k128
91 1/1 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key128(round_key[k],
Tests: T1 T2 T3
92 round_idx[k]);
93 // original 80bit key variant
94 end else if (KeyWidth == 80) begin : gen_k80
95 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key80(round_key[k],
96 round_idx[k]);
97 // reduced 64bit key variant
98 end else begin : gen_k64
99 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key64(round_key[k],
100 round_idx[k]);
101 end
102 ////////////////////////////////
103 // encryption pass
104 end else begin : gen_enc
105 // Increment round count.
106 assign round_idx[k+1] = round_idx[k] + 1'b1;
107 // original 64bit variant
108 if (DataWidth == 64) begin : gen_d64
109 assign data_state_sbox = prim_cipher_pkg::sbox4_64bit(data_state_xor,
110 prim_cipher_pkg::PRESENT_SBOX4);
111 assign data_state[k+1] = prim_cipher_pkg::perm_64bit(data_state_sbox,
112 prim_cipher_pkg::PRESENT_PERM64);
113 // reduced 32bit variant
114 end else begin : gen_d32
115 assign data_state_sbox = prim_cipher_pkg::sbox4_32bit(data_state_xor,
116 prim_cipher_pkg::PRESENT_SBOX4);
117 assign data_state[k+1] = prim_cipher_pkg::perm_32bit(data_state_sbox,
118 prim_cipher_pkg::PRESENT_PERM32);
119 end
120 // update round key, count goes from 1 to 31 (max)
121 // original 128bit key variant
122 if (KeyWidth == 128) begin : gen_k128
123 assign round_key[k+1] = prim_cipher_pkg::present_update_key128(round_key[k], round_idx[k]);
124 // original 80bit key variant
125 end else if (KeyWidth == 80) begin : gen_k80
126 assign round_key[k+1] = prim_cipher_pkg::present_update_key80(round_key[k], round_idx[k]);
127 // reduced 64bit key variant
128 end else begin : gen_k64
129 assign round_key[k+1] = prim_cipher_pkg::present_update_key64(round_key[k], round_idx[k]);
130 end
131 end // gen_enc
132 ////////////////////////////////
133 end // gen_round
134
135 // This only needs to be applied after the last round.
136 // Note that for a full-round implementation the output index
137 // will be 0 for enc/dec for the last round (either due to wraparound or subtraction).
138 localparam int LastRoundIdx = (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1;
139 1/1 assign data_o = (int'(idx_o) == LastRoundIdx) ?
Tests: T1 T2 T3
140 data_state[NumPhysRounds] ^
141 round_key[NumPhysRounds][KeyWidth-1 : KeyWidth-DataWidth] :
142 data_state[NumPhysRounds];
143
144 1/1 assign key_o = round_key[NumPhysRounds];
Tests: T1 T2 T3
145 1/1 assign idx_o = round_idx[NumPhysRounds];
Tests: T1 T2 T3
Line Coverage for Module :
prim_present ( parameter DataWidth=64,KeyWidth=128,NumRounds=31,NumPhysRounds=31,Decrypt=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 161 | 161 | 100.00 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
61 // initialize
62 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
63 1/1 assign round_key[0] = key_i;
Tests: T1 T2 T3
64 1/1 assign round_idx[0] = idx_i;
Tests: T1 T2 T3
65
66 for (genvar k = 0; k < NumPhysRounds; k++) begin : gen_round
67 logic [DataWidth-1:0] data_state_xor, data_state_sbox;
68 // cipher layers
69 31/31 assign data_state_xor = data_state[k] ^ round_key[k][KeyWidth-1 : KeyWidth-DataWidth];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
70 ////////////////////////////////
71 // decryption pass, performs inverse permutation, sbox and keyschedule
72 if (Decrypt) begin : gen_dec
73 // Decrement round count.
74 31/31 assign round_idx[k+1] = round_idx[k] - 1'b1;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
75 // original 64bit variant
76 if (DataWidth == 64) begin : gen_d64
77 31/31 assign data_state_sbox = prim_cipher_pkg::perm_64bit(data_state_xor,
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
78 prim_cipher_pkg::PRESENT_PERM64_INV);
79 31/31 assign data_state[k+1] = prim_cipher_pkg::sbox4_64bit(data_state_sbox,
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
80 prim_cipher_pkg::PRESENT_SBOX4_INV);
81 // reduced 32bit variant
82 end else begin : gen_d32
83 assign data_state_sbox = prim_cipher_pkg::perm_32bit(data_state_xor,
84 prim_cipher_pkg::PRESENT_PERM32_INV);
85 assign data_state[k+1] = prim_cipher_pkg::sbox4_32bit(data_state_sbox,
86 prim_cipher_pkg::PRESENT_SBOX4_INV);
87 end
88 // update round key, count goes from 1 to 31 (max)
89 // original 128bit key variant
90 if (KeyWidth == 128) begin : gen_k128
91 31/31 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key128(round_key[k],
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
92 round_idx[k]);
93 // original 80bit key variant
94 end else if (KeyWidth == 80) begin : gen_k80
95 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key80(round_key[k],
96 round_idx[k]);
97 // reduced 64bit key variant
98 end else begin : gen_k64
99 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key64(round_key[k],
100 round_idx[k]);
101 end
102 ////////////////////////////////
103 // encryption pass
104 end else begin : gen_enc
105 // Increment round count.
106 assign round_idx[k+1] = round_idx[k] + 1'b1;
107 // original 64bit variant
108 if (DataWidth == 64) begin : gen_d64
109 assign data_state_sbox = prim_cipher_pkg::sbox4_64bit(data_state_xor,
110 prim_cipher_pkg::PRESENT_SBOX4);
111 assign data_state[k+1] = prim_cipher_pkg::perm_64bit(data_state_sbox,
112 prim_cipher_pkg::PRESENT_PERM64);
113 // reduced 32bit variant
114 end else begin : gen_d32
115 assign data_state_sbox = prim_cipher_pkg::sbox4_32bit(data_state_xor,
116 prim_cipher_pkg::PRESENT_SBOX4);
117 assign data_state[k+1] = prim_cipher_pkg::perm_32bit(data_state_sbox,
118 prim_cipher_pkg::PRESENT_PERM32);
119 end
120 // update round key, count goes from 1 to 31 (max)
121 // original 128bit key variant
122 if (KeyWidth == 128) begin : gen_k128
123 assign round_key[k+1] = prim_cipher_pkg::present_update_key128(round_key[k], round_idx[k]);
124 // original 80bit key variant
125 end else if (KeyWidth == 80) begin : gen_k80
126 assign round_key[k+1] = prim_cipher_pkg::present_update_key80(round_key[k], round_idx[k]);
127 // reduced 64bit key variant
128 end else begin : gen_k64
129 assign round_key[k+1] = prim_cipher_pkg::present_update_key64(round_key[k], round_idx[k]);
130 end
131 end // gen_enc
132 ////////////////////////////////
133 end // gen_round
134
135 // This only needs to be applied after the last round.
136 // Note that for a full-round implementation the output index
137 // will be 0 for enc/dec for the last round (either due to wraparound or subtraction).
138 localparam int LastRoundIdx = (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1;
139 1/1 assign data_o = (int'(idx_o) == LastRoundIdx) ?
Tests: T1 T2 T3
140 data_state[NumPhysRounds] ^
141 round_key[NumPhysRounds][KeyWidth-1 : KeyWidth-DataWidth] :
142 data_state[NumPhysRounds];
143
144 1/1 assign key_o = round_key[NumPhysRounds];
Tests: T1 T2 T3
145 1/1 assign idx_o = round_idx[NumPhysRounds];
Tests: T1 T2 T3
Cond Coverage for Module :
prim_present
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 139
EXPRESSION
Number Term
1 (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 139
SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Toggle Coverage for Module :
prim_present
| Total | Covered | Percent |
| Totals |
6 |
6 |
100.00 |
| Total Bits |
788 |
788 |
100.00 |
| Total Bits 0->1 |
394 |
394 |
100.00 |
| Total Bits 1->0 |
394 |
394 |
100.00 |
| | | |
| Ports |
6 |
6 |
100.00 |
| Port Bits |
788 |
788 |
100.00 |
| Port Bits 0->1 |
394 |
394 |
100.00 |
| Port Bits 1->0 |
394 |
394 |
100.00 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| data_i[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| key_i[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| idx_i[4:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| key_o[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| idx_o[4:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
Branch Coverage for Module :
prim_present
| Line No. | Total | Covered | Percent |
| Branches |
|
1 |
1 |
100.00 |
| TERNARY |
139 |
1 |
1 |
100.00 |
139 assign data_o = (int'(idx_o) == LastRoundIdx) ?
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
T1,T2,T3 |
Assert Coverage for Module :
prim_present
Assertion Details
SupportedNumPhysRounds0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
200 |
200 |
0 |
0 |
| T1 |
4 |
4 |
0 |
0 |
| T2 |
4 |
4 |
0 |
0 |
| T3 |
4 |
4 |
0 |
0 |
| T4 |
4 |
4 |
0 |
0 |
| T5 |
4 |
4 |
0 |
0 |
| T6 |
4 |
4 |
0 |
0 |
| T7 |
4 |
4 |
0 |
0 |
| T8 |
4 |
4 |
0 |
0 |
| T9 |
4 |
4 |
0 |
0 |
| T10 |
4 |
4 |
0 |
0 |
SupportedNumPhysRounds1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
200 |
200 |
0 |
0 |
| T1 |
4 |
4 |
0 |
0 |
| T2 |
4 |
4 |
0 |
0 |
| T3 |
4 |
4 |
0 |
0 |
| T4 |
4 |
4 |
0 |
0 |
| T5 |
4 |
4 |
0 |
0 |
| T6 |
4 |
4 |
0 |
0 |
| T7 |
4 |
4 |
0 |
0 |
| T8 |
4 |
4 |
0 |
0 |
| T9 |
4 |
4 |
0 |
0 |
| T10 |
4 |
4 |
0 |
0 |
SupportedNumRounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
200 |
200 |
0 |
0 |
| T1 |
4 |
4 |
0 |
0 |
| T2 |
4 |
4 |
0 |
0 |
| T3 |
4 |
4 |
0 |
0 |
| T4 |
4 |
4 |
0 |
0 |
| T5 |
4 |
4 |
0 |
0 |
| T6 |
4 |
4 |
0 |
0 |
| T7 |
4 |
4 |
0 |
0 |
| T8 |
4 |
4 |
0 |
0 |
| T9 |
4 |
4 |
0 |
0 |
| T10 |
4 |
4 |
0 |
0 |
SupportedWidths_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
200 |
200 |
0 |
0 |
| T1 |
4 |
4 |
0 |
0 |
| T2 |
4 |
4 |
0 |
0 |
| T3 |
4 |
4 |
0 |
0 |
| T4 |
4 |
4 |
0 |
0 |
| T5 |
4 |
4 |
0 |
0 |
| T6 |
4 |
4 |
0 |
0 |
| T7 |
4 |
4 |
0 |
0 |
| T8 |
4 |
4 |
0 |
0 |
| T9 |
4 |
4 |
0 |
0 |
| T10 |
4 |
4 |
0 |
0 |
Line Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 161 | 128 | 79.50 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 106 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 0 | 0.00 |
61 // initialize
62 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
63 1/1 assign round_key[0] = key_i;
Tests: T1 T2 T3
64 0/1 ==> assign round_idx[0] = idx_i;
65
66 for (genvar k = 0; k < NumPhysRounds; k++) begin : gen_round
67 logic [DataWidth-1:0] data_state_xor, data_state_sbox;
68 // cipher layers
69 31/31 assign data_state_xor = data_state[k] ^ round_key[k][KeyWidth-1 : KeyWidth-DataWidth];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
70 ////////////////////////////////
71 // decryption pass, performs inverse permutation, sbox and keyschedule
72 if (Decrypt) begin : gen_dec
73 // Decrement round count.
74 assign round_idx[k+1] = round_idx[k] - 1'b1;
75 // original 64bit variant
76 if (DataWidth == 64) begin : gen_d64
77 assign data_state_sbox = prim_cipher_pkg::perm_64bit(data_state_xor,
78 prim_cipher_pkg::PRESENT_PERM64_INV);
79 assign data_state[k+1] = prim_cipher_pkg::sbox4_64bit(data_state_sbox,
80 prim_cipher_pkg::PRESENT_SBOX4_INV);
81 // reduced 32bit variant
82 end else begin : gen_d32
83 assign data_state_sbox = prim_cipher_pkg::perm_32bit(data_state_xor,
84 prim_cipher_pkg::PRESENT_PERM32_INV);
85 assign data_state[k+1] = prim_cipher_pkg::sbox4_32bit(data_state_sbox,
86 prim_cipher_pkg::PRESENT_SBOX4_INV);
87 end
88 // update round key, count goes from 1 to 31 (max)
89 // original 128bit key variant
90 if (KeyWidth == 128) begin : gen_k128
91 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key128(round_key[k],
92 round_idx[k]);
93 // original 80bit key variant
94 end else if (KeyWidth == 80) begin : gen_k80
95 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key80(round_key[k],
96 round_idx[k]);
97 // reduced 64bit key variant
98 end else begin : gen_k64
99 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key64(round_key[k],
100 round_idx[k]);
101 end
102 ////////////////////////////////
103 // encryption pass
104 end else begin : gen_enc
105 // Increment round count.
106 0/31 ==> assign round_idx[k+1] = round_idx[k] + 1'b1;
107 // original 64bit variant
108 if (DataWidth == 64) begin : gen_d64
109 31/31 assign data_state_sbox = prim_cipher_pkg::sbox4_64bit(data_state_xor,
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
110 prim_cipher_pkg::PRESENT_SBOX4);
111 31/31 assign data_state[k+1] = prim_cipher_pkg::perm_64bit(data_state_sbox,
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
112 prim_cipher_pkg::PRESENT_PERM64);
113 // reduced 32bit variant
114 end else begin : gen_d32
115 assign data_state_sbox = prim_cipher_pkg::sbox4_32bit(data_state_xor,
116 prim_cipher_pkg::PRESENT_SBOX4);
117 assign data_state[k+1] = prim_cipher_pkg::perm_32bit(data_state_sbox,
118 prim_cipher_pkg::PRESENT_PERM32);
119 end
120 // update round key, count goes from 1 to 31 (max)
121 // original 128bit key variant
122 if (KeyWidth == 128) begin : gen_k128
123 31/31 assign round_key[k+1] = prim_cipher_pkg::present_update_key128(round_key[k], round_idx[k]);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
124 // original 80bit key variant
125 end else if (KeyWidth == 80) begin : gen_k80
126 assign round_key[k+1] = prim_cipher_pkg::present_update_key80(round_key[k], round_idx[k]);
127 // reduced 64bit key variant
128 end else begin : gen_k64
129 assign round_key[k+1] = prim_cipher_pkg::present_update_key64(round_key[k], round_idx[k]);
130 end
131 end // gen_enc
132 ////////////////////////////////
133 end // gen_round
134
135 // This only needs to be applied after the last round.
136 // Note that for a full-round implementation the output index
137 // will be 0 for enc/dec for the last round (either due to wraparound or subtraction).
138 localparam int LastRoundIdx = (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1;
139 1/1 assign data_o = (int'(idx_o) == LastRoundIdx) ?
Tests: T1 T2 T3
140 data_state[NumPhysRounds] ^
141 round_key[NumPhysRounds][KeyWidth-1 : KeyWidth-DataWidth] :
142 data_state[NumPhysRounds];
143
144 1/1 assign key_o = round_key[NumPhysRounds];
Tests: T1 T2 T3
145 0/1 ==> assign idx_o = round_idx[NumPhysRounds];
Cond Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 139
EXPRESSION
Number Term
1 (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 139
SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
Toggle Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut
| Total | Covered | Percent |
| Totals |
6 |
4 |
66.67 |
| Total Bits |
788 |
768 |
97.46 |
| Total Bits 0->1 |
394 |
384 |
97.46 |
| Total Bits 1->0 |
394 |
384 |
97.46 |
| | | |
| Ports |
6 |
4 |
66.67 |
| Port Bits |
788 |
768 |
97.46 |
| Port Bits 0->1 |
394 |
384 |
97.46 |
| Port Bits 1->0 |
394 |
384 |
97.46 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| data_i[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| key_i[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| idx_i[4:0] |
No |
No |
|
No |
|
INPUT |
| data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| key_o[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| idx_o[4:0] |
No |
No |
|
No |
|
OUTPUT |
Branch Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut
| Line No. | Total | Covered | Percent |
| Branches |
|
1 |
1 |
100.00 |
| TERNARY |
139 |
1 |
1 |
100.00 |
139 assign data_o = (int'(idx_o) == LastRoundIdx) ?
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
Assert Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[1].dut
Assertion Details
SupportedNumPhysRounds0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedNumPhysRounds1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedNumRounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedWidths_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 161 | 161 | 100.00 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
61 // initialize
62 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
63 1/1 assign round_key[0] = key_i;
Tests: T1 T2 T3
64 1/1 assign round_idx[0] = idx_i;
Tests: T1 T2 T3
65
66 for (genvar k = 0; k < NumPhysRounds; k++) begin : gen_round
67 logic [DataWidth-1:0] data_state_xor, data_state_sbox;
68 // cipher layers
69 31/31 assign data_state_xor = data_state[k] ^ round_key[k][KeyWidth-1 : KeyWidth-DataWidth];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
70 ////////////////////////////////
71 // decryption pass, performs inverse permutation, sbox and keyschedule
72 if (Decrypt) begin : gen_dec
73 // Decrement round count.
74 31/31 assign round_idx[k+1] = round_idx[k] - 1'b1;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
75 // original 64bit variant
76 if (DataWidth == 64) begin : gen_d64
77 31/31 assign data_state_sbox = prim_cipher_pkg::perm_64bit(data_state_xor,
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
78 prim_cipher_pkg::PRESENT_PERM64_INV);
79 31/31 assign data_state[k+1] = prim_cipher_pkg::sbox4_64bit(data_state_sbox,
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
80 prim_cipher_pkg::PRESENT_SBOX4_INV);
81 // reduced 32bit variant
82 end else begin : gen_d32
83 assign data_state_sbox = prim_cipher_pkg::perm_32bit(data_state_xor,
84 prim_cipher_pkg::PRESENT_PERM32_INV);
85 assign data_state[k+1] = prim_cipher_pkg::sbox4_32bit(data_state_sbox,
86 prim_cipher_pkg::PRESENT_SBOX4_INV);
87 end
88 // update round key, count goes from 1 to 31 (max)
89 // original 128bit key variant
90 if (KeyWidth == 128) begin : gen_k128
91 31/31 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key128(round_key[k],
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
92 round_idx[k]);
93 // original 80bit key variant
94 end else if (KeyWidth == 80) begin : gen_k80
95 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key80(round_key[k],
96 round_idx[k]);
97 // reduced 64bit key variant
98 end else begin : gen_k64
99 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key64(round_key[k],
100 round_idx[k]);
101 end
102 ////////////////////////////////
103 // encryption pass
104 end else begin : gen_enc
105 // Increment round count.
106 assign round_idx[k+1] = round_idx[k] + 1'b1;
107 // original 64bit variant
108 if (DataWidth == 64) begin : gen_d64
109 assign data_state_sbox = prim_cipher_pkg::sbox4_64bit(data_state_xor,
110 prim_cipher_pkg::PRESENT_SBOX4);
111 assign data_state[k+1] = prim_cipher_pkg::perm_64bit(data_state_sbox,
112 prim_cipher_pkg::PRESENT_PERM64);
113 // reduced 32bit variant
114 end else begin : gen_d32
115 assign data_state_sbox = prim_cipher_pkg::sbox4_32bit(data_state_xor,
116 prim_cipher_pkg::PRESENT_SBOX4);
117 assign data_state[k+1] = prim_cipher_pkg::perm_32bit(data_state_sbox,
118 prim_cipher_pkg::PRESENT_PERM32);
119 end
120 // update round key, count goes from 1 to 31 (max)
121 // original 128bit key variant
122 if (KeyWidth == 128) begin : gen_k128
123 assign round_key[k+1] = prim_cipher_pkg::present_update_key128(round_key[k], round_idx[k]);
124 // original 80bit key variant
125 end else if (KeyWidth == 80) begin : gen_k80
126 assign round_key[k+1] = prim_cipher_pkg::present_update_key80(round_key[k], round_idx[k]);
127 // reduced 64bit key variant
128 end else begin : gen_k64
129 assign round_key[k+1] = prim_cipher_pkg::present_update_key64(round_key[k], round_idx[k]);
130 end
131 end // gen_enc
132 ////////////////////////////////
133 end // gen_round
134
135 // This only needs to be applied after the last round.
136 // Note that for a full-round implementation the output index
137 // will be 0 for enc/dec for the last round (either due to wraparound or subtraction).
138 localparam int LastRoundIdx = (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1;
139 1/1 assign data_o = (int'(idx_o) == LastRoundIdx) ?
Tests: T1 T2 T3
140 data_state[NumPhysRounds] ^
141 round_key[NumPhysRounds][KeyWidth-1 : KeyWidth-DataWidth] :
142 data_state[NumPhysRounds];
143
144 1/1 assign key_o = round_key[NumPhysRounds];
Tests: T1 T2 T3
145 1/1 assign idx_o = round_idx[NumPhysRounds];
Tests: T1 T2 T3
Cond Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 139
EXPRESSION
Number Term
1 (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
LINE 139
SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Covered | T1,T2,T3 |
Toggle Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut
| Total | Covered | Percent |
| Totals |
6 |
4 |
66.67 |
| Total Bits |
788 |
768 |
97.46 |
| Total Bits 0->1 |
394 |
384 |
97.46 |
| Total Bits 1->0 |
394 |
384 |
97.46 |
| | | |
| Ports |
6 |
4 |
66.67 |
| Port Bits |
788 |
768 |
97.46 |
| Port Bits 0->1 |
394 |
384 |
97.46 |
| Port Bits 1->0 |
394 |
384 |
97.46 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| data_i[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| key_i[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| idx_i[4:0] |
No |
No |
|
No |
|
INPUT |
| data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| key_o[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| idx_o[4:0] |
No |
No |
|
No |
|
OUTPUT |
Branch Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut
| Line No. | Total | Covered | Percent |
| Branches |
|
1 |
1 |
100.00 |
| TERNARY |
139 |
1 |
1 |
100.00 |
139 assign data_o = (int'(idx_o) == LastRoundIdx) ?
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
|
Assert Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[1].dut
Assertion Details
SupportedNumPhysRounds0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedNumPhysRounds1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedNumRounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedWidths_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 11 | 11 | 100.00 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
61 // initialize
62 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
63 1/1 assign round_key[0] = key_i;
Tests: T1 T2 T3
64 1/1 assign round_idx[0] = idx_i;
Tests: T1 T2 T3
65
66 for (genvar k = 0; k < NumPhysRounds; k++) begin : gen_round
67 logic [DataWidth-1:0] data_state_xor, data_state_sbox;
68 // cipher layers
69 1/1 assign data_state_xor = data_state[k] ^ round_key[k][KeyWidth-1 : KeyWidth-DataWidth];
Tests: T1 T2 T3
70 ////////////////////////////////
71 // decryption pass, performs inverse permutation, sbox and keyschedule
72 if (Decrypt) begin : gen_dec
73 // Decrement round count.
74 assign round_idx[k+1] = round_idx[k] - 1'b1;
75 // original 64bit variant
76 if (DataWidth == 64) begin : gen_d64
77 assign data_state_sbox = prim_cipher_pkg::perm_64bit(data_state_xor,
78 prim_cipher_pkg::PRESENT_PERM64_INV);
79 assign data_state[k+1] = prim_cipher_pkg::sbox4_64bit(data_state_sbox,
80 prim_cipher_pkg::PRESENT_SBOX4_INV);
81 // reduced 32bit variant
82 end else begin : gen_d32
83 assign data_state_sbox = prim_cipher_pkg::perm_32bit(data_state_xor,
84 prim_cipher_pkg::PRESENT_PERM32_INV);
85 assign data_state[k+1] = prim_cipher_pkg::sbox4_32bit(data_state_sbox,
86 prim_cipher_pkg::PRESENT_SBOX4_INV);
87 end
88 // update round key, count goes from 1 to 31 (max)
89 // original 128bit key variant
90 if (KeyWidth == 128) begin : gen_k128
91 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key128(round_key[k],
92 round_idx[k]);
93 // original 80bit key variant
94 end else if (KeyWidth == 80) begin : gen_k80
95 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key80(round_key[k],
96 round_idx[k]);
97 // reduced 64bit key variant
98 end else begin : gen_k64
99 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key64(round_key[k],
100 round_idx[k]);
101 end
102 ////////////////////////////////
103 // encryption pass
104 end else begin : gen_enc
105 // Increment round count.
106 1/1 assign round_idx[k+1] = round_idx[k] + 1'b1;
Tests: T1 T2 T3
107 // original 64bit variant
108 if (DataWidth == 64) begin : gen_d64
109 1/1 assign data_state_sbox = prim_cipher_pkg::sbox4_64bit(data_state_xor,
Tests: T1 T2 T3
110 prim_cipher_pkg::PRESENT_SBOX4);
111 1/1 assign data_state[k+1] = prim_cipher_pkg::perm_64bit(data_state_sbox,
Tests: T1 T2 T3
112 prim_cipher_pkg::PRESENT_PERM64);
113 // reduced 32bit variant
114 end else begin : gen_d32
115 assign data_state_sbox = prim_cipher_pkg::sbox4_32bit(data_state_xor,
116 prim_cipher_pkg::PRESENT_SBOX4);
117 assign data_state[k+1] = prim_cipher_pkg::perm_32bit(data_state_sbox,
118 prim_cipher_pkg::PRESENT_PERM32);
119 end
120 // update round key, count goes from 1 to 31 (max)
121 // original 128bit key variant
122 if (KeyWidth == 128) begin : gen_k128
123 1/1 assign round_key[k+1] = prim_cipher_pkg::present_update_key128(round_key[k], round_idx[k]);
Tests: T1 T2 T3
124 // original 80bit key variant
125 end else if (KeyWidth == 80) begin : gen_k80
126 assign round_key[k+1] = prim_cipher_pkg::present_update_key80(round_key[k], round_idx[k]);
127 // reduced 64bit key variant
128 end else begin : gen_k64
129 assign round_key[k+1] = prim_cipher_pkg::present_update_key64(round_key[k], round_idx[k]);
130 end
131 end // gen_enc
132 ////////////////////////////////
133 end // gen_round
134
135 // This only needs to be applied after the last round.
136 // Note that for a full-round implementation the output index
137 // will be 0 for enc/dec for the last round (either due to wraparound or subtraction).
138 localparam int LastRoundIdx = (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1;
139 1/1 assign data_o = (int'(idx_o) == LastRoundIdx) ?
Tests: T1 T2 T3
140 data_state[NumPhysRounds] ^
141 round_key[NumPhysRounds][KeyWidth-1 : KeyWidth-DataWidth] :
142 data_state[NumPhysRounds];
143
144 1/1 assign key_o = round_key[NumPhysRounds];
Tests: T1 T2 T3
145 1/1 assign idx_o = round_idx[NumPhysRounds];
Tests: T1 T2 T3
Cond Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 139
EXPRESSION
Number Term
1 (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 139
SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Toggle Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut
| Total | Covered | Percent |
| Totals |
6 |
6 |
100.00 |
| Total Bits |
788 |
788 |
100.00 |
| Total Bits 0->1 |
394 |
394 |
100.00 |
| Total Bits 1->0 |
394 |
394 |
100.00 |
| | | |
| Ports |
6 |
6 |
100.00 |
| Port Bits |
788 |
788 |
100.00 |
| Port Bits 0->1 |
394 |
394 |
100.00 |
| Port Bits 1->0 |
394 |
394 |
100.00 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| data_i[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| key_i[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| idx_i[4:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| key_o[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| idx_o[4:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
Branch Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut
| Line No. | Total | Covered | Percent |
| Branches |
|
1 |
1 |
100.00 |
| TERNARY |
139 |
1 |
1 |
100.00 |
139 assign data_o = (int'(idx_o) == LastRoundIdx) ?
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
T1,T2,T3 |
Assert Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[0].gen_duts[0].dut
Assertion Details
SupportedNumPhysRounds0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedNumPhysRounds1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedNumRounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedWidths_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 11 | 11 | 100.00 |
| CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
61 // initialize
62 1/1 assign data_state[0] = data_i;
Tests: T1 T2 T3
63 1/1 assign round_key[0] = key_i;
Tests: T1 T2 T3
64 1/1 assign round_idx[0] = idx_i;
Tests: T1 T2 T3
65
66 for (genvar k = 0; k < NumPhysRounds; k++) begin : gen_round
67 logic [DataWidth-1:0] data_state_xor, data_state_sbox;
68 // cipher layers
69 1/1 assign data_state_xor = data_state[k] ^ round_key[k][KeyWidth-1 : KeyWidth-DataWidth];
Tests: T1 T2 T3
70 ////////////////////////////////
71 // decryption pass, performs inverse permutation, sbox and keyschedule
72 if (Decrypt) begin : gen_dec
73 // Decrement round count.
74 1/1 assign round_idx[k+1] = round_idx[k] - 1'b1;
Tests: T1 T2 T3
75 // original 64bit variant
76 if (DataWidth == 64) begin : gen_d64
77 1/1 assign data_state_sbox = prim_cipher_pkg::perm_64bit(data_state_xor,
Tests: T1 T2 T3
78 prim_cipher_pkg::PRESENT_PERM64_INV);
79 1/1 assign data_state[k+1] = prim_cipher_pkg::sbox4_64bit(data_state_sbox,
Tests: T1 T2 T3
80 prim_cipher_pkg::PRESENT_SBOX4_INV);
81 // reduced 32bit variant
82 end else begin : gen_d32
83 assign data_state_sbox = prim_cipher_pkg::perm_32bit(data_state_xor,
84 prim_cipher_pkg::PRESENT_PERM32_INV);
85 assign data_state[k+1] = prim_cipher_pkg::sbox4_32bit(data_state_sbox,
86 prim_cipher_pkg::PRESENT_SBOX4_INV);
87 end
88 // update round key, count goes from 1 to 31 (max)
89 // original 128bit key variant
90 if (KeyWidth == 128) begin : gen_k128
91 1/1 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key128(round_key[k],
Tests: T1 T2 T3
92 round_idx[k]);
93 // original 80bit key variant
94 end else if (KeyWidth == 80) begin : gen_k80
95 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key80(round_key[k],
96 round_idx[k]);
97 // reduced 64bit key variant
98 end else begin : gen_k64
99 assign round_key[k+1] = prim_cipher_pkg::present_inv_update_key64(round_key[k],
100 round_idx[k]);
101 end
102 ////////////////////////////////
103 // encryption pass
104 end else begin : gen_enc
105 // Increment round count.
106 assign round_idx[k+1] = round_idx[k] + 1'b1;
107 // original 64bit variant
108 if (DataWidth == 64) begin : gen_d64
109 assign data_state_sbox = prim_cipher_pkg::sbox4_64bit(data_state_xor,
110 prim_cipher_pkg::PRESENT_SBOX4);
111 assign data_state[k+1] = prim_cipher_pkg::perm_64bit(data_state_sbox,
112 prim_cipher_pkg::PRESENT_PERM64);
113 // reduced 32bit variant
114 end else begin : gen_d32
115 assign data_state_sbox = prim_cipher_pkg::sbox4_32bit(data_state_xor,
116 prim_cipher_pkg::PRESENT_SBOX4);
117 assign data_state[k+1] = prim_cipher_pkg::perm_32bit(data_state_sbox,
118 prim_cipher_pkg::PRESENT_PERM32);
119 end
120 // update round key, count goes from 1 to 31 (max)
121 // original 128bit key variant
122 if (KeyWidth == 128) begin : gen_k128
123 assign round_key[k+1] = prim_cipher_pkg::present_update_key128(round_key[k], round_idx[k]);
124 // original 80bit key variant
125 end else if (KeyWidth == 80) begin : gen_k80
126 assign round_key[k+1] = prim_cipher_pkg::present_update_key80(round_key[k], round_idx[k]);
127 // reduced 64bit key variant
128 end else begin : gen_k64
129 assign round_key[k+1] = prim_cipher_pkg::present_update_key64(round_key[k], round_idx[k]);
130 end
131 end // gen_enc
132 ////////////////////////////////
133 end // gen_round
134
135 // This only needs to be applied after the last round.
136 // Note that for a full-round implementation the output index
137 // will be 0 for enc/dec for the last round (either due to wraparound or subtraction).
138 localparam int LastRoundIdx = (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1;
139 1/1 assign data_o = (int'(idx_o) == LastRoundIdx) ?
Tests: T1 T2 T3
140 data_state[NumPhysRounds] ^
141 round_key[NumPhysRounds][KeyWidth-1 : KeyWidth-DataWidth] :
142 data_state[NumPhysRounds];
143
144 1/1 assign key_o = round_key[NumPhysRounds];
Tests: T1 T2 T3
145 1/1 assign idx_o = round_idx[NumPhysRounds];
Tests: T1 T2 T3
Cond Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 139
EXPRESSION
Number Term
1 (int'(idx_o) == LastRoundIdx) ? ((data_state[NumPhysRounds] ^ round_key[NumPhysRounds][(KeyWidth - 1):(KeyWidth - DataWidth)])) : data_state[NumPhysRounds])
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 139
SUB-EXPRESSION (int'(idx_o) == LastRoundIdx)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Unreachable | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Toggle Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut
| Total | Covered | Percent |
| Totals |
6 |
6 |
100.00 |
| Total Bits |
788 |
788 |
100.00 |
| Total Bits 0->1 |
394 |
394 |
100.00 |
| Total Bits 1->0 |
394 |
394 |
100.00 |
| | | |
| Ports |
6 |
6 |
100.00 |
| Port Bits |
788 |
788 |
100.00 |
| Port Bits 0->1 |
394 |
394 |
100.00 |
| Port Bits 1->0 |
394 |
394 |
100.00 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| data_i[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| key_i[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| idx_i[4:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| data_o[63:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| key_o[127:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| idx_o[4:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
Branch Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut
| Line No. | Total | Covered | Percent |
| Branches |
|
1 |
1 |
100.00 |
| TERNARY |
139 |
1 |
1 |
100.00 |
139 assign data_o = (int'(idx_o) == LastRoundIdx) ?
-1-
==>
==> (Unreachable)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Unreachable |
T1,T2,T3 |
Assert Coverage for Instance : prim_present_tb.gen_encrypt_decrypt[1].gen_duts[0].dut
Assertion Details
SupportedNumPhysRounds0_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedNumPhysRounds1_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedNumRounds_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
SupportedWidths_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
50 |
50 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |