ac0bef2ce
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 6.000s | 1.067ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 21.127us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 3.000s | 18.472us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 2.665ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 1.060ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 71.126us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 18.472us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 4.000s | 1.060ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | pulse | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | blink | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | heartbeat | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | resolution | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | multi_channel | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | polarity | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | phase | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | lowpower | pwm_rand_output | 1.133m | 21.874ms | 50 | 50 | 100.00 |
V2 | perf | pwm_perf | 50.000s | 21.006ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.317m | 639.975ms | 49 | 50 | 98.00 |
V2 | alert_test | pwm_alert_test | 3.000s | 112.988us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 3.000s | 32.402us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 7.000s | 49.321us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 7.000s | 49.321us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 21.127us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 18.472us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 4.000s | 1.060ms | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 975.165us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 21.127us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 18.472us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 4.000s | 1.060ms | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 975.165us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 289 | 290 | 99.66 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 427.614us | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 66.860us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 427.614us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 419 | 420 | 99.76 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 6 | 85.71 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.57 | 99.59 | 99.26 | 99.96 | 94.96 | 94.92 | -- | 100.00 | 99.34 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 1 failures:
28.pwm_stress_all.2823090938
Line 2574, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/28.pwm_stress_all/latest/run.log
UVM_ERROR @ 184780881262 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 184780881262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---