PWRMGR Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: 3df77bec1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	29.310us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	31.559us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	20.884us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.830s	265.057us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.040s	173.751us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.270s	51.069us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	20.884us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	173.751us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.610s	246.837us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.610s	246.837us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.810s	42.728us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	43.940us	50	50	100.00
V2	reset	pwrmgr_reset	1.340s	72.017us	50	50	100.00
		pwrmgr_reset_invalid	1.070s	95.668us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.340s	72.017us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.870s	295.715us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.640s	278.474us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.000s	56.145us	49	50	98.00
V2	stress_all	pwrmgr_stress_all	6.980s	1.837ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.630s	17.534us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.700s	919.025us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.700s	919.025us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	31.559us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.884us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	173.751us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	64.801us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	31.559us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.884us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	173.751us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	64.801us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.680s	206.115us	20	20	100.00
		pwrmgr_sec_cm	2.230s	1.284ms	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.230s	1.284ms	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.230s	1.284ms	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.680s	206.115us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.990s	825.946us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.150s	832.820us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	66.097us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.660s	29.796us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.230s	1.284ms	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.230s	1.284ms	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.230s	1.284ms	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	48.606us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	61.784us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.570s	213.584us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	20.884us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	20.884us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	40.230s	13.022ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1068	1070	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	98.21	96.58	99.44	96.00	96.27	100.00	99.02

Failure Buckets

• Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:

  • Test pwrmgr_disable_rom_integrity_check has 1 failures.

    • 28.pwrmgr_disable_rom_integrity_check.3815860072
      Line 228, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest/run.log

            Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])'
        UVM_ERROR @  56022026 ps: (pwrmgr.sv:155) [ASSERT FAILED] PwrmgrSecCmEscToSlowResetReq_A
        UVM_INFO @  56022026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 49.pwrmgr_stress_all_with_rand_reset.1849625047
      Line 1280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 5399712009 ps: (pwrmgr.sv:160) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 5399712009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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