PWRMGR Simulation Results

Sunday August 27 2023 19:02:43 UTC

GitHub Revision: `dce077626`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2741363328

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.700s	30.412us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	32.302us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	49.235us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.020s	161.067us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.010s	48.677us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.310s	101.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	49.235us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	48.677us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.690s	296.383us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.690s	296.383us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.830s	69.126us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	41.672us	50	50	100.00
V2	reset	pwrmgr_reset	1.300s	81.937us	50	50	100.00
		pwrmgr_reset_invalid	1.010s	74.637us	0	50	0.00
V2	main_power_glitch_reset	pwrmgr_reset	1.300s	81.937us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.710s	346.504us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.460s	288.396us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.950s	66.260us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.840s	2.290ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.660s	21.989us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.560s	550.017us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.560s	550.017us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	32.302us	5	5	100.00
		pwrmgr_csr_rw	0.700s	49.235us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	48.677us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	40.265us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	32.302us	5	5	100.00
		pwrmgr_csr_rw	0.700s	49.235us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	48.677us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	40.265us	20	20	100.00
V2		TOTAL			489	540	90.56
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.790s	736.335us	20	20	100.00
		pwrmgr_sec_cm	2.080s	677.936us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.080s	677.936us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.080s	677.936us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.790s	736.335us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.270s	829.720us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.240s	914.896us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.950s	74.763us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	30.038us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.080s	677.936us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.080s	677.936us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.080s	677.936us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	39.770us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	56.312us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.700s	289.266us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	49.235us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	49.235us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	46.020s	11.654ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1018	1070	95.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.80	98.22	96.58	99.44	74.00	96.32	100.00	99.02

Failure Buckets

Offending '(fast_state == FastPwrStateRomCheckGood)' has 50 failures:

Test pwrmgr_reset_invalid has 50 failures.

0.pwrmgr_reset_invalid.3747988272
Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @  73846087 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @  73846087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_reset_invalid.818442199
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @  85275646 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @  85275646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_wakeup_reset has 1 failures.
  - 10.pwrmgr_wakeup_reset.1264692604
    Line 395, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 49.pwrmgr_stress_all_with_rand_reset.2049351373
    Line 3127, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
      Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
  UVM_ERROR @ 17267389845 ps: (pwrmgr_sec_cm_checker_assert.sv:121) [ASSERT FAILED] RstreqChkMainpd_A
  UVM_INFO @ 17267389845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```