Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	590180	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

284790

1

T1

1468

T2

51

T3

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	551169	1			T1	2764		T2	126		T3	36
values[0x0]	161576	1			T1	1534		T2	18		T3	61
values[0x1]	162225	1			T1	1526		T2	10		T3	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	467604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

407366

1

T1

2361

T2

70

T3

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3140	1			T1	17		T2	2		T3	1
valid_sources[0x01]	3695	1			T1	25		T6	3		T10	2
valid_sources[0x02]	7247	1			T1	19		T10	18		T55	4
valid_sources[0x03]	8009	1			T1	17		T2	2		T5	1
valid_sources[0x04]	2840	1			T1	14		T10	17		T54	5
valid_sources[0x05]	2729	1			T1	30		T3	3		T6	3
valid_sources[0x06]	2736	1			T1	18		T5	3		T6	4
valid_sources[0x07]	2899	1			T1	30		T10	4		T55	1
valid_sources[0x08]	2694	1			T1	28		T5	1		T6	3
valid_sources[0x09]	3085	1			T1	27		T5	1		T10	1
valid_sources[0x0a]	3442	1			T1	30		T3	3		T5	2
valid_sources[0x0b]	2758	1			T1	14		T2	1		T5	2
valid_sources[0x0c]	2629	1			T1	15		T2	1		T6	2
valid_sources[0x0d]	2735	1			T1	26		T6	2		T10	27
valid_sources[0x0e]	3062	1			T1	15		T2	1		T6	1
valid_sources[0x0f]	2836	1			T1	28		T10	10		T55	3
valid_sources[0x10]	2855	1			T1	30		T5	1		T10	5
valid_sources[0x11]	2948	1			T1	22		T2	2		T6	1
valid_sources[0x12]	2831	1			T1	25		T2	1		T6	3
valid_sources[0x13]	2718	1			T1	14		T10	2		T54	12
valid_sources[0x14]	6140	1			T1	22		T6	2		T10	7
valid_sources[0x15]	2575	1			T1	13		T2	1		T6	1
valid_sources[0x16]	2654	1			T1	20		T3	2		T10	5
valid_sources[0x17]	3000	1			T1	23		T2	1		T3	4
valid_sources[0x18]	2883	1			T1	21		T5	1		T6	1
valid_sources[0x19]	3933	1			T1	14		T2	1		T6	2
valid_sources[0x1a]	5137	1			T1	25		T6	1		T37	8
valid_sources[0x1b]	6044	1			T1	32		T6	1		T10	13
valid_sources[0x1c]	3236	1			T1	22		T6	1		T10	21
valid_sources[0x1d]	2937	1			T1	24		T2	1		T3	4
valid_sources[0x1e]	2658	1			T1	24		T2	1		T5	3
valid_sources[0x1f]	3294	1			T1	23		T10	5		T55	1
valid_sources[0x20]	2623	1			T1	21		T2	1		T6	4
valid_sources[0x21]	2841	1			T1	31		T2	1		T3	13
valid_sources[0x22]	2610	1			T1	14		T2	1		T6	3
valid_sources[0x23]	2979	1			T1	17		T2	2		T10	8
valid_sources[0x24]	3098	1			T1	18		T6	4		T10	15
valid_sources[0x25]	2587	1			T1	21		T6	1		T10	28
valid_sources[0x26]	3188	1			T1	40		T6	1		T10	5
valid_sources[0x27]	4995	1			T1	22		T6	1		T10	12
valid_sources[0x28]	10963	1			T1	19		T2	1		T10	14
valid_sources[0x29]	4099	1			T1	16		T4	1		T6	1
valid_sources[0x2a]	2668	1			T1	28		T6	1		T10	7
valid_sources[0x2b]	4133	1			T1	22		T2	3		T6	3
valid_sources[0x2c]	2286	1			T1	20		T2	3		T5	2
valid_sources[0x2d]	3682	1			T1	18		T5	3		T6	2
valid_sources[0x2e]	2589	1			T1	16		T6	2		T10	27
valid_sources[0x2f]	6044	1			T1	29		T10	6		T37	4
valid_sources[0x30]	6288	1			T1	13		T2	1		T3	4
valid_sources[0x31]	2686	1			T1	36		T3	5		T10	21
valid_sources[0x32]	3164	1			T1	18		T6	3		T10	12
valid_sources[0x33]	3037	1			T1	21		T4	1		T5	4
valid_sources[0x34]	2843	1			T1	33		T2	1		T3	4
valid_sources[0x35]	2782	1			T1	25		T2	1		T5	1
valid_sources[0x36]	2912	1			T1	35		T2	2		T6	3
valid_sources[0x37]	3769	1			T1	25		T6	1		T10	13
valid_sources[0x38]	3722	1			T1	21		T6	1		T10	15
valid_sources[0x39]	3100	1			T1	22		T6	1		T10	6
valid_sources[0x3a]	2655	1			T1	28		T6	3		T55	1
valid_sources[0x3b]	2901	1			T1	24		T6	1		T10	17
valid_sources[0x3c]	2671	1			T1	15		T10	10		T54	9
valid_sources[0x3d]	2594	1			T1	15		T6	1		T10	20
valid_sources[0x3e]	2757	1			T1	25		T2	2		T6	2
valid_sources[0x3f]	2394	1			T1	27		T2	4		T3	2
valid_sources[0x40]	3823	1			T1	27		T3	2		T10	13
valid_sources[0x41]	9193	1			T1	17		T6	1		T10	2
valid_sources[0x42]	2490	1			T1	18		T2	1		T6	1
valid_sources[0x43]	2638	1			T1	32		T2	1		T3	5
valid_sources[0x44]	3983	1			T1	18		T2	2		T10	11
valid_sources[0x45]	5507	1			T1	26		T6	1		T10	4
valid_sources[0x46]	2633	1			T1	24		T2	1		T6	3
valid_sources[0x47]	2648	1			T1	12		T2	1		T3	4
valid_sources[0x48]	3610	1			T1	22		T2	1		T6	1
valid_sources[0x49]	2612	1			T1	25		T2	1		T4	3
valid_sources[0x4a]	2490	1			T1	16		T2	2		T10	11
valid_sources[0x4b]	7540	1			T1	26		T10	12		T21	1
valid_sources[0x4c]	3312	1			T1	25		T5	1		T6	1
valid_sources[0x4d]	2687	1			T1	27		T6	1		T10	24
valid_sources[0x4e]	2867	1			T1	22		T2	1		T6	2
valid_sources[0x4f]	2716	1			T1	22		T2	2		T5	1
valid_sources[0x50]	2564	1			T1	21		T2	1		T3	2
valid_sources[0x51]	2591	1			T1	21		T6	2		T10	15
valid_sources[0x52]	2862	1			T1	19		T2	1		T6	4
valid_sources[0x53]	4176	1			T1	27		T2	1		T6	2
valid_sources[0x54]	2659	1			T1	18		T3	1		T4	1
valid_sources[0x55]	2479	1			T1	19		T10	20		T55	2
valid_sources[0x56]	2931	1			T1	24		T6	2		T10	17
valid_sources[0x57]	2692	1			T1	17		T2	1		T6	1
valid_sources[0x58]	2918	1			T1	24		T2	1		T5	3
valid_sources[0x59]	2806	1			T1	22		T2	1		T6	2
valid_sources[0x5a]	3241	1			T1	25		T2	1		T6	1
valid_sources[0x5b]	3808	1			T1	28		T6	1		T10	14
valid_sources[0x5c]	2513	1			T1	12		T2	3		T55	2
valid_sources[0x5d]	3019	1			T1	29		T10	4		T54	6
valid_sources[0x5e]	2590	1			T1	17		T3	12		T10	5
valid_sources[0x5f]	2646	1			T1	25		T2	2		T10	23
valid_sources[0x60]	2896	1			T1	26		T2	2		T6	2
valid_sources[0x61]	4135	1			T1	23		T6	1		T10	3
valid_sources[0x62]	2698	1			T1	15		T3	7		T10	9
valid_sources[0x63]	2755	1			T1	14		T6	1		T10	12
valid_sources[0x64]	4244	1			T1	31		T6	1		T10	4
valid_sources[0x65]	2693	1			T1	16		T6	2		T10	30
valid_sources[0x66]	3010	1			T1	22		T2	2		T10	10
valid_sources[0x67]	2643	1			T1	32		T6	1		T10	2
valid_sources[0x68]	2958	1			T1	10		T2	2		T3	2
valid_sources[0x69]	2583	1			T1	17		T2	1		T10	4
valid_sources[0x6a]	2676	1			T1	20		T2	1		T5	2
valid_sources[0x6b]	3072	1			T1	26		T10	4		T21	1
valid_sources[0x6c]	3957	1			T1	31		T6	1		T10	36
valid_sources[0x6d]	3876	1			T1	17		T10	6		T54	2
valid_sources[0x6e]	2807	1			T1	23		T5	2		T6	1
valid_sources[0x6f]	9914	1			T1	31		T2	4		T5	1
valid_sources[0x70]	4338	1			T1	19		T3	2		T5	1
valid_sources[0x71]	2795	1			T1	23		T6	2		T10	11
valid_sources[0x72]	3022	1			T1	23		T2	1		T5	1
valid_sources[0x73]	2511	1			T1	25		T6	1		T10	14
valid_sources[0x74]	2793	1			T1	27		T10	4		T37	9
valid_sources[0x75]	2839	1			T1	25		T5	3		T6	1
valid_sources[0x76]	2911	1			T1	14		T10	12		T21	1
valid_sources[0x77]	2919	1			T1	17		T5	1		T10	2
valid_sources[0x78]	3191	1			T1	31		T6	2		T10	15
valid_sources[0x79]	2495	1			T1	22		T4	1		T6	1
valid_sources[0x7a]	2885	1			T1	28		T6	3		T10	17
valid_sources[0x7b]	2701	1			T1	19		T6	1		T10	17
valid_sources[0x7c]	3223	1			T1	21		T5	1		T6	1
valid_sources[0x7d]	2812	1			T1	26		T3	9		T10	13
valid_sources[0x7e]	2780	1			T1	18		T6	1		T10	18
valid_sources[0x7f]	2642	1			T1	18		T2	1		T10	5
valid_sources[0x80]	3107	1			T1	33		T6	1		T10	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

191680

1

T1

685

T2

44

T3

1

values[0x0]

all_enables

biggest_size

60174

1

T1

510

T2

6

T3

23

values[0x1]

all_enables

biggest_size

32936

1

T1

273

T2

1

T3

14