SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34817 | 1 | T24 | 420 | T37 | 393 | T22 | 268 | ||||
others[1] | 34519 | 1 | T24 | 368 | T37 | 375 | T22 | 331 | ||||
others[2] | 34650 | 1 | T24 | 387 | T21 | 1 | T37 | 435 | ||||
others[3] | 57927 | 1 | T24 | 694 | T37 | 672 | T22 | 490 | ||||
false | 19182 | 1 | T1 | 96 | T10 | 68 | T24 | 50 | ||||
true | 29030 | 1 | T1 | 153 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34711 | 1 | T24 | 377 | T37 | 390 | T22 | 310 | ||||
others[1] | 34946 | 1 | T24 | 423 | T37 | 392 | T22 | 306 | ||||
others[2] | 34681 | 1 | T24 | 400 | T37 | 413 | T22 | 281 | ||||
others[3] | 57677 | 1 | T24 | 656 | T37 | 668 | T22 | 504 | ||||
false | 12145 | 1 | T1 | 48 | T10 | 34 | T24 | 50 | ||||
true | 22056 | 1 | T1 | 105 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 634 | 1 | T1 | 2 | T118 | 8 | T38 | 2 | ||||
others[1] | 639 | 1 | T1 | 3 | T5 | 2 | T118 | 2 | ||||
others[2] | 691 | 1 | T8 | 1 | T10 | 1 | T118 | 3 | ||||
others[3] | 1046 | 1 | T1 | 3 | T8 | 2 | T118 | 14 | ||||
false | 13048 | 1 | T1 | 84 | T2 | 1 | T3 | 1 | ||||
true | 3853 | 1 | T1 | 19 | T8 | 5 | T10 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |